1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sm8250.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/phy/phy-qcom-qmp.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/power/qcom,rpmhpd.h>
21 #include <dt-bindings/soc/qcom,apr.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/sound/qcom,q6afe.h>
24 #include <dt-bindings/thermal/thermal.h>
25 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
26 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
27
28 / {
29 interrupt-parent = <&intc>;
30
31 #address-cells = <2>;
32 #size-cells = <2>;
33
34 aliases {
35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 i2c3 = &i2c3;
39 i2c4 = &i2c4;
40 i2c5 = &i2c5;
41 i2c6 = &i2c6;
42 i2c7 = &i2c7;
43 i2c8 = &i2c8;
44 i2c9 = &i2c9;
45 i2c10 = &i2c10;
46 i2c11 = &i2c11;
47 i2c12 = &i2c12;
48 i2c13 = &i2c13;
49 i2c14 = &i2c14;
50 i2c15 = &i2c15;
51 i2c16 = &i2c16;
52 i2c17 = &i2c17;
53 i2c18 = &i2c18;
54 i2c19 = &i2c19;
55 spi0 = &spi0;
56 spi1 = &spi1;
57 spi2 = &spi2;
58 spi3 = &spi3;
59 spi4 = &spi4;
60 spi5 = &spi5;
61 spi6 = &spi6;
62 spi7 = &spi7;
63 spi8 = &spi8;
64 spi9 = &spi9;
65 spi10 = &spi10;
66 spi11 = &spi11;
67 spi12 = &spi12;
68 spi13 = &spi13;
69 spi14 = &spi14;
70 spi15 = &spi15;
71 spi16 = &spi16;
72 spi17 = &spi17;
73 spi18 = &spi18;
74 spi19 = &spi19;
75 };
76
77 chosen { };
78
79 clocks {
80 xo_board: xo-board {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <38400000>;
84 clock-output-names = "xo_board";
85 };
86
87 sleep_clk: sleep-clk {
88 compatible = "fixed-clock";
89 clock-frequency = <32768>;
90 #clock-cells = <0>;
91 };
92 };
93
94 cpus {
95 #address-cells = <2>;
96 #size-cells = <0>;
97
98 CPU0: cpu@0 {
99 device_type = "cpu";
100 compatible = "qcom,kryo485";
101 reg = <0x0 0x0>;
102 clocks = <&cpufreq_hw 0>;
103 enable-method = "psci";
104 capacity-dmips-mhz = <448>;
105 dynamic-power-coefficient = <105>;
106 next-level-cache = <&L2_0>;
107 power-domains = <&CPU_PD0>;
108 power-domain-names = "psci";
109 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = <&cpu0_opp_table>;
111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
112 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
113 #cooling-cells = <2>;
114 L2_0: l2-cache {
115 compatible = "cache";
116 cache-level = <2>;
117 cache-size = <0x20000>;
118 cache-unified;
119 next-level-cache = <&L3_0>;
120 L3_0: l3-cache {
121 compatible = "cache";
122 cache-level = <3>;
123 cache-size = <0x400000>;
124 cache-unified;
125 };
126 };
127 };
128
129 CPU1: cpu@100 {
130 device_type = "cpu";
131 compatible = "qcom,kryo485";
132 reg = <0x0 0x100>;
133 clocks = <&cpufreq_hw 0>;
134 enable-method = "psci";
135 capacity-dmips-mhz = <448>;
136 dynamic-power-coefficient = <105>;
137 next-level-cache = <&L2_100>;
138 power-domains = <&CPU_PD1>;
139 power-domain-names = "psci";
140 qcom,freq-domain = <&cpufreq_hw 0>;
141 operating-points-v2 = <&cpu0_opp_table>;
142 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
143 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
144 #cooling-cells = <2>;
145 L2_100: l2-cache {
146 compatible = "cache";
147 cache-level = <2>;
148 cache-size = <0x20000>;
149 cache-unified;
150 next-level-cache = <&L3_0>;
151 };
152 };
153
154 CPU2: cpu@200 {
155 device_type = "cpu";
156 compatible = "qcom,kryo485";
157 reg = <0x0 0x200>;
158 clocks = <&cpufreq_hw 0>;
159 enable-method = "psci";
160 capacity-dmips-mhz = <448>;
161 dynamic-power-coefficient = <105>;
162 next-level-cache = <&L2_200>;
163 power-domains = <&CPU_PD2>;
164 power-domain-names = "psci";
165 qcom,freq-domain = <&cpufreq_hw 0>;
166 operating-points-v2 = <&cpu0_opp_table>;
167 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
168 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
169 #cooling-cells = <2>;
170 L2_200: l2-cache {
171 compatible = "cache";
172 cache-level = <2>;
173 cache-size = <0x20000>;
174 cache-unified;
175 next-level-cache = <&L3_0>;
176 };
177 };
178
179 CPU3: cpu@300 {
180 device_type = "cpu";
181 compatible = "qcom,kryo485";
182 reg = <0x0 0x300>;
183 clocks = <&cpufreq_hw 0>;
184 enable-method = "psci";
185 capacity-dmips-mhz = <448>;
186 dynamic-power-coefficient = <105>;
187 next-level-cache = <&L2_300>;
188 power-domains = <&CPU_PD3>;
189 power-domain-names = "psci";
190 qcom,freq-domain = <&cpufreq_hw 0>;
191 operating-points-v2 = <&cpu0_opp_table>;
192 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
193 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
194 #cooling-cells = <2>;
195 L2_300: l2-cache {
196 compatible = "cache";
197 cache-level = <2>;
198 cache-size = <0x20000>;
199 cache-unified;
200 next-level-cache = <&L3_0>;
201 };
202 };
203
204 CPU4: cpu@400 {
205 device_type = "cpu";
206 compatible = "qcom,kryo485";
207 reg = <0x0 0x400>;
208 clocks = <&cpufreq_hw 1>;
209 enable-method = "psci";
210 capacity-dmips-mhz = <1024>;
211 dynamic-power-coefficient = <379>;
212 next-level-cache = <&L2_400>;
213 power-domains = <&CPU_PD4>;
214 power-domain-names = "psci";
215 qcom,freq-domain = <&cpufreq_hw 1>;
216 operating-points-v2 = <&cpu4_opp_table>;
217 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
218 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
219 #cooling-cells = <2>;
220 L2_400: l2-cache {
221 compatible = "cache";
222 cache-level = <2>;
223 cache-size = <0x40000>;
224 cache-unified;
225 next-level-cache = <&L3_0>;
226 };
227 };
228
229 CPU5: cpu@500 {
230 device_type = "cpu";
231 compatible = "qcom,kryo485";
232 reg = <0x0 0x500>;
233 clocks = <&cpufreq_hw 1>;
234 enable-method = "psci";
235 capacity-dmips-mhz = <1024>;
236 dynamic-power-coefficient = <379>;
237 next-level-cache = <&L2_500>;
238 power-domains = <&CPU_PD5>;
239 power-domain-names = "psci";
240 qcom,freq-domain = <&cpufreq_hw 1>;
241 operating-points-v2 = <&cpu4_opp_table>;
242 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
243 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
244 #cooling-cells = <2>;
245 L2_500: l2-cache {
246 compatible = "cache";
247 cache-level = <2>;
248 cache-size = <0x40000>;
249 cache-unified;
250 next-level-cache = <&L3_0>;
251 };
252 };
253
254 CPU6: cpu@600 {
255 device_type = "cpu";
256 compatible = "qcom,kryo485";
257 reg = <0x0 0x600>;
258 clocks = <&cpufreq_hw 1>;
259 enable-method = "psci";
260 capacity-dmips-mhz = <1024>;
261 dynamic-power-coefficient = <379>;
262 next-level-cache = <&L2_600>;
263 power-domains = <&CPU_PD6>;
264 power-domain-names = "psci";
265 qcom,freq-domain = <&cpufreq_hw 1>;
266 operating-points-v2 = <&cpu4_opp_table>;
267 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
268 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
269 #cooling-cells = <2>;
270 L2_600: l2-cache {
271 compatible = "cache";
272 cache-level = <2>;
273 cache-size = <0x40000>;
274 cache-unified;
275 next-level-cache = <&L3_0>;
276 };
277 };
278
279 CPU7: cpu@700 {
280 device_type = "cpu";
281 compatible = "qcom,kryo485";
282 reg = <0x0 0x700>;
283 clocks = <&cpufreq_hw 2>;
284 enable-method = "psci";
285 capacity-dmips-mhz = <1024>;
286 dynamic-power-coefficient = <444>;
287 next-level-cache = <&L2_700>;
288 power-domains = <&CPU_PD7>;
289 power-domain-names = "psci";
290 qcom,freq-domain = <&cpufreq_hw 2>;
291 operating-points-v2 = <&cpu7_opp_table>;
292 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
293 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
294 #cooling-cells = <2>;
295 L2_700: l2-cache {
296 compatible = "cache";
297 cache-level = <2>;
298 cache-size = <0x80000>;
299 cache-unified;
300 next-level-cache = <&L3_0>;
301 };
302 };
303
304 cpu-map {
305 cluster0 {
306 core0 {
307 cpu = <&CPU0>;
308 };
309
310 core1 {
311 cpu = <&CPU1>;
312 };
313
314 core2 {
315 cpu = <&CPU2>;
316 };
317
318 core3 {
319 cpu = <&CPU3>;
320 };
321
322 core4 {
323 cpu = <&CPU4>;
324 };
325
326 core5 {
327 cpu = <&CPU5>;
328 };
329
330 core6 {
331 cpu = <&CPU6>;
332 };
333
334 core7 {
335 cpu = <&CPU7>;
336 };
337 };
338 };
339
340 idle-states {
341 entry-method = "psci";
342
343 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
344 compatible = "arm,idle-state";
345 idle-state-name = "silver-rail-power-collapse";
346 arm,psci-suspend-param = <0x40000004>;
347 entry-latency-us = <360>;
348 exit-latency-us = <531>;
349 min-residency-us = <3934>;
350 local-timer-stop;
351 };
352
353 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
354 compatible = "arm,idle-state";
355 idle-state-name = "gold-rail-power-collapse";
356 arm,psci-suspend-param = <0x40000004>;
357 entry-latency-us = <702>;
358 exit-latency-us = <1061>;
359 min-residency-us = <4488>;
360 local-timer-stop;
361 };
362 };
363
364 domain-idle-states {
365 CLUSTER_SLEEP_0: cluster-sleep-0 {
366 compatible = "domain-idle-state";
367 arm,psci-suspend-param = <0x4100c244>;
368 entry-latency-us = <3264>;
369 exit-latency-us = <6562>;
370 min-residency-us = <9987>;
371 };
372 };
373 };
374
375 qup_virt: interconnect-qup-virt {
376 compatible = "qcom,sm8250-qup-virt";
377 #interconnect-cells = <2>;
378 qcom,bcm-voters = <&apps_bcm_voter>;
379 };
380
381 cpu0_opp_table: opp-table-cpu0 {
382 compatible = "operating-points-v2";
383 opp-shared;
384
385 cpu0_opp1: opp-300000000 {
386 opp-hz = /bits/ 64 <300000000>;
387 opp-peak-kBps = <800000 9600000>;
388 };
389
390 cpu0_opp2: opp-403200000 {
391 opp-hz = /bits/ 64 <403200000>;
392 opp-peak-kBps = <800000 9600000>;
393 };
394
395 cpu0_opp3: opp-518400000 {
396 opp-hz = /bits/ 64 <518400000>;
397 opp-peak-kBps = <800000 16588800>;
398 };
399
400 cpu0_opp4: opp-614400000 {
401 opp-hz = /bits/ 64 <614400000>;
402 opp-peak-kBps = <800000 16588800>;
403 };
404
405 cpu0_opp5: opp-691200000 {
406 opp-hz = /bits/ 64 <691200000>;
407 opp-peak-kBps = <800000 19660800>;
408 };
409
410 cpu0_opp6: opp-787200000 {
411 opp-hz = /bits/ 64 <787200000>;
412 opp-peak-kBps = <1804000 19660800>;
413 };
414
415 cpu0_opp7: opp-883200000 {
416 opp-hz = /bits/ 64 <883200000>;
417 opp-peak-kBps = <1804000 23347200>;
418 };
419
420 cpu0_opp8: opp-979200000 {
421 opp-hz = /bits/ 64 <979200000>;
422 opp-peak-kBps = <1804000 26419200>;
423 };
424
425 cpu0_opp9: opp-1075200000 {
426 opp-hz = /bits/ 64 <1075200000>;
427 opp-peak-kBps = <1804000 29491200>;
428 };
429
430 cpu0_opp10: opp-1171200000 {
431 opp-hz = /bits/ 64 <1171200000>;
432 opp-peak-kBps = <1804000 32563200>;
433 };
434
435 cpu0_opp11: opp-1248000000 {
436 opp-hz = /bits/ 64 <1248000000>;
437 opp-peak-kBps = <1804000 36249600>;
438 };
439
440 cpu0_opp12: opp-1344000000 {
441 opp-hz = /bits/ 64 <1344000000>;
442 opp-peak-kBps = <2188000 36249600>;
443 };
444
445 cpu0_opp13: opp-1420800000 {
446 opp-hz = /bits/ 64 <1420800000>;
447 opp-peak-kBps = <2188000 39321600>;
448 };
449
450 cpu0_opp14: opp-1516800000 {
451 opp-hz = /bits/ 64 <1516800000>;
452 opp-peak-kBps = <3072000 42393600>;
453 };
454
455 cpu0_opp15: opp-1612800000 {
456 opp-hz = /bits/ 64 <1612800000>;
457 opp-peak-kBps = <3072000 42393600>;
458 };
459
460 cpu0_opp16: opp-1708800000 {
461 opp-hz = /bits/ 64 <1708800000>;
462 opp-peak-kBps = <4068000 42393600>;
463 };
464
465 cpu0_opp17: opp-1804800000 {
466 opp-hz = /bits/ 64 <1804800000>;
467 opp-peak-kBps = <4068000 42393600>;
468 };
469 };
470
471 cpu4_opp_table: opp-table-cpu4 {
472 compatible = "operating-points-v2";
473 opp-shared;
474
475 cpu4_opp1: opp-710400000 {
476 opp-hz = /bits/ 64 <710400000>;
477 opp-peak-kBps = <1804000 19660800>;
478 };
479
480 cpu4_opp2: opp-825600000 {
481 opp-hz = /bits/ 64 <825600000>;
482 opp-peak-kBps = <2188000 23347200>;
483 };
484
485 cpu4_opp3: opp-940800000 {
486 opp-hz = /bits/ 64 <940800000>;
487 opp-peak-kBps = <2188000 26419200>;
488 };
489
490 cpu4_opp4: opp-1056000000 {
491 opp-hz = /bits/ 64 <1056000000>;
492 opp-peak-kBps = <3072000 26419200>;
493 };
494
495 cpu4_opp5: opp-1171200000 {
496 opp-hz = /bits/ 64 <1171200000>;
497 opp-peak-kBps = <3072000 29491200>;
498 };
499
500 cpu4_opp6: opp-1286400000 {
501 opp-hz = /bits/ 64 <1286400000>;
502 opp-peak-kBps = <4068000 29491200>;
503 };
504
505 cpu4_opp7: opp-1382400000 {
506 opp-hz = /bits/ 64 <1382400000>;
507 opp-peak-kBps = <4068000 32563200>;
508 };
509
510 cpu4_opp8: opp-1478400000 {
511 opp-hz = /bits/ 64 <1478400000>;
512 opp-peak-kBps = <4068000 32563200>;
513 };
514
515 cpu4_opp9: opp-1574400000 {
516 opp-hz = /bits/ 64 <1574400000>;
517 opp-peak-kBps = <5412000 39321600>;
518 };
519
520 cpu4_opp10: opp-1670400000 {
521 opp-hz = /bits/ 64 <1670400000>;
522 opp-peak-kBps = <5412000 42393600>;
523 };
524
525 cpu4_opp11: opp-1766400000 {
526 opp-hz = /bits/ 64 <1766400000>;
527 opp-peak-kBps = <5412000 45465600>;
528 };
529
530 cpu4_opp12: opp-1862400000 {
531 opp-hz = /bits/ 64 <1862400000>;
532 opp-peak-kBps = <6220000 45465600>;
533 };
534
535 cpu4_opp13: opp-1958400000 {
536 opp-hz = /bits/ 64 <1958400000>;
537 opp-peak-kBps = <6220000 48537600>;
538 };
539
540 cpu4_opp14: opp-2054400000 {
541 opp-hz = /bits/ 64 <2054400000>;
542 opp-peak-kBps = <7216000 48537600>;
543 };
544
545 cpu4_opp15: opp-2150400000 {
546 opp-hz = /bits/ 64 <2150400000>;
547 opp-peak-kBps = <7216000 51609600>;
548 };
549
550 cpu4_opp16: opp-2246400000 {
551 opp-hz = /bits/ 64 <2246400000>;
552 opp-peak-kBps = <7216000 51609600>;
553 };
554
555 cpu4_opp17: opp-2342400000 {
556 opp-hz = /bits/ 64 <2342400000>;
557 opp-peak-kBps = <8368000 51609600>;
558 };
559
560 cpu4_opp18: opp-2419200000 {
561 opp-hz = /bits/ 64 <2419200000>;
562 opp-peak-kBps = <8368000 51609600>;
563 };
564 };
565
566 cpu7_opp_table: opp-table-cpu7 {
567 compatible = "operating-points-v2";
568 opp-shared;
569
570 cpu7_opp1: opp-844800000 {
571 opp-hz = /bits/ 64 <844800000>;
572 opp-peak-kBps = <2188000 19660800>;
573 };
574
575 cpu7_opp2: opp-960000000 {
576 opp-hz = /bits/ 64 <960000000>;
577 opp-peak-kBps = <2188000 26419200>;
578 };
579
580 cpu7_opp3: opp-1075200000 {
581 opp-hz = /bits/ 64 <1075200000>;
582 opp-peak-kBps = <3072000 26419200>;
583 };
584
585 cpu7_opp4: opp-1190400000 {
586 opp-hz = /bits/ 64 <1190400000>;
587 opp-peak-kBps = <3072000 29491200>;
588 };
589
590 cpu7_opp5: opp-1305600000 {
591 opp-hz = /bits/ 64 <1305600000>;
592 opp-peak-kBps = <4068000 32563200>;
593 };
594
595 cpu7_opp6: opp-1401600000 {
596 opp-hz = /bits/ 64 <1401600000>;
597 opp-peak-kBps = <4068000 32563200>;
598 };
599
600 cpu7_opp7: opp-1516800000 {
601 opp-hz = /bits/ 64 <1516800000>;
602 opp-peak-kBps = <4068000 36249600>;
603 };
604
605 cpu7_opp8: opp-1632000000 {
606 opp-hz = /bits/ 64 <1632000000>;
607 opp-peak-kBps = <5412000 39321600>;
608 };
609
610 cpu7_opp9: opp-1747200000 {
611 opp-hz = /bits/ 64 <1708800000>;
612 opp-peak-kBps = <5412000 42393600>;
613 };
614
615 cpu7_opp10: opp-1862400000 {
616 opp-hz = /bits/ 64 <1862400000>;
617 opp-peak-kBps = <6220000 45465600>;
618 };
619
620 cpu7_opp11: opp-1977600000 {
621 opp-hz = /bits/ 64 <1977600000>;
622 opp-peak-kBps = <6220000 48537600>;
623 };
624
625 cpu7_opp12: opp-2073600000 {
626 opp-hz = /bits/ 64 <2073600000>;
627 opp-peak-kBps = <7216000 48537600>;
628 };
629
630 cpu7_opp13: opp-2169600000 {
631 opp-hz = /bits/ 64 <2169600000>;
632 opp-peak-kBps = <7216000 51609600>;
633 };
634
635 cpu7_opp14: opp-2265600000 {
636 opp-hz = /bits/ 64 <2265600000>;
637 opp-peak-kBps = <7216000 51609600>;
638 };
639
640 cpu7_opp15: opp-2361600000 {
641 opp-hz = /bits/ 64 <2361600000>;
642 opp-peak-kBps = <8368000 51609600>;
643 };
644
645 cpu7_opp16: opp-2457600000 {
646 opp-hz = /bits/ 64 <2457600000>;
647 opp-peak-kBps = <8368000 51609600>;
648 };
649
650 cpu7_opp17: opp-2553600000 {
651 opp-hz = /bits/ 64 <2553600000>;
652 opp-peak-kBps = <8368000 51609600>;
653 };
654
655 cpu7_opp18: opp-2649600000 {
656 opp-hz = /bits/ 64 <2649600000>;
657 opp-peak-kBps = <8368000 51609600>;
658 };
659
660 cpu7_opp19: opp-2745600000 {
661 opp-hz = /bits/ 64 <2745600000>;
662 opp-peak-kBps = <8368000 51609600>;
663 };
664
665 cpu7_opp20: opp-2841600000 {
666 opp-hz = /bits/ 64 <2841600000>;
667 opp-peak-kBps = <8368000 51609600>;
668 };
669 };
670
671 firmware {
672 scm: scm {
673 compatible = "qcom,scm-sm8250", "qcom,scm";
674 qcom,dload-mode = <&tcsr 0x13000>;
675 #reset-cells = <1>;
676 };
677 };
678
679 memory@80000000 {
680 device_type = "memory";
681 /* We expect the bootloader to fill in the size */
682 reg = <0x0 0x80000000 0x0 0x0>;
683 };
684
685 pmu {
686 compatible = "arm,armv8-pmuv3";
687 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
688 };
689
690 psci {
691 compatible = "arm,psci-1.0";
692 method = "smc";
693
694 CPU_PD0: power-domain-cpu0 {
695 #power-domain-cells = <0>;
696 power-domains = <&CLUSTER_PD>;
697 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
698 };
699
700 CPU_PD1: power-domain-cpu1 {
701 #power-domain-cells = <0>;
702 power-domains = <&CLUSTER_PD>;
703 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
704 };
705
706 CPU_PD2: power-domain-cpu2 {
707 #power-domain-cells = <0>;
708 power-domains = <&CLUSTER_PD>;
709 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
710 };
711
712 CPU_PD3: power-domain-cpu3 {
713 #power-domain-cells = <0>;
714 power-domains = <&CLUSTER_PD>;
715 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
716 };
717
718 CPU_PD4: power-domain-cpu4 {
719 #power-domain-cells = <0>;
720 power-domains = <&CLUSTER_PD>;
721 domain-idle-states = <&BIG_CPU_SLEEP_0>;
722 };
723
724 CPU_PD5: power-domain-cpu5 {
725 #power-domain-cells = <0>;
726 power-domains = <&CLUSTER_PD>;
727 domain-idle-states = <&BIG_CPU_SLEEP_0>;
728 };
729
730 CPU_PD6: power-domain-cpu6 {
731 #power-domain-cells = <0>;
732 power-domains = <&CLUSTER_PD>;
733 domain-idle-states = <&BIG_CPU_SLEEP_0>;
734 };
735
736 CPU_PD7: power-domain-cpu7 {
737 #power-domain-cells = <0>;
738 power-domains = <&CLUSTER_PD>;
739 domain-idle-states = <&BIG_CPU_SLEEP_0>;
740 };
741
742 CLUSTER_PD: power-domain-cpu-cluster0 {
743 #power-domain-cells = <0>;
744 domain-idle-states = <&CLUSTER_SLEEP_0>;
745 };
746 };
747
748 qup_opp_table: opp-table-qup {
749 compatible = "operating-points-v2";
750
751 opp-50000000 {
752 opp-hz = /bits/ 64 <50000000>;
753 required-opps = <&rpmhpd_opp_min_svs>;
754 };
755
756 opp-75000000 {
757 opp-hz = /bits/ 64 <75000000>;
758 required-opps = <&rpmhpd_opp_low_svs>;
759 };
760
761 opp-120000000 {
762 opp-hz = /bits/ 64 <120000000>;
763 required-opps = <&rpmhpd_opp_svs>;
764 };
765 };
766
767 reserved-memory {
768 #address-cells = <2>;
769 #size-cells = <2>;
770 ranges;
771
772 hyp_mem: memory@80000000 {
773 reg = <0x0 0x80000000 0x0 0x600000>;
774 no-map;
775 };
776
777 xbl_aop_mem: memory@80700000 {
778 reg = <0x0 0x80700000 0x0 0x160000>;
779 no-map;
780 };
781
782 cmd_db: memory@80860000 {
783 compatible = "qcom,cmd-db";
784 reg = <0x0 0x80860000 0x0 0x20000>;
785 no-map;
786 };
787
788 smem_mem: memory@80900000 {
789 reg = <0x0 0x80900000 0x0 0x200000>;
790 no-map;
791 };
792
793 removed_mem: memory@80b00000 {
794 reg = <0x0 0x80b00000 0x0 0x5300000>;
795 no-map;
796 };
797
798 camera_mem: memory@86200000 {
799 reg = <0x0 0x86200000 0x0 0x500000>;
800 no-map;
801 };
802
803 wlan_mem: memory@86700000 {
804 reg = <0x0 0x86700000 0x0 0x100000>;
805 no-map;
806 };
807
808 ipa_fw_mem: memory@86800000 {
809 reg = <0x0 0x86800000 0x0 0x10000>;
810 no-map;
811 };
812
813 ipa_gsi_mem: memory@86810000 {
814 reg = <0x0 0x86810000 0x0 0xa000>;
815 no-map;
816 };
817
818 gpu_mem: memory@8681a000 {
819 reg = <0x0 0x8681a000 0x0 0x2000>;
820 no-map;
821 };
822
823 npu_mem: memory@86900000 {
824 reg = <0x0 0x86900000 0x0 0x500000>;
825 no-map;
826 };
827
828 video_mem: memory@86e00000 {
829 reg = <0x0 0x86e00000 0x0 0x500000>;
830 no-map;
831 };
832
833 cvp_mem: memory@87300000 {
834 reg = <0x0 0x87300000 0x0 0x500000>;
835 no-map;
836 };
837
838 cdsp_mem: memory@87800000 {
839 reg = <0x0 0x87800000 0x0 0x1400000>;
840 no-map;
841 };
842
843 slpi_mem: memory@88c00000 {
844 reg = <0x0 0x88c00000 0x0 0x1500000>;
845 no-map;
846 };
847
848 adsp_mem: memory@8a100000 {
849 reg = <0x0 0x8a100000 0x0 0x1d00000>;
850 no-map;
851 };
852
853 spss_mem: memory@8be00000 {
854 reg = <0x0 0x8be00000 0x0 0x100000>;
855 no-map;
856 };
857
858 cdsp_secure_heap: memory@8bf00000 {
859 reg = <0x0 0x8bf00000 0x0 0x4600000>;
860 no-map;
861 };
862 };
863
864 smem {
865 compatible = "qcom,smem";
866 memory-region = <&smem_mem>;
867 hwlocks = <&tcsr_mutex 3>;
868 };
869
870 smp2p-adsp {
871 compatible = "qcom,smp2p";
872 qcom,smem = <443>, <429>;
873 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
874 IPCC_MPROC_SIGNAL_SMP2P
875 IRQ_TYPE_EDGE_RISING>;
876 mboxes = <&ipcc IPCC_CLIENT_LPASS
877 IPCC_MPROC_SIGNAL_SMP2P>;
878
879 qcom,local-pid = <0>;
880 qcom,remote-pid = <2>;
881
882 smp2p_adsp_out: master-kernel {
883 qcom,entry-name = "master-kernel";
884 #qcom,smem-state-cells = <1>;
885 };
886
887 smp2p_adsp_in: slave-kernel {
888 qcom,entry-name = "slave-kernel";
889 interrupt-controller;
890 #interrupt-cells = <2>;
891 };
892 };
893
894 smp2p-cdsp {
895 compatible = "qcom,smp2p";
896 qcom,smem = <94>, <432>;
897 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
898 IPCC_MPROC_SIGNAL_SMP2P
899 IRQ_TYPE_EDGE_RISING>;
900 mboxes = <&ipcc IPCC_CLIENT_CDSP
901 IPCC_MPROC_SIGNAL_SMP2P>;
902
903 qcom,local-pid = <0>;
904 qcom,remote-pid = <5>;
905
906 smp2p_cdsp_out: master-kernel {
907 qcom,entry-name = "master-kernel";
908 #qcom,smem-state-cells = <1>;
909 };
910
911 smp2p_cdsp_in: slave-kernel {
912 qcom,entry-name = "slave-kernel";
913 interrupt-controller;
914 #interrupt-cells = <2>;
915 };
916 };
917
918 smp2p-slpi {
919 compatible = "qcom,smp2p";
920 qcom,smem = <481>, <430>;
921 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
922 IPCC_MPROC_SIGNAL_SMP2P
923 IRQ_TYPE_EDGE_RISING>;
924 mboxes = <&ipcc IPCC_CLIENT_SLPI
925 IPCC_MPROC_SIGNAL_SMP2P>;
926
927 qcom,local-pid = <0>;
928 qcom,remote-pid = <3>;
929
930 smp2p_slpi_out: master-kernel {
931 qcom,entry-name = "master-kernel";
932 #qcom,smem-state-cells = <1>;
933 };
934
935 smp2p_slpi_in: slave-kernel {
936 qcom,entry-name = "slave-kernel";
937 interrupt-controller;
938 #interrupt-cells = <2>;
939 };
940 };
941
942 soc: soc@0 {
943 #address-cells = <2>;
944 #size-cells = <2>;
945 ranges = <0 0 0 0 0x10 0>;
946 dma-ranges = <0 0 0 0 0x10 0>;
947 compatible = "simple-bus";
948
949 gcc: clock-controller@100000 {
950 compatible = "qcom,gcc-sm8250";
951 reg = <0x0 0x00100000 0x0 0x1f0000>;
952 #clock-cells = <1>;
953 #reset-cells = <1>;
954 #power-domain-cells = <1>;
955 clock-names = "bi_tcxo",
956 "bi_tcxo_ao",
957 "sleep_clk";
958 clocks = <&rpmhcc RPMH_CXO_CLK>,
959 <&rpmhcc RPMH_CXO_CLK_A>,
960 <&sleep_clk>;
961 };
962
963 ipcc: mailbox@408000 {
964 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
965 reg = <0 0x00408000 0 0x1000>;
966 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
967 interrupt-controller;
968 #interrupt-cells = <3>;
969 #mbox-cells = <2>;
970 };
971
972 qfprom: efuse@784000 {
973 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
974 reg = <0 0x00784000 0 0x8ff>;
975 #address-cells = <1>;
976 #size-cells = <1>;
977
978 gpu_speed_bin: gpu-speed-bin@19b {
979 reg = <0x19b 0x1>;
980 bits = <5 3>;
981 };
982 };
983
984 rng: rng@793000 {
985 compatible = "qcom,prng-ee";
986 reg = <0 0x00793000 0 0x1000>;
987 clocks = <&gcc GCC_PRNG_AHB_CLK>;
988 clock-names = "core";
989 };
990
991 gpi_dma2: dma-controller@800000 {
992 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
993 reg = <0 0x00800000 0 0x70000>;
994 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1002 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1004 dma-channels = <10>;
1005 dma-channel-mask = <0x3f>;
1006 iommus = <&apps_smmu 0x76 0x0>;
1007 #dma-cells = <3>;
1008 status = "disabled";
1009 };
1010
1011 qupv3_id_2: geniqup@8c0000 {
1012 compatible = "qcom,geni-se-qup";
1013 reg = <0x0 0x008c0000 0x0 0x6000>;
1014 clock-names = "m-ahb", "s-ahb";
1015 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1016 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1017 #address-cells = <2>;
1018 #size-cells = <2>;
1019 iommus = <&apps_smmu 0x63 0x0>;
1020 ranges;
1021 status = "disabled";
1022
1023 i2c14: i2c@880000 {
1024 compatible = "qcom,geni-i2c";
1025 reg = <0 0x00880000 0 0x4000>;
1026 clock-names = "se";
1027 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&qup_i2c14_default>;
1030 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1031 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1032 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1033 dma-names = "tx", "rx";
1034 power-domains = <&rpmhpd SM8250_CX>;
1035 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1036 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1037 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1038 interconnect-names = "qup-core",
1039 "qup-config",
1040 "qup-memory";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 status = "disabled";
1044 };
1045
1046 spi14: spi@880000 {
1047 compatible = "qcom,geni-spi";
1048 reg = <0 0x00880000 0 0x4000>;
1049 clock-names = "se";
1050 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1051 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1052 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1053 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1054 dma-names = "tx", "rx";
1055 power-domains = <&rpmhpd RPMHPD_CX>;
1056 operating-points-v2 = <&qup_opp_table>;
1057 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1058 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1059 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1060 interconnect-names = "qup-core",
1061 "qup-config",
1062 "qup-memory";
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1065 status = "disabled";
1066 };
1067
1068 i2c15: i2c@884000 {
1069 compatible = "qcom,geni-i2c";
1070 reg = <0 0x00884000 0 0x4000>;
1071 clock-names = "se";
1072 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1073 pinctrl-names = "default";
1074 pinctrl-0 = <&qup_i2c15_default>;
1075 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1076 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1077 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1078 dma-names = "tx", "rx";
1079 power-domains = <&rpmhpd SM8250_CX>;
1080 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1081 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1082 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1083 interconnect-names = "qup-core",
1084 "qup-config",
1085 "qup-memory";
1086 #address-cells = <1>;
1087 #size-cells = <0>;
1088 status = "disabled";
1089 };
1090
1091 spi15: spi@884000 {
1092 compatible = "qcom,geni-spi";
1093 reg = <0 0x00884000 0 0x4000>;
1094 clock-names = "se";
1095 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1096 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1097 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1098 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1099 dma-names = "tx", "rx";
1100 power-domains = <&rpmhpd RPMHPD_CX>;
1101 operating-points-v2 = <&qup_opp_table>;
1102 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1103 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1104 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1105 interconnect-names = "qup-core",
1106 "qup-config",
1107 "qup-memory";
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110 status = "disabled";
1111 };
1112
1113 i2c16: i2c@888000 {
1114 compatible = "qcom,geni-i2c";
1115 reg = <0 0x00888000 0 0x4000>;
1116 clock-names = "se";
1117 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&qup_i2c16_default>;
1120 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1121 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1122 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1123 dma-names = "tx", "rx";
1124 power-domains = <&rpmhpd SM8250_CX>;
1125 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1126 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1127 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1128 interconnect-names = "qup-core",
1129 "qup-config",
1130 "qup-memory";
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133 status = "disabled";
1134 };
1135
1136 spi16: spi@888000 {
1137 compatible = "qcom,geni-spi";
1138 reg = <0 0x00888000 0 0x4000>;
1139 clock-names = "se";
1140 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1141 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1142 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1143 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1144 dma-names = "tx", "rx";
1145 power-domains = <&rpmhpd RPMHPD_CX>;
1146 operating-points-v2 = <&qup_opp_table>;
1147 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1148 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1149 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1150 interconnect-names = "qup-core",
1151 "qup-config",
1152 "qup-memory";
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1155 status = "disabled";
1156 };
1157
1158 i2c17: i2c@88c000 {
1159 compatible = "qcom,geni-i2c";
1160 reg = <0 0x0088c000 0 0x4000>;
1161 clock-names = "se";
1162 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&qup_i2c17_default>;
1165 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1166 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1167 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1168 dma-names = "tx", "rx";
1169 power-domains = <&rpmhpd SM8250_CX>;
1170 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1171 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1172 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1173 interconnect-names = "qup-core",
1174 "qup-config",
1175 "qup-memory";
1176 #address-cells = <1>;
1177 #size-cells = <0>;
1178 status = "disabled";
1179 };
1180
1181 spi17: spi@88c000 {
1182 compatible = "qcom,geni-spi";
1183 reg = <0 0x0088c000 0 0x4000>;
1184 clock-names = "se";
1185 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1186 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1187 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1188 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1189 dma-names = "tx", "rx";
1190 power-domains = <&rpmhpd RPMHPD_CX>;
1191 operating-points-v2 = <&qup_opp_table>;
1192 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1193 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1194 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1195 interconnect-names = "qup-core",
1196 "qup-config",
1197 "qup-memory";
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1200 status = "disabled";
1201 };
1202
1203 uart17: serial@88c000 {
1204 compatible = "qcom,geni-uart";
1205 reg = <0 0x0088c000 0 0x4000>;
1206 clock-names = "se";
1207 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1208 pinctrl-names = "default";
1209 pinctrl-0 = <&qup_uart17_default>;
1210 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1211 power-domains = <&rpmhpd RPMHPD_CX>;
1212 operating-points-v2 = <&qup_opp_table>;
1213 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1214 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1215 interconnect-names = "qup-core",
1216 "qup-config";
1217 status = "disabled";
1218 };
1219
1220 i2c18: i2c@890000 {
1221 compatible = "qcom,geni-i2c";
1222 reg = <0 0x00890000 0 0x4000>;
1223 clock-names = "se";
1224 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1225 pinctrl-names = "default";
1226 pinctrl-0 = <&qup_i2c18_default>;
1227 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1228 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1229 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1230 dma-names = "tx", "rx";
1231 power-domains = <&rpmhpd SM8250_CX>;
1232 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1233 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1234 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1235 interconnect-names = "qup-core",
1236 "qup-config",
1237 "qup-memory";
1238 #address-cells = <1>;
1239 #size-cells = <0>;
1240 status = "disabled";
1241 };
1242
1243 spi18: spi@890000 {
1244 compatible = "qcom,geni-spi";
1245 reg = <0 0x00890000 0 0x4000>;
1246 clock-names = "se";
1247 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1248 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1249 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1250 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1251 dma-names = "tx", "rx";
1252 power-domains = <&rpmhpd RPMHPD_CX>;
1253 operating-points-v2 = <&qup_opp_table>;
1254 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1255 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1256 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1257 interconnect-names = "qup-core",
1258 "qup-config",
1259 "qup-memory";
1260 #address-cells = <1>;
1261 #size-cells = <0>;
1262 status = "disabled";
1263 };
1264
1265 uart18: serial@890000 {
1266 compatible = "qcom,geni-uart";
1267 reg = <0 0x00890000 0 0x4000>;
1268 clock-names = "se";
1269 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1270 pinctrl-names = "default";
1271 pinctrl-0 = <&qup_uart18_default>;
1272 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1273 power-domains = <&rpmhpd RPMHPD_CX>;
1274 operating-points-v2 = <&qup_opp_table>;
1275 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1276 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1277 interconnect-names = "qup-core",
1278 "qup-config";
1279 status = "disabled";
1280 };
1281
1282 i2c19: i2c@894000 {
1283 compatible = "qcom,geni-i2c";
1284 reg = <0 0x00894000 0 0x4000>;
1285 clock-names = "se";
1286 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1287 pinctrl-names = "default";
1288 pinctrl-0 = <&qup_i2c19_default>;
1289 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1290 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1291 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1292 dma-names = "tx", "rx";
1293 power-domains = <&rpmhpd SM8250_CX>;
1294 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1295 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1296 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1297 interconnect-names = "qup-core",
1298 "qup-config",
1299 "qup-memory";
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1302 status = "disabled";
1303 };
1304
1305 spi19: spi@894000 {
1306 compatible = "qcom,geni-spi";
1307 reg = <0 0x00894000 0 0x4000>;
1308 clock-names = "se";
1309 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1310 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1311 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1312 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1313 dma-names = "tx", "rx";
1314 power-domains = <&rpmhpd RPMHPD_CX>;
1315 operating-points-v2 = <&qup_opp_table>;
1316 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1317 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1318 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1319 interconnect-names = "qup-core",
1320 "qup-config",
1321 "qup-memory";
1322 #address-cells = <1>;
1323 #size-cells = <0>;
1324 status = "disabled";
1325 };
1326 };
1327
1328 gpi_dma0: dma-controller@900000 {
1329 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1330 reg = <0 0x00900000 0 0x70000>;
1331 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1343 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1344 dma-channels = <15>;
1345 dma-channel-mask = <0x7ff>;
1346 iommus = <&apps_smmu 0x5b6 0x0>;
1347 #dma-cells = <3>;
1348 status = "disabled";
1349 };
1350
1351 qupv3_id_0: geniqup@9c0000 {
1352 compatible = "qcom,geni-se-qup";
1353 reg = <0x0 0x009c0000 0x0 0x6000>;
1354 clock-names = "m-ahb", "s-ahb";
1355 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1356 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1357 #address-cells = <2>;
1358 #size-cells = <2>;
1359 iommus = <&apps_smmu 0x5a3 0x0>;
1360 ranges;
1361 status = "disabled";
1362
1363 i2c0: i2c@980000 {
1364 compatible = "qcom,geni-i2c";
1365 reg = <0 0x00980000 0 0x4000>;
1366 clock-names = "se";
1367 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1368 pinctrl-names = "default";
1369 pinctrl-0 = <&qup_i2c0_default>;
1370 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1371 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1372 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1373 dma-names = "tx", "rx";
1374 power-domains = <&rpmhpd SM8250_CX>;
1375 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1376 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1377 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1378 interconnect-names = "qup-core",
1379 "qup-config",
1380 "qup-memory";
1381 #address-cells = <1>;
1382 #size-cells = <0>;
1383 status = "disabled";
1384 };
1385
1386 spi0: spi@980000 {
1387 compatible = "qcom,geni-spi";
1388 reg = <0 0x00980000 0 0x4000>;
1389 clock-names = "se";
1390 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1391 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1392 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1393 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1394 dma-names = "tx", "rx";
1395 power-domains = <&rpmhpd RPMHPD_CX>;
1396 operating-points-v2 = <&qup_opp_table>;
1397 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1398 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1399 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1400 interconnect-names = "qup-core",
1401 "qup-config",
1402 "qup-memory";
1403 #address-cells = <1>;
1404 #size-cells = <0>;
1405 status = "disabled";
1406 };
1407
1408 i2c1: i2c@984000 {
1409 compatible = "qcom,geni-i2c";
1410 reg = <0 0x00984000 0 0x4000>;
1411 clock-names = "se";
1412 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1413 pinctrl-names = "default";
1414 pinctrl-0 = <&qup_i2c1_default>;
1415 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1416 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1417 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1418 dma-names = "tx", "rx";
1419 power-domains = <&rpmhpd SM8250_CX>;
1420 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1421 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1422 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1423 interconnect-names = "qup-core",
1424 "qup-config",
1425 "qup-memory";
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1428 status = "disabled";
1429 };
1430
1431 spi1: spi@984000 {
1432 compatible = "qcom,geni-spi";
1433 reg = <0 0x00984000 0 0x4000>;
1434 clock-names = "se";
1435 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1436 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1437 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1438 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1439 dma-names = "tx", "rx";
1440 power-domains = <&rpmhpd RPMHPD_CX>;
1441 operating-points-v2 = <&qup_opp_table>;
1442 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1443 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1444 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1445 interconnect-names = "qup-core",
1446 "qup-config",
1447 "qup-memory";
1448 #address-cells = <1>;
1449 #size-cells = <0>;
1450 status = "disabled";
1451 };
1452
1453 i2c2: i2c@988000 {
1454 compatible = "qcom,geni-i2c";
1455 reg = <0 0x00988000 0 0x4000>;
1456 clock-names = "se";
1457 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1458 pinctrl-names = "default";
1459 pinctrl-0 = <&qup_i2c2_default>;
1460 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1461 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1462 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1463 dma-names = "tx", "rx";
1464 power-domains = <&rpmhpd SM8250_CX>;
1465 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1466 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1467 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1468 interconnect-names = "qup-core",
1469 "qup-config",
1470 "qup-memory";
1471 #address-cells = <1>;
1472 #size-cells = <0>;
1473 status = "disabled";
1474 };
1475
1476 spi2: spi@988000 {
1477 compatible = "qcom,geni-spi";
1478 reg = <0 0x00988000 0 0x4000>;
1479 clock-names = "se";
1480 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1481 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1482 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1483 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1484 dma-names = "tx", "rx";
1485 power-domains = <&rpmhpd RPMHPD_CX>;
1486 operating-points-v2 = <&qup_opp_table>;
1487 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1488 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1489 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1490 interconnect-names = "qup-core",
1491 "qup-config",
1492 "qup-memory";
1493 #address-cells = <1>;
1494 #size-cells = <0>;
1495 status = "disabled";
1496 };
1497
1498 uart2: serial@988000 {
1499 compatible = "qcom,geni-debug-uart";
1500 reg = <0 0x00988000 0 0x4000>;
1501 clock-names = "se";
1502 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1503 pinctrl-names = "default";
1504 pinctrl-0 = <&qup_uart2_default>;
1505 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1506 power-domains = <&rpmhpd RPMHPD_CX>;
1507 operating-points-v2 = <&qup_opp_table>;
1508 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1509 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1510 interconnect-names = "qup-core",
1511 "qup-config";
1512 status = "disabled";
1513 };
1514
1515 i2c3: i2c@98c000 {
1516 compatible = "qcom,geni-i2c";
1517 reg = <0 0x0098c000 0 0x4000>;
1518 clock-names = "se";
1519 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1520 pinctrl-names = "default";
1521 pinctrl-0 = <&qup_i2c3_default>;
1522 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1523 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1524 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1525 dma-names = "tx", "rx";
1526 power-domains = <&rpmhpd SM8250_CX>;
1527 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1528 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1529 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1530 interconnect-names = "qup-core",
1531 "qup-config",
1532 "qup-memory";
1533 #address-cells = <1>;
1534 #size-cells = <0>;
1535 status = "disabled";
1536 };
1537
1538 spi3: spi@98c000 {
1539 compatible = "qcom,geni-spi";
1540 reg = <0 0x0098c000 0 0x4000>;
1541 clock-names = "se";
1542 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1543 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1544 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1545 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1546 dma-names = "tx", "rx";
1547 power-domains = <&rpmhpd RPMHPD_CX>;
1548 operating-points-v2 = <&qup_opp_table>;
1549 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1550 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1551 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1552 interconnect-names = "qup-core",
1553 "qup-config",
1554 "qup-memory";
1555 #address-cells = <1>;
1556 #size-cells = <0>;
1557 status = "disabled";
1558 };
1559
1560 i2c4: i2c@990000 {
1561 compatible = "qcom,geni-i2c";
1562 reg = <0 0x00990000 0 0x4000>;
1563 clock-names = "se";
1564 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&qup_i2c4_default>;
1567 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1568 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1569 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1570 dma-names = "tx", "rx";
1571 power-domains = <&rpmhpd SM8250_CX>;
1572 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1573 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1574 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1575 interconnect-names = "qup-core",
1576 "qup-config",
1577 "qup-memory";
1578 #address-cells = <1>;
1579 #size-cells = <0>;
1580 status = "disabled";
1581 };
1582
1583 spi4: spi@990000 {
1584 compatible = "qcom,geni-spi";
1585 reg = <0 0x00990000 0 0x4000>;
1586 clock-names = "se";
1587 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1588 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1589 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1590 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1591 dma-names = "tx", "rx";
1592 power-domains = <&rpmhpd RPMHPD_CX>;
1593 operating-points-v2 = <&qup_opp_table>;
1594 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1595 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1596 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1597 interconnect-names = "qup-core",
1598 "qup-config",
1599 "qup-memory";
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1602 status = "disabled";
1603 };
1604
1605 i2c5: i2c@994000 {
1606 compatible = "qcom,geni-i2c";
1607 reg = <0 0x00994000 0 0x4000>;
1608 clock-names = "se";
1609 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1610 pinctrl-names = "default";
1611 pinctrl-0 = <&qup_i2c5_default>;
1612 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1613 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1614 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1615 dma-names = "tx", "rx";
1616 power-domains = <&rpmhpd SM8250_CX>;
1617 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1618 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1619 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1620 interconnect-names = "qup-core",
1621 "qup-config",
1622 "qup-memory";
1623 #address-cells = <1>;
1624 #size-cells = <0>;
1625 status = "disabled";
1626 };
1627
1628 spi5: spi@994000 {
1629 compatible = "qcom,geni-spi";
1630 reg = <0 0x00994000 0 0x4000>;
1631 clock-names = "se";
1632 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1633 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1634 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1635 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1636 dma-names = "tx", "rx";
1637 power-domains = <&rpmhpd RPMHPD_CX>;
1638 operating-points-v2 = <&qup_opp_table>;
1639 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1640 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1641 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1642 interconnect-names = "qup-core",
1643 "qup-config",
1644 "qup-memory";
1645 #address-cells = <1>;
1646 #size-cells = <0>;
1647 status = "disabled";
1648 };
1649
1650 i2c6: i2c@998000 {
1651 compatible = "qcom,geni-i2c";
1652 reg = <0 0x00998000 0 0x4000>;
1653 clock-names = "se";
1654 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1655 pinctrl-names = "default";
1656 pinctrl-0 = <&qup_i2c6_default>;
1657 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1658 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1659 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1660 dma-names = "tx", "rx";
1661 power-domains = <&rpmhpd SM8250_CX>;
1662 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1663 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1664 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1665 interconnect-names = "qup-core",
1666 "qup-config",
1667 "qup-memory";
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1670 status = "disabled";
1671 };
1672
1673 spi6: spi@998000 {
1674 compatible = "qcom,geni-spi";
1675 reg = <0 0x00998000 0 0x4000>;
1676 clock-names = "se";
1677 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1678 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1679 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1680 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1681 dma-names = "tx", "rx";
1682 power-domains = <&rpmhpd RPMHPD_CX>;
1683 operating-points-v2 = <&qup_opp_table>;
1684 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1685 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1686 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1687 interconnect-names = "qup-core",
1688 "qup-config",
1689 "qup-memory";
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1692 status = "disabled";
1693 };
1694
1695 uart6: serial@998000 {
1696 compatible = "qcom,geni-uart";
1697 reg = <0 0x00998000 0 0x4000>;
1698 clock-names = "se";
1699 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1700 pinctrl-names = "default";
1701 pinctrl-0 = <&qup_uart6_default>;
1702 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1703 power-domains = <&rpmhpd RPMHPD_CX>;
1704 operating-points-v2 = <&qup_opp_table>;
1705 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1706 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1707 interconnect-names = "qup-core",
1708 "qup-config";
1709 status = "disabled";
1710 };
1711
1712 i2c7: i2c@99c000 {
1713 compatible = "qcom,geni-i2c";
1714 reg = <0 0x0099c000 0 0x4000>;
1715 clock-names = "se";
1716 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1717 pinctrl-names = "default";
1718 pinctrl-0 = <&qup_i2c7_default>;
1719 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1720 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1721 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1722 dma-names = "tx", "rx";
1723 power-domains = <&rpmhpd SM8250_CX>;
1724 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1725 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1726 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1727 interconnect-names = "qup-core",
1728 "qup-config",
1729 "qup-memory";
1730 #address-cells = <1>;
1731 #size-cells = <0>;
1732 status = "disabled";
1733 };
1734
1735 spi7: spi@99c000 {
1736 compatible = "qcom,geni-spi";
1737 reg = <0 0x0099c000 0 0x4000>;
1738 clock-names = "se";
1739 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1740 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1741 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1742 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1743 dma-names = "tx", "rx";
1744 power-domains = <&rpmhpd RPMHPD_CX>;
1745 operating-points-v2 = <&qup_opp_table>;
1746 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1747 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1748 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1749 interconnect-names = "qup-core",
1750 "qup-config",
1751 "qup-memory";
1752 #address-cells = <1>;
1753 #size-cells = <0>;
1754 status = "disabled";
1755 };
1756 };
1757
1758 gpi_dma1: dma-controller@a00000 {
1759 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1760 reg = <0 0x00a00000 0 0x70000>;
1761 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1769 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1770 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1771 dma-channels = <10>;
1772 dma-channel-mask = <0x3f>;
1773 iommus = <&apps_smmu 0x56 0x0>;
1774 #dma-cells = <3>;
1775 status = "disabled";
1776 };
1777
1778 qupv3_id_1: geniqup@ac0000 {
1779 compatible = "qcom,geni-se-qup";
1780 reg = <0x0 0x00ac0000 0x0 0x6000>;
1781 clock-names = "m-ahb", "s-ahb";
1782 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1783 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1784 #address-cells = <2>;
1785 #size-cells = <2>;
1786 iommus = <&apps_smmu 0x43 0x0>;
1787 ranges;
1788 status = "disabled";
1789
1790 i2c8: i2c@a80000 {
1791 compatible = "qcom,geni-i2c";
1792 reg = <0 0x00a80000 0 0x4000>;
1793 clock-names = "se";
1794 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1795 pinctrl-names = "default";
1796 pinctrl-0 = <&qup_i2c8_default>;
1797 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1798 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1799 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1800 dma-names = "tx", "rx";
1801 power-domains = <&rpmhpd SM8250_CX>;
1802 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1803 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1804 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1805 interconnect-names = "qup-core",
1806 "qup-config",
1807 "qup-memory";
1808 #address-cells = <1>;
1809 #size-cells = <0>;
1810 status = "disabled";
1811 };
1812
1813 spi8: spi@a80000 {
1814 compatible = "qcom,geni-spi";
1815 reg = <0 0x00a80000 0 0x4000>;
1816 clock-names = "se";
1817 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1818 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1819 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1820 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1821 dma-names = "tx", "rx";
1822 power-domains = <&rpmhpd RPMHPD_CX>;
1823 operating-points-v2 = <&qup_opp_table>;
1824 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1825 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1826 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1827 interconnect-names = "qup-core",
1828 "qup-config",
1829 "qup-memory";
1830 #address-cells = <1>;
1831 #size-cells = <0>;
1832 status = "disabled";
1833 };
1834
1835 i2c9: i2c@a84000 {
1836 compatible = "qcom,geni-i2c";
1837 reg = <0 0x00a84000 0 0x4000>;
1838 clock-names = "se";
1839 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1840 pinctrl-names = "default";
1841 pinctrl-0 = <&qup_i2c9_default>;
1842 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1843 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1844 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1845 dma-names = "tx", "rx";
1846 power-domains = <&rpmhpd SM8250_CX>;
1847 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1848 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1849 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1850 interconnect-names = "qup-core",
1851 "qup-config",
1852 "qup-memory";
1853 #address-cells = <1>;
1854 #size-cells = <0>;
1855 status = "disabled";
1856 };
1857
1858 spi9: spi@a84000 {
1859 compatible = "qcom,geni-spi";
1860 reg = <0 0x00a84000 0 0x4000>;
1861 clock-names = "se";
1862 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1863 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1864 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1865 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1866 dma-names = "tx", "rx";
1867 power-domains = <&rpmhpd RPMHPD_CX>;
1868 operating-points-v2 = <&qup_opp_table>;
1869 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1870 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1871 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1872 interconnect-names = "qup-core",
1873 "qup-config",
1874 "qup-memory";
1875 #address-cells = <1>;
1876 #size-cells = <0>;
1877 status = "disabled";
1878 };
1879
1880 i2c10: i2c@a88000 {
1881 compatible = "qcom,geni-i2c";
1882 reg = <0 0x00a88000 0 0x4000>;
1883 clock-names = "se";
1884 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1885 pinctrl-names = "default";
1886 pinctrl-0 = <&qup_i2c10_default>;
1887 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1888 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1889 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1890 dma-names = "tx", "rx";
1891 power-domains = <&rpmhpd SM8250_CX>;
1892 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1893 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1894 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1895 interconnect-names = "qup-core",
1896 "qup-config",
1897 "qup-memory";
1898 #address-cells = <1>;
1899 #size-cells = <0>;
1900 status = "disabled";
1901 };
1902
1903 spi10: spi@a88000 {
1904 compatible = "qcom,geni-spi";
1905 reg = <0 0x00a88000 0 0x4000>;
1906 clock-names = "se";
1907 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1908 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1909 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1910 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1911 dma-names = "tx", "rx";
1912 power-domains = <&rpmhpd RPMHPD_CX>;
1913 operating-points-v2 = <&qup_opp_table>;
1914 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1915 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1916 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1917 interconnect-names = "qup-core",
1918 "qup-config",
1919 "qup-memory";
1920 #address-cells = <1>;
1921 #size-cells = <0>;
1922 status = "disabled";
1923 };
1924
1925 i2c11: i2c@a8c000 {
1926 compatible = "qcom,geni-i2c";
1927 reg = <0 0x00a8c000 0 0x4000>;
1928 clock-names = "se";
1929 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1930 pinctrl-names = "default";
1931 pinctrl-0 = <&qup_i2c11_default>;
1932 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1933 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1934 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1935 dma-names = "tx", "rx";
1936 power-domains = <&rpmhpd SM8250_CX>;
1937 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1938 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1939 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1940 interconnect-names = "qup-core",
1941 "qup-config",
1942 "qup-memory";
1943 #address-cells = <1>;
1944 #size-cells = <0>;
1945 status = "disabled";
1946 };
1947
1948 spi11: spi@a8c000 {
1949 compatible = "qcom,geni-spi";
1950 reg = <0 0x00a8c000 0 0x4000>;
1951 clock-names = "se";
1952 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1953 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1954 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1955 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1956 dma-names = "tx", "rx";
1957 power-domains = <&rpmhpd RPMHPD_CX>;
1958 operating-points-v2 = <&qup_opp_table>;
1959 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1960 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1961 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1962 interconnect-names = "qup-core",
1963 "qup-config",
1964 "qup-memory";
1965 #address-cells = <1>;
1966 #size-cells = <0>;
1967 status = "disabled";
1968 };
1969
1970 i2c12: i2c@a90000 {
1971 compatible = "qcom,geni-i2c";
1972 reg = <0 0x00a90000 0 0x4000>;
1973 clock-names = "se";
1974 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1975 pinctrl-names = "default";
1976 pinctrl-0 = <&qup_i2c12_default>;
1977 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1978 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1979 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1980 dma-names = "tx", "rx";
1981 power-domains = <&rpmhpd SM8250_CX>;
1982 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1983 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1984 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1985 interconnect-names = "qup-core",
1986 "qup-config",
1987 "qup-memory";
1988 #address-cells = <1>;
1989 #size-cells = <0>;
1990 status = "disabled";
1991 };
1992
1993 spi12: spi@a90000 {
1994 compatible = "qcom,geni-spi";
1995 reg = <0 0x00a90000 0 0x4000>;
1996 clock-names = "se";
1997 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1998 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2000 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2001 dma-names = "tx", "rx";
2002 power-domains = <&rpmhpd RPMHPD_CX>;
2003 operating-points-v2 = <&qup_opp_table>;
2004 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2005 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2006 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2007 interconnect-names = "qup-core",
2008 "qup-config",
2009 "qup-memory";
2010 #address-cells = <1>;
2011 #size-cells = <0>;
2012 status = "disabled";
2013 };
2014
2015 uart12: serial@a90000 {
2016 compatible = "qcom,geni-debug-uart";
2017 reg = <0x0 0x00a90000 0x0 0x4000>;
2018 clock-names = "se";
2019 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2020 pinctrl-names = "default";
2021 pinctrl-0 = <&qup_uart12_default>;
2022 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2023 power-domains = <&rpmhpd RPMHPD_CX>;
2024 operating-points-v2 = <&qup_opp_table>;
2025 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2026 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
2027 interconnect-names = "qup-core",
2028 "qup-config";
2029 status = "disabled";
2030 };
2031
2032 i2c13: i2c@a94000 {
2033 compatible = "qcom,geni-i2c";
2034 reg = <0 0x00a94000 0 0x4000>;
2035 clock-names = "se";
2036 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2037 pinctrl-names = "default";
2038 pinctrl-0 = <&qup_i2c13_default>;
2039 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2040 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2041 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2042 dma-names = "tx", "rx";
2043 power-domains = <&rpmhpd SM8250_CX>;
2044 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2045 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2046 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2047 interconnect-names = "qup-core",
2048 "qup-config",
2049 "qup-memory";
2050 #address-cells = <1>;
2051 #size-cells = <0>;
2052 status = "disabled";
2053 };
2054
2055 spi13: spi@a94000 {
2056 compatible = "qcom,geni-spi";
2057 reg = <0 0x00a94000 0 0x4000>;
2058 clock-names = "se";
2059 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2060 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2061 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2062 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2063 dma-names = "tx", "rx";
2064 power-domains = <&rpmhpd RPMHPD_CX>;
2065 operating-points-v2 = <&qup_opp_table>;
2066 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2067 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2068 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2069 interconnect-names = "qup-core",
2070 "qup-config",
2071 "qup-memory";
2072 #address-cells = <1>;
2073 #size-cells = <0>;
2074 status = "disabled";
2075 };
2076 };
2077
2078 config_noc: interconnect@1500000 {
2079 compatible = "qcom,sm8250-config-noc";
2080 reg = <0 0x01500000 0 0xa580>;
2081 #interconnect-cells = <2>;
2082 qcom,bcm-voters = <&apps_bcm_voter>;
2083 };
2084
2085 system_noc: interconnect@1620000 {
2086 compatible = "qcom,sm8250-system-noc";
2087 reg = <0 0x01620000 0 0x1c200>;
2088 #interconnect-cells = <2>;
2089 qcom,bcm-voters = <&apps_bcm_voter>;
2090 };
2091
2092 mc_virt: interconnect@163d000 {
2093 compatible = "qcom,sm8250-mc-virt";
2094 reg = <0 0x0163d000 0 0x1000>;
2095 #interconnect-cells = <2>;
2096 qcom,bcm-voters = <&apps_bcm_voter>;
2097 };
2098
2099 aggre1_noc: interconnect@16e0000 {
2100 compatible = "qcom,sm8250-aggre1-noc";
2101 reg = <0 0x016e0000 0 0x1f180>;
2102 #interconnect-cells = <2>;
2103 qcom,bcm-voters = <&apps_bcm_voter>;
2104 };
2105
2106 aggre2_noc: interconnect@1700000 {
2107 compatible = "qcom,sm8250-aggre2-noc";
2108 reg = <0 0x01700000 0 0x33000>;
2109 #interconnect-cells = <2>;
2110 qcom,bcm-voters = <&apps_bcm_voter>;
2111 };
2112
2113 compute_noc: interconnect@1733000 {
2114 compatible = "qcom,sm8250-compute-noc";
2115 reg = <0 0x01733000 0 0xa180>;
2116 #interconnect-cells = <2>;
2117 qcom,bcm-voters = <&apps_bcm_voter>;
2118 };
2119
2120 mmss_noc: interconnect@1740000 {
2121 compatible = "qcom,sm8250-mmss-noc";
2122 reg = <0 0x01740000 0 0x1f080>;
2123 #interconnect-cells = <2>;
2124 qcom,bcm-voters = <&apps_bcm_voter>;
2125 };
2126
2127 pcie0: pcie@1c00000 {
2128 compatible = "qcom,pcie-sm8250";
2129 reg = <0 0x01c00000 0 0x3000>,
2130 <0 0x60000000 0 0xf1d>,
2131 <0 0x60000f20 0 0xa8>,
2132 <0 0x60001000 0 0x1000>,
2133 <0 0x60100000 0 0x100000>,
2134 <0 0x01c03000 0 0x1000>;
2135 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2136 device_type = "pci";
2137 linux,pci-domain = <0>;
2138 bus-range = <0x00 0xff>;
2139 num-lanes = <1>;
2140
2141 #address-cells = <3>;
2142 #size-cells = <2>;
2143
2144 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2145 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2146
2147 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2148 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2150 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2151 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2152 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2153 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2154 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2155 interrupt-names = "msi0",
2156 "msi1",
2157 "msi2",
2158 "msi3",
2159 "msi4",
2160 "msi5",
2161 "msi6",
2162 "msi7";
2163 #interrupt-cells = <1>;
2164 interrupt-map-mask = <0 0 0 0x7>;
2165 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2166 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2167 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2168 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2169
2170 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2171 <&gcc GCC_PCIE_0_AUX_CLK>,
2172 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2173 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2174 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2175 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2176 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2177 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2178 clock-names = "pipe",
2179 "aux",
2180 "cfg",
2181 "bus_master",
2182 "bus_slave",
2183 "slave_q2a",
2184 "tbu",
2185 "ddrss_sf_tbu";
2186
2187 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2188 <0x100 &apps_smmu 0x1c01 0x1>;
2189
2190 resets = <&gcc GCC_PCIE_0_BCR>;
2191 reset-names = "pci";
2192
2193 power-domains = <&gcc PCIE_0_GDSC>;
2194
2195 phys = <&pcie0_phy>;
2196 phy-names = "pciephy";
2197
2198 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2199 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2200
2201 pinctrl-names = "default";
2202 pinctrl-0 = <&pcie0_default_state>;
2203 dma-coherent;
2204
2205 status = "disabled";
2206
2207 pcieport0: pcie@0 {
2208 device_type = "pci";
2209 reg = <0x0 0x0 0x0 0x0 0x0>;
2210 bus-range = <0x01 0xff>;
2211
2212 #address-cells = <3>;
2213 #size-cells = <2>;
2214 ranges;
2215 };
2216 };
2217
2218 pcie0_phy: phy@1c06000 {
2219 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2220 reg = <0 0x01c06000 0 0x1000>;
2221
2222 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2223 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2224 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2225 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
2226 <&gcc GCC_PCIE_0_PIPE_CLK>;
2227 clock-names = "aux",
2228 "cfg_ahb",
2229 "ref",
2230 "refgen",
2231 "pipe";
2232
2233 clock-output-names = "pcie_0_pipe_clk";
2234 #clock-cells = <0>;
2235
2236 #phy-cells = <0>;
2237
2238 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2239 reset-names = "phy";
2240
2241 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2242 assigned-clock-rates = <100000000>;
2243
2244 status = "disabled";
2245 };
2246
2247 pcie1: pcie@1c08000 {
2248 compatible = "qcom,pcie-sm8250";
2249 reg = <0 0x01c08000 0 0x3000>,
2250 <0 0x40000000 0 0xf1d>,
2251 <0 0x40000f20 0 0xa8>,
2252 <0 0x40001000 0 0x1000>,
2253 <0 0x40100000 0 0x100000>,
2254 <0 0x01c0b000 0 0x1000>;
2255 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2256 device_type = "pci";
2257 linux,pci-domain = <1>;
2258 bus-range = <0x00 0xff>;
2259 num-lanes = <2>;
2260
2261 #address-cells = <3>;
2262 #size-cells = <2>;
2263
2264 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2265 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2266
2267 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2268 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2269 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
2270 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
2271 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
2272 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
2273 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
2274 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2275 interrupt-names = "msi0",
2276 "msi1",
2277 "msi2",
2278 "msi3",
2279 "msi4",
2280 "msi5",
2281 "msi6",
2282 "msi7";
2283 #interrupt-cells = <1>;
2284 interrupt-map-mask = <0 0 0 0x7>;
2285 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2286 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2287 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2288 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2289
2290 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2291 <&gcc GCC_PCIE_1_AUX_CLK>,
2292 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2293 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2294 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2295 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2296 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2297 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2298 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2299 clock-names = "pipe",
2300 "aux",
2301 "cfg",
2302 "bus_master",
2303 "bus_slave",
2304 "slave_q2a",
2305 "ref",
2306 "tbu",
2307 "ddrss_sf_tbu";
2308
2309 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2310 assigned-clock-rates = <19200000>;
2311
2312 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2313 <0x100 &apps_smmu 0x1c81 0x1>;
2314
2315 resets = <&gcc GCC_PCIE_1_BCR>;
2316 reset-names = "pci";
2317
2318 power-domains = <&gcc PCIE_1_GDSC>;
2319
2320 phys = <&pcie1_phy>;
2321 phy-names = "pciephy";
2322
2323 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2324 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2325
2326 pinctrl-names = "default";
2327 pinctrl-0 = <&pcie1_default_state>;
2328 dma-coherent;
2329
2330 status = "disabled";
2331
2332 pcie@0 {
2333 device_type = "pci";
2334 reg = <0x0 0x0 0x0 0x0 0x0>;
2335 bus-range = <0x01 0xff>;
2336
2337 #address-cells = <3>;
2338 #size-cells = <2>;
2339 ranges;
2340 };
2341 };
2342
2343 pcie1_phy: phy@1c0e000 {
2344 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2345 reg = <0 0x01c0e000 0 0x1000>;
2346
2347 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2348 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2349 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2350 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2351 <&gcc GCC_PCIE_1_PIPE_CLK>;
2352 clock-names = "aux",
2353 "cfg_ahb",
2354 "ref",
2355 "refgen",
2356 "pipe";
2357
2358 clock-output-names = "pcie_1_pipe_clk";
2359 #clock-cells = <0>;
2360
2361 #phy-cells = <0>;
2362
2363 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2364 reset-names = "phy";
2365
2366 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2367 assigned-clock-rates = <100000000>;
2368
2369 status = "disabled";
2370 };
2371
2372 pcie2: pcie@1c10000 {
2373 compatible = "qcom,pcie-sm8250";
2374 reg = <0 0x01c10000 0 0x3000>,
2375 <0 0x64000000 0 0xf1d>,
2376 <0 0x64000f20 0 0xa8>,
2377 <0 0x64001000 0 0x1000>,
2378 <0 0x64100000 0 0x100000>,
2379 <0 0x01c13000 0 0x1000>;
2380 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2381 device_type = "pci";
2382 linux,pci-domain = <2>;
2383 bus-range = <0x00 0xff>;
2384 num-lanes = <2>;
2385
2386 #address-cells = <3>;
2387 #size-cells = <2>;
2388
2389 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2390 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2391
2392 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
2393 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2394 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2395 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2396 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
2397 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
2398 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
2399 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
2400 interrupt-names = "msi0",
2401 "msi1",
2402 "msi2",
2403 "msi3",
2404 "msi4",
2405 "msi5",
2406 "msi6",
2407 "msi7";
2408 #interrupt-cells = <1>;
2409 interrupt-map-mask = <0 0 0 0x7>;
2410 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2411 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2412 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2413 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2414
2415 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2416 <&gcc GCC_PCIE_2_AUX_CLK>,
2417 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2418 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2419 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2420 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2421 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2422 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2423 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2424 clock-names = "pipe",
2425 "aux",
2426 "cfg",
2427 "bus_master",
2428 "bus_slave",
2429 "slave_q2a",
2430 "ref",
2431 "tbu",
2432 "ddrss_sf_tbu";
2433
2434 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2435 assigned-clock-rates = <19200000>;
2436
2437 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2438 <0x100 &apps_smmu 0x1d01 0x1>;
2439
2440 resets = <&gcc GCC_PCIE_2_BCR>;
2441 reset-names = "pci";
2442
2443 power-domains = <&gcc PCIE_2_GDSC>;
2444
2445 phys = <&pcie2_phy>;
2446 phy-names = "pciephy";
2447
2448 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2449 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2450
2451 pinctrl-names = "default";
2452 pinctrl-0 = <&pcie2_default_state>;
2453 dma-coherent;
2454
2455 status = "disabled";
2456
2457 pcie@0 {
2458 device_type = "pci";
2459 reg = <0x0 0x0 0x0 0x0 0x0>;
2460 bus-range = <0x01 0xff>;
2461
2462 #address-cells = <3>;
2463 #size-cells = <2>;
2464 ranges;
2465 };
2466 };
2467
2468 pcie2_phy: phy@1c16000 {
2469 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2470 reg = <0 0x01c16000 0 0x1000>;
2471
2472 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2473 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2474 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2475 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
2476 <&gcc GCC_PCIE_2_PIPE_CLK>;
2477 clock-names = "aux",
2478 "cfg_ahb",
2479 "ref",
2480 "refgen",
2481 "pipe";
2482
2483 clock-output-names = "pcie_2_pipe_clk";
2484 #clock-cells = <0>;
2485
2486 #phy-cells = <0>;
2487
2488 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2489 reset-names = "phy";
2490
2491 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2492 assigned-clock-rates = <100000000>;
2493
2494 status = "disabled";
2495 };
2496
2497 ufs_mem_hc: ufshc@1d84000 {
2498 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2499 "jedec,ufs-2.0";
2500 reg = <0 0x01d84000 0 0x3000>;
2501 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2502 phys = <&ufs_mem_phy>;
2503 phy-names = "ufsphy";
2504 lanes-per-direction = <2>;
2505 #reset-cells = <1>;
2506 resets = <&gcc GCC_UFS_PHY_BCR>;
2507 reset-names = "rst";
2508
2509 power-domains = <&gcc UFS_PHY_GDSC>;
2510
2511 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2512
2513 clock-names =
2514 "core_clk",
2515 "bus_aggr_clk",
2516 "iface_clk",
2517 "core_clk_unipro",
2518 "ref_clk",
2519 "tx_lane0_sync_clk",
2520 "rx_lane0_sync_clk",
2521 "rx_lane1_sync_clk";
2522 clocks =
2523 <&gcc GCC_UFS_PHY_AXI_CLK>,
2524 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2525 <&gcc GCC_UFS_PHY_AHB_CLK>,
2526 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2527 <&rpmhcc RPMH_CXO_CLK>,
2528 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2529 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2530 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2531
2532 operating-points-v2 = <&ufs_opp_table>;
2533
2534 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2535 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2536 interconnect-names = "ufs-ddr", "cpu-ufs";
2537
2538 status = "disabled";
2539
2540 ufs_opp_table: opp-table {
2541 compatible = "operating-points-v2";
2542
2543 opp-37500000 {
2544 opp-hz = /bits/ 64 <37500000>,
2545 /bits/ 64 <0>,
2546 /bits/ 64 <0>,
2547 /bits/ 64 <37500000>,
2548 /bits/ 64 <0>,
2549 /bits/ 64 <0>,
2550 /bits/ 64 <0>,
2551 /bits/ 64 <0>;
2552 required-opps = <&rpmhpd_opp_low_svs>;
2553 };
2554
2555 opp-300000000 {
2556 opp-hz = /bits/ 64 <300000000>,
2557 /bits/ 64 <0>,
2558 /bits/ 64 <0>,
2559 /bits/ 64 <300000000>,
2560 /bits/ 64 <0>,
2561 /bits/ 64 <0>,
2562 /bits/ 64 <0>,
2563 /bits/ 64 <0>;
2564 required-opps = <&rpmhpd_opp_nom>;
2565 };
2566 };
2567 };
2568
2569 ufs_mem_phy: phy@1d87000 {
2570 compatible = "qcom,sm8250-qmp-ufs-phy";
2571 reg = <0 0x01d87000 0 0x1000>;
2572
2573 clocks = <&rpmhcc RPMH_CXO_CLK>,
2574 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2575 <&gcc GCC_UFS_1X_CLKREF_EN>;
2576 clock-names = "ref",
2577 "ref_aux",
2578 "qref";
2579
2580 resets = <&ufs_mem_hc 0>;
2581 reset-names = "ufsphy";
2582
2583 power-domains = <&gcc UFS_PHY_GDSC>;
2584
2585 #phy-cells = <0>;
2586
2587 status = "disabled";
2588 };
2589
2590 cryptobam: dma-controller@1dc4000 {
2591 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2592 reg = <0 0x01dc4000 0 0x24000>;
2593 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2594 #dma-cells = <1>;
2595 qcom,ee = <0>;
2596 qcom,controlled-remotely;
2597 num-channels = <8>;
2598 qcom,num-ees = <2>;
2599 iommus = <&apps_smmu 0x592 0x0000>,
2600 <&apps_smmu 0x598 0x0000>,
2601 <&apps_smmu 0x599 0x0000>,
2602 <&apps_smmu 0x59f 0x0000>,
2603 <&apps_smmu 0x586 0x0011>,
2604 <&apps_smmu 0x596 0x0011>;
2605 };
2606
2607 crypto: crypto@1dfa000 {
2608 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2609 reg = <0 0x01dfa000 0 0x6000>;
2610 dmas = <&cryptobam 4>, <&cryptobam 5>;
2611 dma-names = "rx", "tx";
2612 iommus = <&apps_smmu 0x592 0x0000>,
2613 <&apps_smmu 0x598 0x0000>,
2614 <&apps_smmu 0x599 0x0000>,
2615 <&apps_smmu 0x59f 0x0000>,
2616 <&apps_smmu 0x586 0x0011>,
2617 <&apps_smmu 0x596 0x0011>;
2618 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2619 interconnect-names = "memory";
2620 };
2621
2622 tcsr_mutex: hwlock@1f40000 {
2623 compatible = "qcom,tcsr-mutex";
2624 reg = <0x0 0x01f40000 0x0 0x40000>;
2625 #hwlock-cells = <1>;
2626 };
2627
2628 tcsr: syscon@1fc0000 {
2629 compatible = "qcom,sm8250-tcsr", "syscon";
2630 reg = <0x0 0x1fc0000 0x0 0x30000>;
2631 };
2632
2633 wsamacro: codec@3240000 {
2634 compatible = "qcom,sm8250-lpass-wsa-macro";
2635 reg = <0 0x03240000 0 0x1000>;
2636 clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2637 <&audiocc LPASS_CDC_WSA_NPL>,
2638 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2639 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2640 <&aoncc LPASS_CDC_VA_MCLK>,
2641 <&vamacro>;
2642
2643 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2644
2645 #clock-cells = <0>;
2646 clock-output-names = "mclk";
2647 #sound-dai-cells = <1>;
2648
2649 pinctrl-names = "default";
2650 pinctrl-0 = <&wsa_swr_active>;
2651
2652 status = "disabled";
2653 };
2654
2655 swr0: soundwire@3250000 {
2656 reg = <0 0x03250000 0 0x2000>;
2657 compatible = "qcom,soundwire-v1.5.1";
2658 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2659 clocks = <&wsamacro>;
2660 clock-names = "iface";
2661
2662 qcom,din-ports = <2>;
2663 qcom,dout-ports = <6>;
2664
2665 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2666 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2667 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2668 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2669
2670 #sound-dai-cells = <1>;
2671 #address-cells = <2>;
2672 #size-cells = <0>;
2673
2674 status = "disabled";
2675 };
2676
2677 audiocc: clock-controller@3300000 {
2678 compatible = "qcom,sm8250-lpass-audiocc";
2679 reg = <0 0x03300000 0 0x30000>;
2680 #clock-cells = <1>;
2681 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2682 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2683 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2684 clock-names = "core", "audio", "bus";
2685 };
2686
2687 vamacro: codec@3370000 {
2688 compatible = "qcom,sm8250-lpass-va-macro";
2689 reg = <0 0x03370000 0 0x1000>;
2690 clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2691 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2692 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2693
2694 clock-names = "mclk", "macro", "dcodec";
2695
2696 #clock-cells = <0>;
2697 clock-output-names = "fsgen";
2698 #sound-dai-cells = <1>;
2699 };
2700
2701 rxmacro: rxmacro@3200000 {
2702 pinctrl-names = "default";
2703 pinctrl-0 = <&rx_swr_active>;
2704 compatible = "qcom,sm8250-lpass-rx-macro";
2705 reg = <0 0x03200000 0 0x1000>;
2706 status = "disabled";
2707
2708 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2709 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2710 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2711 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2712 <&vamacro>;
2713
2714 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2715
2716 #clock-cells = <0>;
2717 clock-output-names = "mclk";
2718 #sound-dai-cells = <1>;
2719 };
2720
2721 swr1: soundwire@3210000 {
2722 reg = <0 0x03210000 0 0x2000>;
2723 compatible = "qcom,soundwire-v1.5.1";
2724 status = "disabled";
2725 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2726 clocks = <&rxmacro>;
2727 clock-names = "iface";
2728 label = "RX";
2729 qcom,din-ports = <0>;
2730 qcom,dout-ports = <5>;
2731
2732 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2733 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2734 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2735 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2736 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2737 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2738 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2739 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2740 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2741
2742 #sound-dai-cells = <1>;
2743 #address-cells = <2>;
2744 #size-cells = <0>;
2745 };
2746
2747 txmacro: txmacro@3220000 {
2748 pinctrl-names = "default";
2749 pinctrl-0 = <&tx_swr_active>;
2750 compatible = "qcom,sm8250-lpass-tx-macro";
2751 reg = <0 0x03220000 0 0x1000>;
2752 status = "disabled";
2753
2754 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2755 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2756 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2757 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2758 <&vamacro>;
2759
2760 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2761
2762 #clock-cells = <0>;
2763 clock-output-names = "mclk";
2764 #sound-dai-cells = <1>;
2765 };
2766
2767 /* tx macro */
2768 swr2: soundwire@3230000 {
2769 reg = <0 0x03230000 0 0x2000>;
2770 compatible = "qcom,soundwire-v1.5.1";
2771 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2772 interrupt-names = "core";
2773 status = "disabled";
2774
2775 clocks = <&txmacro>;
2776 clock-names = "iface";
2777 label = "TX";
2778
2779 qcom,din-ports = <5>;
2780 qcom,dout-ports = <0>;
2781 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2782 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2783 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2784 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2785 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2786 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2787 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2788 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2789 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2790 #sound-dai-cells = <1>;
2791 #address-cells = <2>;
2792 #size-cells = <0>;
2793 };
2794
2795 aoncc: clock-controller@3380000 {
2796 compatible = "qcom,sm8250-lpass-aoncc";
2797 reg = <0 0x03380000 0 0x40000>;
2798 #clock-cells = <1>;
2799 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2800 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2801 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2802 clock-names = "core", "audio", "bus";
2803 };
2804
2805 lpass_tlmm: pinctrl@33c0000 {
2806 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2807 reg = <0 0x033c0000 0x0 0x20000>,
2808 <0 0x03550000 0x0 0x10000>;
2809 gpio-controller;
2810 #gpio-cells = <2>;
2811 gpio-ranges = <&lpass_tlmm 0 0 14>;
2812
2813 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2814 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2815 clock-names = "core", "audio";
2816
2817 wsa_swr_active: wsa-swr-active-state {
2818 clk-pins {
2819 pins = "gpio10";
2820 function = "wsa_swr_clk";
2821 drive-strength = <2>;
2822 slew-rate = <1>;
2823 bias-disable;
2824 };
2825
2826 data-pins {
2827 pins = "gpio11";
2828 function = "wsa_swr_data";
2829 drive-strength = <2>;
2830 slew-rate = <1>;
2831 bias-bus-hold;
2832 };
2833 };
2834
2835 wsa_swr_sleep: wsa-swr-sleep-state {
2836 clk-pins {
2837 pins = "gpio10";
2838 function = "wsa_swr_clk";
2839 drive-strength = <2>;
2840 bias-pull-down;
2841 };
2842
2843 data-pins {
2844 pins = "gpio11";
2845 function = "wsa_swr_data";
2846 drive-strength = <2>;
2847 bias-pull-down;
2848 };
2849 };
2850
2851 dmic01_active: dmic01-active-state {
2852 clk-pins {
2853 pins = "gpio6";
2854 function = "dmic1_clk";
2855 drive-strength = <8>;
2856 output-high;
2857 };
2858 data-pins {
2859 pins = "gpio7";
2860 function = "dmic1_data";
2861 drive-strength = <8>;
2862 };
2863 };
2864
2865 dmic01_sleep: dmic01-sleep-state {
2866 clk-pins {
2867 pins = "gpio6";
2868 function = "dmic1_clk";
2869 drive-strength = <2>;
2870 bias-disable;
2871 output-low;
2872 };
2873
2874 data-pins {
2875 pins = "gpio7";
2876 function = "dmic1_data";
2877 drive-strength = <2>;
2878 bias-pull-down;
2879 };
2880 };
2881
2882 rx_swr_active: rx-swr-active-state {
2883 clk-pins {
2884 pins = "gpio3";
2885 function = "swr_rx_clk";
2886 drive-strength = <2>;
2887 slew-rate = <1>;
2888 bias-disable;
2889 };
2890
2891 data-pins {
2892 pins = "gpio4", "gpio5";
2893 function = "swr_rx_data";
2894 drive-strength = <2>;
2895 slew-rate = <1>;
2896 bias-bus-hold;
2897 };
2898 };
2899
2900 tx_swr_active: tx-swr-active-state {
2901 clk-pins {
2902 pins = "gpio0";
2903 function = "swr_tx_clk";
2904 drive-strength = <2>;
2905 slew-rate = <1>;
2906 bias-disable;
2907 };
2908
2909 data-pins {
2910 pins = "gpio1", "gpio2";
2911 function = "swr_tx_data";
2912 drive-strength = <2>;
2913 slew-rate = <1>;
2914 bias-bus-hold;
2915 };
2916 };
2917
2918 tx_swr_sleep: tx-swr-sleep-state {
2919 clk-pins {
2920 pins = "gpio0";
2921 function = "swr_tx_clk";
2922 drive-strength = <2>;
2923 bias-pull-down;
2924 };
2925
2926 data1-pins {
2927 pins = "gpio1";
2928 function = "swr_tx_data";
2929 drive-strength = <2>;
2930 bias-bus-hold;
2931 };
2932
2933 data2-pins {
2934 pins = "gpio2";
2935 function = "swr_tx_data";
2936 drive-strength = <2>;
2937 bias-pull-down;
2938 };
2939 };
2940 };
2941
2942 gpu: gpu@3d00000 {
2943 compatible = "qcom,adreno-650.2",
2944 "qcom,adreno";
2945
2946 reg = <0 0x03d00000 0 0x40000>;
2947 reg-names = "kgsl_3d0_reg_memory";
2948
2949 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2950
2951 iommus = <&adreno_smmu 0 0x401>;
2952
2953 operating-points-v2 = <&gpu_opp_table>;
2954
2955 qcom,gmu = <&gmu>;
2956
2957 nvmem-cells = <&gpu_speed_bin>;
2958 nvmem-cell-names = "speed_bin";
2959 #cooling-cells = <2>;
2960
2961 status = "disabled";
2962
2963 zap-shader {
2964 memory-region = <&gpu_mem>;
2965 };
2966
2967 gpu_opp_table: opp-table {
2968 compatible = "operating-points-v2";
2969
2970 opp-670000000 {
2971 opp-hz = /bits/ 64 <670000000>;
2972 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2973 opp-supported-hw = <0xa>;
2974 };
2975
2976 opp-587000000 {
2977 opp-hz = /bits/ 64 <587000000>;
2978 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2979 opp-supported-hw = <0xb>;
2980 };
2981
2982 opp-525000000 {
2983 opp-hz = /bits/ 64 <525000000>;
2984 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2985 opp-supported-hw = <0xf>;
2986 };
2987
2988 opp-490000000 {
2989 opp-hz = /bits/ 64 <490000000>;
2990 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2991 opp-supported-hw = <0xf>;
2992 };
2993
2994 opp-441600000 {
2995 opp-hz = /bits/ 64 <441600000>;
2996 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2997 opp-supported-hw = <0xf>;
2998 };
2999
3000 opp-400000000 {
3001 opp-hz = /bits/ 64 <400000000>;
3002 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3003 opp-supported-hw = <0xf>;
3004 };
3005
3006 opp-305000000 {
3007 opp-hz = /bits/ 64 <305000000>;
3008 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3009 opp-supported-hw = <0xf>;
3010 };
3011 };
3012 };
3013
3014 gmu: gmu@3d6a000 {
3015 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
3016
3017 reg = <0 0x03d6a000 0 0x30000>,
3018 <0 0x3de0000 0 0x10000>,
3019 <0 0xb290000 0 0x10000>,
3020 <0 0xb490000 0 0x10000>;
3021 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
3022
3023 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3024 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3025 interrupt-names = "hfi", "gmu";
3026
3027 clocks = <&gpucc GPU_CC_AHB_CLK>,
3028 <&gpucc GPU_CC_CX_GMU_CLK>,
3029 <&gpucc GPU_CC_CXO_CLK>,
3030 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3031 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3032 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3033
3034 power-domains = <&gpucc GPU_CX_GDSC>,
3035 <&gpucc GPU_GX_GDSC>;
3036 power-domain-names = "cx", "gx";
3037
3038 iommus = <&adreno_smmu 5 0x400>;
3039
3040 operating-points-v2 = <&gmu_opp_table>;
3041
3042 status = "disabled";
3043
3044 gmu_opp_table: opp-table {
3045 compatible = "operating-points-v2";
3046
3047 opp-200000000 {
3048 opp-hz = /bits/ 64 <200000000>;
3049 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3050 };
3051 };
3052 };
3053
3054 gpucc: clock-controller@3d90000 {
3055 compatible = "qcom,sm8250-gpucc";
3056 reg = <0 0x03d90000 0 0x9000>;
3057 clocks = <&rpmhcc RPMH_CXO_CLK>,
3058 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3059 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3060 clock-names = "bi_tcxo",
3061 "gcc_gpu_gpll0_clk_src",
3062 "gcc_gpu_gpll0_div_clk_src";
3063 #clock-cells = <1>;
3064 #reset-cells = <1>;
3065 #power-domain-cells = <1>;
3066 };
3067
3068 adreno_smmu: iommu@3da0000 {
3069 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
3070 "qcom,smmu-500", "arm,mmu-500";
3071 reg = <0 0x03da0000 0 0x10000>;
3072 #iommu-cells = <2>;
3073 #global-interrupts = <2>;
3074 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3075 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3076 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3077 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3078 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3079 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3080 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3081 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3082 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3083 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3084 clocks = <&gpucc GPU_CC_AHB_CLK>,
3085 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3086 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3087 clock-names = "ahb", "bus", "iface";
3088
3089 power-domains = <&gpucc GPU_CX_GDSC>;
3090 dma-coherent;
3091 };
3092
3093 slpi: remoteproc@5c00000 {
3094 compatible = "qcom,sm8250-slpi-pas";
3095 reg = <0 0x05c00000 0 0x4000>;
3096
3097 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
3098 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3099 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3100 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3101 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3102 interrupt-names = "wdog", "fatal", "ready",
3103 "handover", "stop-ack";
3104
3105 clocks = <&rpmhcc RPMH_CXO_CLK>;
3106 clock-names = "xo";
3107
3108 power-domains = <&rpmhpd RPMHPD_LCX>,
3109 <&rpmhpd RPMHPD_LMX>;
3110 power-domain-names = "lcx", "lmx";
3111
3112 memory-region = <&slpi_mem>;
3113
3114 qcom,qmp = <&aoss_qmp>;
3115
3116 qcom,smem-states = <&smp2p_slpi_out 0>;
3117 qcom,smem-state-names = "stop";
3118
3119 status = "disabled";
3120
3121 glink-edge {
3122 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3123 IPCC_MPROC_SIGNAL_GLINK_QMP
3124 IRQ_TYPE_EDGE_RISING>;
3125 mboxes = <&ipcc IPCC_CLIENT_SLPI
3126 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3127
3128 label = "slpi";
3129 qcom,remote-pid = <3>;
3130
3131 fastrpc {
3132 compatible = "qcom,fastrpc";
3133 qcom,glink-channels = "fastrpcglink-apps-dsp";
3134 label = "sdsp";
3135 qcom,non-secure-domain;
3136 #address-cells = <1>;
3137 #size-cells = <0>;
3138
3139 compute-cb@1 {
3140 compatible = "qcom,fastrpc-compute-cb";
3141 reg = <1>;
3142 iommus = <&apps_smmu 0x0541 0x0>;
3143 };
3144
3145 compute-cb@2 {
3146 compatible = "qcom,fastrpc-compute-cb";
3147 reg = <2>;
3148 iommus = <&apps_smmu 0x0542 0x0>;
3149 };
3150
3151 compute-cb@3 {
3152 compatible = "qcom,fastrpc-compute-cb";
3153 reg = <3>;
3154 iommus = <&apps_smmu 0x0543 0x0>;
3155 /* note: shared-cb = <4> in downstream */
3156 };
3157 };
3158 };
3159 };
3160
3161 stm@6002000 {
3162 compatible = "arm,coresight-stm", "arm,primecell";
3163 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3164 reg-names = "stm-base", "stm-stimulus-base";
3165
3166 clocks = <&aoss_qmp>;
3167 clock-names = "apb_pclk";
3168
3169 out-ports {
3170 port {
3171 stm_out: endpoint {
3172 remote-endpoint = <&funnel0_in7>;
3173 };
3174 };
3175 };
3176 };
3177
3178 tpda@6004000 {
3179 compatible = "qcom,coresight-tpda", "arm,primecell";
3180 reg = <0 0x06004000 0 0x1000>;
3181
3182 clocks = <&aoss_qmp>;
3183 clock-names = "apb_pclk";
3184
3185 out-ports {
3186
3187 port {
3188 tpda_out_funnel_qatb: endpoint {
3189 remote-endpoint = <&funnel_qatb_in_tpda>;
3190 };
3191 };
3192 };
3193
3194 in-ports {
3195 #address-cells = <1>;
3196 #size-cells = <0>;
3197
3198 port@9 {
3199 reg = <9>;
3200 tpda_9_in_tpdm_mm: endpoint {
3201 remote-endpoint = <&tpdm_mm_out_tpda9>;
3202 };
3203 };
3204
3205 port@17 {
3206 reg = <23>;
3207 tpda_23_in_tpdm_prng: endpoint {
3208 remote-endpoint = <&tpdm_prng_out_tpda_23>;
3209 };
3210 };
3211 };
3212 };
3213
3214 funnel@6005000 {
3215 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3216 reg = <0 0x06005000 0 0x1000>;
3217
3218 clocks = <&aoss_qmp>;
3219 clock-names = "apb_pclk";
3220
3221 out-ports {
3222 port {
3223 funnel_qatb_out_funnel_in0: endpoint {
3224 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
3225 };
3226 };
3227 };
3228
3229 in-ports {
3230 port {
3231 funnel_qatb_in_tpda: endpoint {
3232 remote-endpoint = <&tpda_out_funnel_qatb>;
3233 };
3234 };
3235 };
3236 };
3237
3238 funnel@6041000 {
3239 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3240 reg = <0 0x06041000 0 0x1000>;
3241
3242 clocks = <&aoss_qmp>;
3243 clock-names = "apb_pclk";
3244
3245 out-ports {
3246 port {
3247 funnel_in0_out_funnel_merg: endpoint {
3248 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3249 };
3250 };
3251 };
3252
3253 in-ports {
3254 #address-cells = <1>;
3255 #size-cells = <0>;
3256
3257 port@6 {
3258 reg = <6>;
3259 funnel_in0_in_funnel_qatb: endpoint {
3260 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
3261 };
3262 };
3263
3264 port@7 {
3265 reg = <7>;
3266 funnel0_in7: endpoint {
3267 remote-endpoint = <&stm_out>;
3268 };
3269 };
3270 };
3271 };
3272
3273 funnel@6042000 {
3274 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3275 reg = <0 0x06042000 0 0x1000>;
3276
3277 clocks = <&aoss_qmp>;
3278 clock-names = "apb_pclk";
3279
3280 out-ports {
3281 port {
3282 funnel_in1_out_funnel_merg: endpoint {
3283 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3284 };
3285 };
3286 };
3287
3288 in-ports {
3289 #address-cells = <1>;
3290 #size-cells = <0>;
3291
3292 port@4 {
3293 reg = <4>;
3294 funnel_in1_in_funnel_apss_merg: endpoint {
3295 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3296 };
3297 };
3298 };
3299 };
3300
3301 funnel@6045000 {
3302 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3303 reg = <0 0x06045000 0 0x1000>;
3304
3305 clocks = <&aoss_qmp>;
3306 clock-names = "apb_pclk";
3307
3308 out-ports {
3309 port {
3310 funnel_merg_out_funnel_swao: endpoint {
3311 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3312 };
3313 };
3314 };
3315
3316 in-ports {
3317 #address-cells = <1>;
3318 #size-cells = <0>;
3319
3320 port@0 {
3321 reg = <0>;
3322 funnel_merg_in_funnel_in0: endpoint {
3323 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3324 };
3325 };
3326
3327 port@1 {
3328 reg = <1>;
3329 funnel_merg_in_funnel_in1: endpoint {
3330 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3331 };
3332 };
3333 };
3334 };
3335
3336 replicator@6046000 {
3337 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3338 reg = <0 0x06046000 0 0x1000>;
3339
3340 clocks = <&aoss_qmp>;
3341 clock-names = "apb_pclk";
3342
3343 out-ports {
3344 port {
3345 replicator_out: endpoint {
3346 remote-endpoint = <&etr_in>;
3347 };
3348 };
3349 };
3350
3351 in-ports {
3352 port {
3353 replicator_cx_in_swao_out: endpoint {
3354 remote-endpoint = <&replicator_swao_out_cx_in>;
3355 };
3356 };
3357 };
3358 };
3359
3360 etr@6048000 {
3361 compatible = "arm,coresight-tmc", "arm,primecell";
3362 reg = <0 0x06048000 0 0x1000>;
3363
3364 clocks = <&aoss_qmp>;
3365 clock-names = "apb_pclk";
3366 arm,scatter-gather;
3367
3368 in-ports {
3369 port {
3370 etr_in: endpoint {
3371 remote-endpoint = <&replicator_out>;
3372 };
3373 };
3374 };
3375 };
3376
3377 tpdm@684c000 {
3378 compatible = "qcom,coresight-tpdm", "arm,primecell";
3379 reg = <0 0x0684c000 0 0x1000>;
3380
3381 clocks = <&aoss_qmp>;
3382 clock-names = "apb_pclk";
3383
3384 out-ports {
3385 port {
3386 tpdm_prng_out_tpda_23: endpoint {
3387 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3388 };
3389 };
3390 };
3391 };
3392
3393 funnel@6b04000 {
3394 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3395 arm,primecell-periphid = <0x000bb908>;
3396
3397 reg = <0 0x06b04000 0 0x1000>;
3398
3399 clocks = <&aoss_qmp>;
3400 clock-names = "apb_pclk";
3401
3402 out-ports {
3403 port {
3404 funnel_swao_out_etf: endpoint {
3405 remote-endpoint = <&etf_in_funnel_swao_out>;
3406 };
3407 };
3408 };
3409
3410 in-ports {
3411 #address-cells = <1>;
3412 #size-cells = <0>;
3413
3414 port@7 {
3415 reg = <7>;
3416 funnel_swao_in_funnel_merg: endpoint {
3417 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3418 };
3419 };
3420 };
3421 };
3422
3423 etf@6b05000 {
3424 compatible = "arm,coresight-tmc", "arm,primecell";
3425 reg = <0 0x06b05000 0 0x1000>;
3426
3427 clocks = <&aoss_qmp>;
3428 clock-names = "apb_pclk";
3429
3430 out-ports {
3431 port {
3432 etf_out: endpoint {
3433 remote-endpoint = <&replicator_in>;
3434 };
3435 };
3436 };
3437
3438 in-ports {
3439
3440 port {
3441 etf_in_funnel_swao_out: endpoint {
3442 remote-endpoint = <&funnel_swao_out_etf>;
3443 };
3444 };
3445 };
3446 };
3447
3448 replicator@6b06000 {
3449 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3450 reg = <0 0x06b06000 0 0x1000>;
3451
3452 clocks = <&aoss_qmp>;
3453 clock-names = "apb_pclk";
3454
3455 out-ports {
3456 port {
3457 replicator_swao_out_cx_in: endpoint {
3458 remote-endpoint = <&replicator_cx_in_swao_out>;
3459 };
3460 };
3461 };
3462
3463 in-ports {
3464 port {
3465 replicator_in: endpoint {
3466 remote-endpoint = <&etf_out>;
3467 };
3468 };
3469 };
3470 };
3471
3472 tpdm@6c08000 {
3473 compatible = "qcom,coresight-tpdm", "arm,primecell";
3474 reg = <0 0x06c08000 0 0x1000>;
3475
3476 clocks = <&aoss_qmp>;
3477 clock-names = "apb_pclk";
3478
3479 out-ports {
3480 port {
3481 tpdm_mm_out_funnel_dl_mm: endpoint {
3482 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3483 };
3484 };
3485 };
3486 };
3487
3488 funnel@6c0b000 {
3489 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3490 reg = <0 0x06c0b000 0 0x1000>;
3491
3492 clocks = <&aoss_qmp>;
3493 clock-names = "apb_pclk";
3494
3495 out-ports {
3496 port {
3497 funnel_dl_mm_out_funnel_dl_center: endpoint {
3498 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3499 };
3500 };
3501 };
3502
3503 in-ports {
3504 #address-cells = <1>;
3505 #size-cells = <0>;
3506
3507 port@3 {
3508 reg = <3>;
3509 funnel_dl_mm_in_tpdm_mm: endpoint {
3510 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3511 };
3512 };
3513 };
3514 };
3515
3516 funnel@6c2d000 {
3517 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3518 reg = <0 0x06c2d000 0 0x1000>;
3519
3520 clocks = <&aoss_qmp>;
3521 clock-names = "apb_pclk";
3522
3523 out-ports {
3524 port {
3525 tpdm_mm_out_tpda9: endpoint {
3526 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3527 };
3528 };
3529 };
3530
3531 in-ports {
3532 #address-cells = <1>;
3533 #size-cells = <0>;
3534
3535 port@2 {
3536 reg = <2>;
3537 funnel_dl_center_in_funnel_dl_mm: endpoint {
3538 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3539 };
3540 };
3541 };
3542 };
3543
3544 etm@7040000 {
3545 compatible = "arm,coresight-etm4x", "arm,primecell";
3546 reg = <0 0x07040000 0 0x1000>;
3547
3548 cpu = <&CPU0>;
3549
3550 clocks = <&aoss_qmp>;
3551 clock-names = "apb_pclk";
3552 arm,coresight-loses-context-with-cpu;
3553
3554 out-ports {
3555 port {
3556 etm0_out: endpoint {
3557 remote-endpoint = <&apss_funnel_in0>;
3558 };
3559 };
3560 };
3561 };
3562
3563 etm@7140000 {
3564 compatible = "arm,coresight-etm4x", "arm,primecell";
3565 reg = <0 0x07140000 0 0x1000>;
3566
3567 cpu = <&CPU1>;
3568
3569 clocks = <&aoss_qmp>;
3570 clock-names = "apb_pclk";
3571 arm,coresight-loses-context-with-cpu;
3572
3573 out-ports {
3574 port {
3575 etm1_out: endpoint {
3576 remote-endpoint = <&apss_funnel_in1>;
3577 };
3578 };
3579 };
3580 };
3581
3582 etm@7240000 {
3583 compatible = "arm,coresight-etm4x", "arm,primecell";
3584 reg = <0 0x07240000 0 0x1000>;
3585
3586 cpu = <&CPU2>;
3587
3588 clocks = <&aoss_qmp>;
3589 clock-names = "apb_pclk";
3590 arm,coresight-loses-context-with-cpu;
3591
3592 out-ports {
3593 port {
3594 etm2_out: endpoint {
3595 remote-endpoint = <&apss_funnel_in2>;
3596 };
3597 };
3598 };
3599 };
3600
3601 etm@7340000 {
3602 compatible = "arm,coresight-etm4x", "arm,primecell";
3603 reg = <0 0x07340000 0 0x1000>;
3604
3605 cpu = <&CPU3>;
3606
3607 clocks = <&aoss_qmp>;
3608 clock-names = "apb_pclk";
3609 arm,coresight-loses-context-with-cpu;
3610
3611 out-ports {
3612 port {
3613 etm3_out: endpoint {
3614 remote-endpoint = <&apss_funnel_in3>;
3615 };
3616 };
3617 };
3618 };
3619
3620 etm@7440000 {
3621 compatible = "arm,coresight-etm4x", "arm,primecell";
3622 reg = <0 0x07440000 0 0x1000>;
3623
3624 cpu = <&CPU4>;
3625
3626 clocks = <&aoss_qmp>;
3627 clock-names = "apb_pclk";
3628 arm,coresight-loses-context-with-cpu;
3629
3630 out-ports {
3631 port {
3632 etm4_out: endpoint {
3633 remote-endpoint = <&apss_funnel_in4>;
3634 };
3635 };
3636 };
3637 };
3638
3639 etm@7540000 {
3640 compatible = "arm,coresight-etm4x", "arm,primecell";
3641 reg = <0 0x07540000 0 0x1000>;
3642
3643 cpu = <&CPU5>;
3644
3645 clocks = <&aoss_qmp>;
3646 clock-names = "apb_pclk";
3647 arm,coresight-loses-context-with-cpu;
3648
3649 out-ports {
3650 port {
3651 etm5_out: endpoint {
3652 remote-endpoint = <&apss_funnel_in5>;
3653 };
3654 };
3655 };
3656 };
3657
3658 etm@7640000 {
3659 compatible = "arm,coresight-etm4x", "arm,primecell";
3660 reg = <0 0x07640000 0 0x1000>;
3661
3662 cpu = <&CPU6>;
3663
3664 clocks = <&aoss_qmp>;
3665 clock-names = "apb_pclk";
3666 arm,coresight-loses-context-with-cpu;
3667
3668 out-ports {
3669 port {
3670 etm6_out: endpoint {
3671 remote-endpoint = <&apss_funnel_in6>;
3672 };
3673 };
3674 };
3675 };
3676
3677 etm@7740000 {
3678 compatible = "arm,coresight-etm4x", "arm,primecell";
3679 reg = <0 0x07740000 0 0x1000>;
3680
3681 cpu = <&CPU7>;
3682
3683 clocks = <&aoss_qmp>;
3684 clock-names = "apb_pclk";
3685 arm,coresight-loses-context-with-cpu;
3686
3687 out-ports {
3688 port {
3689 etm7_out: endpoint {
3690 remote-endpoint = <&apss_funnel_in7>;
3691 };
3692 };
3693 };
3694 };
3695
3696 funnel@7800000 {
3697 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3698 reg = <0 0x07800000 0 0x1000>;
3699
3700 clocks = <&aoss_qmp>;
3701 clock-names = "apb_pclk";
3702
3703 out-ports {
3704 port {
3705 funnel_apss_out_funnel_apss_merg: endpoint {
3706 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3707 };
3708 };
3709 };
3710
3711 in-ports {
3712 #address-cells = <1>;
3713 #size-cells = <0>;
3714
3715 port@0 {
3716 reg = <0>;
3717 apss_funnel_in0: endpoint {
3718 remote-endpoint = <&etm0_out>;
3719 };
3720 };
3721
3722 port@1 {
3723 reg = <1>;
3724 apss_funnel_in1: endpoint {
3725 remote-endpoint = <&etm1_out>;
3726 };
3727 };
3728
3729 port@2 {
3730 reg = <2>;
3731 apss_funnel_in2: endpoint {
3732 remote-endpoint = <&etm2_out>;
3733 };
3734 };
3735
3736 port@3 {
3737 reg = <3>;
3738 apss_funnel_in3: endpoint {
3739 remote-endpoint = <&etm3_out>;
3740 };
3741 };
3742
3743 port@4 {
3744 reg = <4>;
3745 apss_funnel_in4: endpoint {
3746 remote-endpoint = <&etm4_out>;
3747 };
3748 };
3749
3750 port@5 {
3751 reg = <5>;
3752 apss_funnel_in5: endpoint {
3753 remote-endpoint = <&etm5_out>;
3754 };
3755 };
3756
3757 port@6 {
3758 reg = <6>;
3759 apss_funnel_in6: endpoint {
3760 remote-endpoint = <&etm6_out>;
3761 };
3762 };
3763
3764 port@7 {
3765 reg = <7>;
3766 apss_funnel_in7: endpoint {
3767 remote-endpoint = <&etm7_out>;
3768 };
3769 };
3770 };
3771 };
3772
3773 funnel@7810000 {
3774 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3775 reg = <0 0x07810000 0 0x1000>;
3776
3777 clocks = <&aoss_qmp>;
3778 clock-names = "apb_pclk";
3779
3780 out-ports {
3781 port {
3782 funnel_apss_merg_out_funnel_in1: endpoint {
3783 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3784 };
3785 };
3786 };
3787
3788 in-ports {
3789 port {
3790 funnel_apss_merg_in_funnel_apss: endpoint {
3791 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3792 };
3793 };
3794 };
3795 };
3796
3797 cdsp: remoteproc@8300000 {
3798 compatible = "qcom,sm8250-cdsp-pas";
3799 reg = <0 0x08300000 0 0x10000>;
3800
3801 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3802 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3803 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3804 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3805 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3806 interrupt-names = "wdog", "fatal", "ready",
3807 "handover", "stop-ack";
3808
3809 clocks = <&rpmhcc RPMH_CXO_CLK>;
3810 clock-names = "xo";
3811
3812 power-domains = <&rpmhpd RPMHPD_CX>;
3813
3814 memory-region = <&cdsp_mem>;
3815
3816 qcom,qmp = <&aoss_qmp>;
3817
3818 qcom,smem-states = <&smp2p_cdsp_out 0>;
3819 qcom,smem-state-names = "stop";
3820
3821 status = "disabled";
3822
3823 glink-edge {
3824 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3825 IPCC_MPROC_SIGNAL_GLINK_QMP
3826 IRQ_TYPE_EDGE_RISING>;
3827 mboxes = <&ipcc IPCC_CLIENT_CDSP
3828 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3829
3830 label = "cdsp";
3831 qcom,remote-pid = <5>;
3832
3833 fastrpc {
3834 compatible = "qcom,fastrpc";
3835 qcom,glink-channels = "fastrpcglink-apps-dsp";
3836 label = "cdsp";
3837 qcom,non-secure-domain;
3838 #address-cells = <1>;
3839 #size-cells = <0>;
3840
3841 compute-cb@1 {
3842 compatible = "qcom,fastrpc-compute-cb";
3843 reg = <1>;
3844 iommus = <&apps_smmu 0x1001 0x0460>;
3845 };
3846
3847 compute-cb@2 {
3848 compatible = "qcom,fastrpc-compute-cb";
3849 reg = <2>;
3850 iommus = <&apps_smmu 0x1002 0x0460>;
3851 };
3852
3853 compute-cb@3 {
3854 compatible = "qcom,fastrpc-compute-cb";
3855 reg = <3>;
3856 iommus = <&apps_smmu 0x1003 0x0460>;
3857 };
3858
3859 compute-cb@4 {
3860 compatible = "qcom,fastrpc-compute-cb";
3861 reg = <4>;
3862 iommus = <&apps_smmu 0x1004 0x0460>;
3863 };
3864
3865 compute-cb@5 {
3866 compatible = "qcom,fastrpc-compute-cb";
3867 reg = <5>;
3868 iommus = <&apps_smmu 0x1005 0x0460>;
3869 };
3870
3871 compute-cb@6 {
3872 compatible = "qcom,fastrpc-compute-cb";
3873 reg = <6>;
3874 iommus = <&apps_smmu 0x1006 0x0460>;
3875 };
3876
3877 compute-cb@7 {
3878 compatible = "qcom,fastrpc-compute-cb";
3879 reg = <7>;
3880 iommus = <&apps_smmu 0x1007 0x0460>;
3881 };
3882
3883 compute-cb@8 {
3884 compatible = "qcom,fastrpc-compute-cb";
3885 reg = <8>;
3886 iommus = <&apps_smmu 0x1008 0x0460>;
3887 };
3888
3889 /* note: secure cb9 in downstream */
3890 };
3891 };
3892 };
3893
3894 usb_1_hsphy: phy@88e3000 {
3895 compatible = "qcom,sm8250-usb-hs-phy",
3896 "qcom,usb-snps-hs-7nm-phy";
3897 reg = <0 0x088e3000 0 0x400>;
3898 status = "disabled";
3899 #phy-cells = <0>;
3900
3901 clocks = <&rpmhcc RPMH_CXO_CLK>;
3902 clock-names = "ref";
3903
3904 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3905 };
3906
3907 usb_2_hsphy: phy@88e4000 {
3908 compatible = "qcom,sm8250-usb-hs-phy",
3909 "qcom,usb-snps-hs-7nm-phy";
3910 reg = <0 0x088e4000 0 0x400>;
3911 status = "disabled";
3912 #phy-cells = <0>;
3913
3914 clocks = <&rpmhcc RPMH_CXO_CLK>;
3915 clock-names = "ref";
3916
3917 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3918 };
3919
3920 usb_1_qmpphy: phy@88e8000 {
3921 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3922 reg = <0 0x088e8000 0 0x3000>;
3923 status = "disabled";
3924
3925 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3926 <&rpmhcc RPMH_CXO_CLK>,
3927 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3928 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3929 clock-names = "aux",
3930 "ref",
3931 "com_aux",
3932 "usb3_pipe";
3933
3934 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3935 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3936 reset-names = "phy", "common";
3937
3938 #clock-cells = <1>;
3939 #phy-cells = <1>;
3940
3941 orientation-switch;
3942
3943 ports {
3944 #address-cells = <1>;
3945 #size-cells = <0>;
3946
3947 port@0 {
3948 reg = <0>;
3949 usb_1_qmpphy_out: endpoint {};
3950 };
3951
3952 port@1 {
3953 reg = <1>;
3954
3955 usb_1_qmpphy_usb_ss_in: endpoint {
3956 remote-endpoint = <&usb_1_dwc3_ss_out>;
3957 };
3958 };
3959
3960 port@2 {
3961 reg = <2>;
3962
3963 usb_1_qmpphy_dp_in: endpoint {};
3964 };
3965 };
3966 };
3967
3968 usb_2_qmpphy: phy@88eb000 {
3969 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3970 reg = <0 0x088eb000 0 0x1000>;
3971
3972 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3973 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3974 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3975 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3976 clock-names = "aux",
3977 "ref",
3978 "com_aux",
3979 "pipe";
3980 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3981 #clock-cells = <0>;
3982 #phy-cells = <0>;
3983
3984 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3985 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
3986 reset-names = "phy",
3987 "phy_phy";
3988
3989 status = "disabled";
3990 };
3991
3992 sdhc_2: mmc@8804000 {
3993 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3994 reg = <0 0x08804000 0 0x1000>;
3995
3996 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3997 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3998 interrupt-names = "hc_irq", "pwr_irq";
3999
4000 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4001 <&gcc GCC_SDCC2_APPS_CLK>,
4002 <&rpmhcc RPMH_CXO_CLK>;
4003 clock-names = "iface", "core", "xo";
4004 iommus = <&apps_smmu 0x4a0 0x0>;
4005 qcom,dll-config = <0x0007642c>;
4006 qcom,ddr-config = <0x80040868>;
4007 power-domains = <&rpmhpd RPMHPD_CX>;
4008 operating-points-v2 = <&sdhc2_opp_table>;
4009
4010 status = "disabled";
4011
4012 sdhc2_opp_table: opp-table {
4013 compatible = "operating-points-v2";
4014
4015 opp-19200000 {
4016 opp-hz = /bits/ 64 <19200000>;
4017 required-opps = <&rpmhpd_opp_min_svs>;
4018 };
4019
4020 opp-50000000 {
4021 opp-hz = /bits/ 64 <50000000>;
4022 required-opps = <&rpmhpd_opp_low_svs>;
4023 };
4024
4025 opp-100000000 {
4026 opp-hz = /bits/ 64 <100000000>;
4027 required-opps = <&rpmhpd_opp_svs>;
4028 };
4029
4030 opp-202000000 {
4031 opp-hz = /bits/ 64 <202000000>;
4032 required-opps = <&rpmhpd_opp_svs_l1>;
4033 };
4034 };
4035 };
4036
4037 pmu@9091000 {
4038 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4039 reg = <0 0x09091000 0 0x1000>;
4040
4041 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
4042
4043 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>;
4044
4045 operating-points-v2 = <&llcc_bwmon_opp_table>;
4046
4047 llcc_bwmon_opp_table: opp-table {
4048 compatible = "operating-points-v2";
4049
4050 opp-800000 {
4051 opp-peak-kBps = <(200 * 4 * 1000)>;
4052 };
4053
4054 opp-1200000 {
4055 opp-peak-kBps = <(300 * 4 * 1000)>;
4056 };
4057
4058 opp-1804000 {
4059 opp-peak-kBps = <(451 * 4 * 1000)>;
4060 };
4061
4062 opp-2188000 {
4063 opp-peak-kBps = <(547 * 4 * 1000)>;
4064 };
4065
4066 opp-2724000 {
4067 opp-peak-kBps = <(681 * 4 * 1000)>;
4068 };
4069
4070 opp-3072000 {
4071 opp-peak-kBps = <(768 * 4 * 1000)>;
4072 };
4073
4074 opp-4068000 {
4075 opp-peak-kBps = <(1017 * 4 * 1000)>;
4076 };
4077
4078 /* 1353 MHz, LPDDR4X */
4079
4080 opp-6220000 {
4081 opp-peak-kBps = <(1555 * 4 * 1000)>;
4082 };
4083
4084 opp-7216000 {
4085 opp-peak-kBps = <(1804 * 4 * 1000)>;
4086 };
4087
4088 opp-8368000 {
4089 opp-peak-kBps = <(2092 * 4 * 1000)>;
4090 };
4091
4092 /* LPDDR5 */
4093 opp-10944000 {
4094 opp-peak-kBps = <(2736 * 4 * 1000)>;
4095 };
4096 };
4097 };
4098
4099 pmu@90b6400 {
4100 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
4101 reg = <0 0x090b6400 0 0x600>;
4102
4103 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
4104
4105 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>;
4106 operating-points-v2 = <&cpu_bwmon_opp_table>;
4107
4108 cpu_bwmon_opp_table: opp-table {
4109 compatible = "operating-points-v2";
4110
4111 opp-800000 {
4112 opp-peak-kBps = <(200 * 4 * 1000)>;
4113 };
4114
4115 opp-1804000 {
4116 opp-peak-kBps = <(451 * 4 * 1000)>;
4117 };
4118
4119 opp-2188000 {
4120 opp-peak-kBps = <(547 * 4 * 1000)>;
4121 };
4122
4123 opp-2724000 {
4124 opp-peak-kBps = <(681 * 4 * 1000)>;
4125 };
4126
4127 opp-3072000 {
4128 opp-peak-kBps = <(768 * 4 * 1000)>;
4129 };
4130
4131 /* 1017MHz, 1353 MHz, LPDDR4X */
4132
4133 opp-6220000 {
4134 opp-peak-kBps = <(1555 * 4 * 1000)>;
4135 };
4136
4137 opp-6832000 {
4138 opp-peak-kBps = <(1708 * 4 * 1000)>;
4139 };
4140
4141 opp-8368000 {
4142 opp-peak-kBps = <(2092 * 4 * 1000)>;
4143 };
4144
4145 /* 2133MHz, LPDDR4X */
4146
4147 /* LPDDR5 */
4148 opp-10944000 {
4149 opp-peak-kBps = <(2736 * 4 * 1000)>;
4150 };
4151
4152 /* LPDDR5 */
4153 opp-12784000 {
4154 opp-peak-kBps = <(3196 * 4 * 1000)>;
4155 };
4156 };
4157 };
4158
4159 dc_noc: interconnect@90c0000 {
4160 compatible = "qcom,sm8250-dc-noc";
4161 reg = <0 0x090c0000 0 0x4200>;
4162 #interconnect-cells = <2>;
4163 qcom,bcm-voters = <&apps_bcm_voter>;
4164 };
4165
4166 gem_noc: interconnect@9100000 {
4167 compatible = "qcom,sm8250-gem-noc";
4168 reg = <0 0x09100000 0 0xb4000>;
4169 #interconnect-cells = <2>;
4170 qcom,bcm-voters = <&apps_bcm_voter>;
4171 };
4172
4173 npu_noc: interconnect@9990000 {
4174 compatible = "qcom,sm8250-npu-noc";
4175 reg = <0 0x09990000 0 0x1600>;
4176 #interconnect-cells = <2>;
4177 qcom,bcm-voters = <&apps_bcm_voter>;
4178 };
4179
4180 usb_1: usb@a6f8800 {
4181 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4182 reg = <0 0x0a6f8800 0 0x400>;
4183 status = "disabled";
4184 #address-cells = <2>;
4185 #size-cells = <2>;
4186 ranges;
4187 dma-ranges;
4188
4189 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4190 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4191 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4192 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4193 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4194 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4195 clock-names = "cfg_noc",
4196 "core",
4197 "iface",
4198 "sleep",
4199 "mock_utmi",
4200 "xo";
4201
4202 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4203 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4204 assigned-clock-rates = <19200000>, <200000000>;
4205
4206 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4207 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4208 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4209 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4210 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4211 interrupt-names = "pwr_event",
4212 "hs_phy_irq",
4213 "dp_hs_phy_irq",
4214 "dm_hs_phy_irq",
4215 "ss_phy_irq";
4216
4217 power-domains = <&gcc USB30_PRIM_GDSC>;
4218 wakeup-source;
4219
4220 resets = <&gcc GCC_USB30_PRIM_BCR>;
4221
4222 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
4223 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
4224 interconnect-names = "usb-ddr", "apps-usb";
4225
4226 usb_1_dwc3: usb@a600000 {
4227 compatible = "snps,dwc3";
4228 reg = <0 0x0a600000 0 0xcd00>;
4229 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4230 iommus = <&apps_smmu 0x0 0x0>;
4231 snps,dis_u2_susphy_quirk;
4232 snps,dis_enblslpm_quirk;
4233 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4234 phy-names = "usb2-phy", "usb3-phy";
4235
4236 ports {
4237 #address-cells = <1>;
4238 #size-cells = <0>;
4239
4240 port@0 {
4241 reg = <0>;
4242
4243 usb_1_dwc3_hs_out: endpoint {
4244 };
4245 };
4246
4247 port@1 {
4248 reg = <1>;
4249
4250 usb_1_dwc3_ss_out: endpoint {
4251 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
4252 };
4253 };
4254 };
4255 };
4256 };
4257
4258 system-cache-controller@9200000 {
4259 compatible = "qcom,sm8250-llcc";
4260 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
4261 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
4262 <0 0x09600000 0 0x50000>;
4263 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4264 "llcc3_base", "llcc_broadcast_base";
4265 };
4266
4267 usb_2: usb@a8f8800 {
4268 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4269 reg = <0 0x0a8f8800 0 0x400>;
4270 status = "disabled";
4271 #address-cells = <2>;
4272 #size-cells = <2>;
4273 ranges;
4274 dma-ranges;
4275
4276 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4277 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4278 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4279 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4280 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4281 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4282 clock-names = "cfg_noc",
4283 "core",
4284 "iface",
4285 "sleep",
4286 "mock_utmi",
4287 "xo";
4288
4289 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4290 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4291 assigned-clock-rates = <19200000>, <200000000>;
4292
4293 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
4294 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4295 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
4296 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4297 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
4298 interrupt-names = "pwr_event",
4299 "hs_phy_irq",
4300 "dp_hs_phy_irq",
4301 "dm_hs_phy_irq",
4302 "ss_phy_irq";
4303
4304 power-domains = <&gcc USB30_SEC_GDSC>;
4305 wakeup-source;
4306
4307 resets = <&gcc GCC_USB30_SEC_BCR>;
4308
4309 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
4310 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
4311 interconnect-names = "usb-ddr", "apps-usb";
4312
4313 usb_2_dwc3: usb@a800000 {
4314 compatible = "snps,dwc3";
4315 reg = <0 0x0a800000 0 0xcd00>;
4316 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4317 iommus = <&apps_smmu 0x20 0>;
4318 snps,dis_u2_susphy_quirk;
4319 snps,dis_enblslpm_quirk;
4320 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
4321 phy-names = "usb2-phy", "usb3-phy";
4322 };
4323 };
4324
4325 venus: video-codec@aa00000 {
4326 compatible = "qcom,sm8250-venus";
4327 reg = <0 0x0aa00000 0 0x100000>;
4328 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4329 power-domains = <&videocc MVS0C_GDSC>,
4330 <&videocc MVS0_GDSC>,
4331 <&rpmhpd RPMHPD_MX>;
4332 power-domain-names = "venus", "vcodec0", "mx";
4333 operating-points-v2 = <&venus_opp_table>;
4334
4335 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4336 <&videocc VIDEO_CC_MVS0C_CLK>,
4337 <&videocc VIDEO_CC_MVS0_CLK>;
4338 clock-names = "iface", "core", "vcodec0_core";
4339
4340 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
4341 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
4342 interconnect-names = "cpu-cfg", "video-mem";
4343
4344 iommus = <&apps_smmu 0x2100 0x0400>;
4345 memory-region = <&video_mem>;
4346
4347 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4348 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4349 reset-names = "bus", "core";
4350
4351 status = "disabled";
4352
4353 video-decoder {
4354 compatible = "venus-decoder";
4355 };
4356
4357 video-encoder {
4358 compatible = "venus-encoder";
4359 };
4360
4361 venus_opp_table: opp-table {
4362 compatible = "operating-points-v2";
4363
4364 opp-720000000 {
4365 opp-hz = /bits/ 64 <720000000>;
4366 required-opps = <&rpmhpd_opp_low_svs>;
4367 };
4368
4369 opp-1014000000 {
4370 opp-hz = /bits/ 64 <1014000000>;
4371 required-opps = <&rpmhpd_opp_svs>;
4372 };
4373
4374 opp-1098000000 {
4375 opp-hz = /bits/ 64 <1098000000>;
4376 required-opps = <&rpmhpd_opp_svs_l1>;
4377 };
4378
4379 opp-1332000000 {
4380 opp-hz = /bits/ 64 <1332000000>;
4381 required-opps = <&rpmhpd_opp_nom>;
4382 };
4383 };
4384 };
4385
4386 videocc: clock-controller@abf0000 {
4387 compatible = "qcom,sm8250-videocc";
4388 reg = <0 0x0abf0000 0 0x10000>;
4389 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4390 <&rpmhcc RPMH_CXO_CLK>,
4391 <&rpmhcc RPMH_CXO_CLK_A>;
4392 power-domains = <&rpmhpd RPMHPD_MMCX>;
4393 required-opps = <&rpmhpd_opp_low_svs>;
4394 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4395 #clock-cells = <1>;
4396 #reset-cells = <1>;
4397 #power-domain-cells = <1>;
4398 };
4399
4400 cci0: cci@ac4f000 {
4401 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4402 #address-cells = <1>;
4403 #size-cells = <0>;
4404
4405 reg = <0 0x0ac4f000 0 0x1000>;
4406 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4407 power-domains = <&camcc TITAN_TOP_GDSC>;
4408
4409 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4410 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4411 <&camcc CAM_CC_CPAS_AHB_CLK>,
4412 <&camcc CAM_CC_CCI_0_CLK>,
4413 <&camcc CAM_CC_CCI_0_CLK_SRC>;
4414 clock-names = "camnoc_axi",
4415 "slow_ahb_src",
4416 "cpas_ahb",
4417 "cci",
4418 "cci_src";
4419
4420 pinctrl-0 = <&cci0_default>;
4421 pinctrl-1 = <&cci0_sleep>;
4422 pinctrl-names = "default", "sleep";
4423
4424 status = "disabled";
4425
4426 cci0_i2c0: i2c-bus@0 {
4427 reg = <0>;
4428 clock-frequency = <1000000>;
4429 #address-cells = <1>;
4430 #size-cells = <0>;
4431 };
4432
4433 cci0_i2c1: i2c-bus@1 {
4434 reg = <1>;
4435 clock-frequency = <1000000>;
4436 #address-cells = <1>;
4437 #size-cells = <0>;
4438 };
4439 };
4440
4441 cci1: cci@ac50000 {
4442 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4443 #address-cells = <1>;
4444 #size-cells = <0>;
4445
4446 reg = <0 0x0ac50000 0 0x1000>;
4447 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4448 power-domains = <&camcc TITAN_TOP_GDSC>;
4449
4450 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4451 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4452 <&camcc CAM_CC_CPAS_AHB_CLK>,
4453 <&camcc CAM_CC_CCI_1_CLK>,
4454 <&camcc CAM_CC_CCI_1_CLK_SRC>;
4455 clock-names = "camnoc_axi",
4456 "slow_ahb_src",
4457 "cpas_ahb",
4458 "cci",
4459 "cci_src";
4460
4461 pinctrl-0 = <&cci1_default>;
4462 pinctrl-1 = <&cci1_sleep>;
4463 pinctrl-names = "default", "sleep";
4464
4465 status = "disabled";
4466
4467 cci1_i2c0: i2c-bus@0 {
4468 reg = <0>;
4469 clock-frequency = <1000000>;
4470 #address-cells = <1>;
4471 #size-cells = <0>;
4472 };
4473
4474 cci1_i2c1: i2c-bus@1 {
4475 reg = <1>;
4476 clock-frequency = <1000000>;
4477 #address-cells = <1>;
4478 #size-cells = <0>;
4479 };
4480 };
4481
4482 camss: camss@ac6a000 {
4483 compatible = "qcom,sm8250-camss";
4484 status = "disabled";
4485
4486 reg = <0 0x0ac6a000 0 0x2000>,
4487 <0 0x0ac6c000 0 0x2000>,
4488 <0 0x0ac6e000 0 0x1000>,
4489 <0 0x0ac70000 0 0x1000>,
4490 <0 0x0ac72000 0 0x1000>,
4491 <0 0x0ac74000 0 0x1000>,
4492 <0 0x0acb4000 0 0xd000>,
4493 <0 0x0acc3000 0 0xd000>,
4494 <0 0x0acd9000 0 0x2200>,
4495 <0 0x0acdb200 0 0x2200>;
4496 reg-names = "csiphy0",
4497 "csiphy1",
4498 "csiphy2",
4499 "csiphy3",
4500 "csiphy4",
4501 "csiphy5",
4502 "vfe0",
4503 "vfe1",
4504 "vfe_lite0",
4505 "vfe_lite1";
4506
4507 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4508 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4509 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4510 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4511 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4512 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4513 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4514 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4515 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4516 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
4517 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4518 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4519 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
4520 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4521 interrupt-names = "csiphy0",
4522 "csiphy1",
4523 "csiphy2",
4524 "csiphy3",
4525 "csiphy4",
4526 "csiphy5",
4527 "csid0",
4528 "csid1",
4529 "csid2",
4530 "csid3",
4531 "vfe0",
4532 "vfe1",
4533 "vfe_lite0",
4534 "vfe_lite1";
4535
4536 power-domains = <&camcc IFE_0_GDSC>,
4537 <&camcc IFE_1_GDSC>,
4538 <&camcc TITAN_TOP_GDSC>;
4539
4540 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4541 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4542 <&gcc GCC_CAMERA_SF_AXI_CLK>,
4543 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4544 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
4545 <&camcc CAM_CC_CORE_AHB_CLK>,
4546 <&camcc CAM_CC_CPAS_AHB_CLK>,
4547 <&camcc CAM_CC_CSIPHY0_CLK>,
4548 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
4549 <&camcc CAM_CC_CSIPHY1_CLK>,
4550 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4551 <&camcc CAM_CC_CSIPHY2_CLK>,
4552 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4553 <&camcc CAM_CC_CSIPHY3_CLK>,
4554 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
4555 <&camcc CAM_CC_CSIPHY4_CLK>,
4556 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
4557 <&camcc CAM_CC_CSIPHY5_CLK>,
4558 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
4559 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4560 <&camcc CAM_CC_IFE_0_AHB_CLK>,
4561 <&camcc CAM_CC_IFE_0_AXI_CLK>,
4562 <&camcc CAM_CC_IFE_0_CLK>,
4563 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4564 <&camcc CAM_CC_IFE_0_CSID_CLK>,
4565 <&camcc CAM_CC_IFE_0_AREG_CLK>,
4566 <&camcc CAM_CC_IFE_1_AHB_CLK>,
4567 <&camcc CAM_CC_IFE_1_AXI_CLK>,
4568 <&camcc CAM_CC_IFE_1_CLK>,
4569 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4570 <&camcc CAM_CC_IFE_1_CSID_CLK>,
4571 <&camcc CAM_CC_IFE_1_AREG_CLK>,
4572 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
4573 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
4574 <&camcc CAM_CC_IFE_LITE_CLK>,
4575 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4576 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
4577
4578 clock-names = "cam_ahb_clk",
4579 "cam_hf_axi",
4580 "cam_sf_axi",
4581 "camnoc_axi",
4582 "camnoc_axi_src",
4583 "core_ahb",
4584 "cpas_ahb",
4585 "csiphy0",
4586 "csiphy0_timer",
4587 "csiphy1",
4588 "csiphy1_timer",
4589 "csiphy2",
4590 "csiphy2_timer",
4591 "csiphy3",
4592 "csiphy3_timer",
4593 "csiphy4",
4594 "csiphy4_timer",
4595 "csiphy5",
4596 "csiphy5_timer",
4597 "slow_ahb_src",
4598 "vfe0_ahb",
4599 "vfe0_axi",
4600 "vfe0",
4601 "vfe0_cphy_rx",
4602 "vfe0_csid",
4603 "vfe0_areg",
4604 "vfe1_ahb",
4605 "vfe1_axi",
4606 "vfe1",
4607 "vfe1_cphy_rx",
4608 "vfe1_csid",
4609 "vfe1_areg",
4610 "vfe_lite_ahb",
4611 "vfe_lite_axi",
4612 "vfe_lite",
4613 "vfe_lite_cphy_rx",
4614 "vfe_lite_csid";
4615
4616 iommus = <&apps_smmu 0x800 0x400>,
4617 <&apps_smmu 0x801 0x400>,
4618 <&apps_smmu 0x840 0x400>,
4619 <&apps_smmu 0x841 0x400>,
4620 <&apps_smmu 0xc00 0x400>,
4621 <&apps_smmu 0xc01 0x400>,
4622 <&apps_smmu 0xc40 0x400>,
4623 <&apps_smmu 0xc41 0x400>;
4624
4625 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4626 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4627 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4628 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4629 interconnect-names = "cam_ahb",
4630 "cam_hf_0_mnoc",
4631 "cam_sf_0_mnoc",
4632 "cam_sf_icp_mnoc";
4633
4634 ports {
4635 #address-cells = <1>;
4636 #size-cells = <0>;
4637
4638 port@0 {
4639 reg = <0>;
4640 };
4641
4642 port@1 {
4643 reg = <1>;
4644 };
4645
4646 port@2 {
4647 reg = <2>;
4648 };
4649
4650 port@3 {
4651 reg = <3>;
4652 };
4653
4654 port@4 {
4655 reg = <4>;
4656 };
4657
4658 port@5 {
4659 reg = <5>;
4660 };
4661 };
4662 };
4663
4664 camcc: clock-controller@ad00000 {
4665 compatible = "qcom,sm8250-camcc";
4666 reg = <0 0x0ad00000 0 0x10000>;
4667 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4668 <&rpmhcc RPMH_CXO_CLK>,
4669 <&rpmhcc RPMH_CXO_CLK_A>,
4670 <&sleep_clk>;
4671 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4672 power-domains = <&rpmhpd RPMHPD_MMCX>;
4673 required-opps = <&rpmhpd_opp_low_svs>;
4674 status = "disabled";
4675 #clock-cells = <1>;
4676 #reset-cells = <1>;
4677 #power-domain-cells = <1>;
4678 };
4679
4680 mdss: display-subsystem@ae00000 {
4681 compatible = "qcom,sm8250-mdss";
4682 reg = <0 0x0ae00000 0 0x1000>;
4683 reg-names = "mdss";
4684
4685 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4686 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4687 interconnect-names = "mdp0-mem", "mdp1-mem";
4688
4689 power-domains = <&dispcc MDSS_GDSC>;
4690
4691 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4692 <&gcc GCC_DISP_HF_AXI_CLK>,
4693 <&gcc GCC_DISP_SF_AXI_CLK>,
4694 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4695 clock-names = "iface", "bus", "nrt_bus", "core";
4696
4697 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4698 interrupt-controller;
4699 #interrupt-cells = <1>;
4700
4701 iommus = <&apps_smmu 0x820 0x402>;
4702
4703 status = "disabled";
4704
4705 #address-cells = <2>;
4706 #size-cells = <2>;
4707 ranges;
4708
4709 mdss_mdp: display-controller@ae01000 {
4710 compatible = "qcom,sm8250-dpu";
4711 reg = <0 0x0ae01000 0 0x8f000>,
4712 <0 0x0aeb0000 0 0x2008>;
4713 reg-names = "mdp", "vbif";
4714
4715 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4716 <&gcc GCC_DISP_HF_AXI_CLK>,
4717 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4718 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4719 clock-names = "iface", "bus", "core", "vsync";
4720
4721 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4722 assigned-clock-rates = <19200000>;
4723
4724 operating-points-v2 = <&mdp_opp_table>;
4725 power-domains = <&rpmhpd RPMHPD_MMCX>;
4726
4727 interrupt-parent = <&mdss>;
4728 interrupts = <0>;
4729
4730 ports {
4731 #address-cells = <1>;
4732 #size-cells = <0>;
4733
4734 port@0 {
4735 reg = <0>;
4736 dpu_intf1_out: endpoint {
4737 remote-endpoint = <&mdss_dsi0_in>;
4738 };
4739 };
4740
4741 port@1 {
4742 reg = <1>;
4743 dpu_intf2_out: endpoint {
4744 remote-endpoint = <&mdss_dsi1_in>;
4745 };
4746 };
4747
4748 port@2 {
4749 reg = <2>;
4750
4751 dpu_intf0_out: endpoint {
4752 remote-endpoint = <&mdss_dp_in>;
4753 };
4754 };
4755 };
4756
4757 mdp_opp_table: opp-table {
4758 compatible = "operating-points-v2";
4759
4760 opp-200000000 {
4761 opp-hz = /bits/ 64 <200000000>;
4762 required-opps = <&rpmhpd_opp_low_svs>;
4763 };
4764
4765 opp-300000000 {
4766 opp-hz = /bits/ 64 <300000000>;
4767 required-opps = <&rpmhpd_opp_svs>;
4768 };
4769
4770 opp-345000000 {
4771 opp-hz = /bits/ 64 <345000000>;
4772 required-opps = <&rpmhpd_opp_svs_l1>;
4773 };
4774
4775 opp-460000000 {
4776 opp-hz = /bits/ 64 <460000000>;
4777 required-opps = <&rpmhpd_opp_nom>;
4778 };
4779 };
4780 };
4781
4782 mdss_dp: displayport-controller@ae90000 {
4783 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp";
4784 reg = <0 0xae90000 0 0x200>,
4785 <0 0xae90200 0 0x200>,
4786 <0 0xae90400 0 0x600>,
4787 <0 0xae91000 0 0x400>,
4788 <0 0xae91400 0 0x400>;
4789 interrupt-parent = <&mdss>;
4790 interrupts = <12>;
4791 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4792 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4793 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4794 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4795 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4796 clock-names = "core_iface",
4797 "core_aux",
4798 "ctrl_link",
4799 "ctrl_link_iface",
4800 "stream_pixel";
4801
4802 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4803 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4804 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4805 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4806
4807 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4808 phy-names = "dp";
4809
4810 #sound-dai-cells = <0>;
4811
4812 operating-points-v2 = <&dp_opp_table>;
4813 power-domains = <&rpmhpd SM8250_MMCX>;
4814
4815 status = "disabled";
4816
4817 ports {
4818 #address-cells = <1>;
4819 #size-cells = <0>;
4820
4821 port@0 {
4822 reg = <0>;
4823 mdss_dp_in: endpoint {
4824 remote-endpoint = <&dpu_intf0_out>;
4825 };
4826 };
4827
4828 port@1 {
4829 reg = <1>;
4830
4831 mdss_dp_out: endpoint {
4832 };
4833 };
4834 };
4835
4836 dp_opp_table: opp-table {
4837 compatible = "operating-points-v2";
4838
4839 opp-160000000 {
4840 opp-hz = /bits/ 64 <160000000>;
4841 required-opps = <&rpmhpd_opp_low_svs>;
4842 };
4843
4844 opp-270000000 {
4845 opp-hz = /bits/ 64 <270000000>;
4846 required-opps = <&rpmhpd_opp_svs>;
4847 };
4848
4849 opp-540000000 {
4850 opp-hz = /bits/ 64 <540000000>;
4851 required-opps = <&rpmhpd_opp_svs_l1>;
4852 };
4853
4854 opp-810000000 {
4855 opp-hz = /bits/ 64 <810000000>;
4856 required-opps = <&rpmhpd_opp_nom>;
4857 };
4858 };
4859 };
4860
4861 mdss_dsi0: dsi@ae94000 {
4862 compatible = "qcom,sm8250-dsi-ctrl",
4863 "qcom,mdss-dsi-ctrl";
4864 reg = <0 0x0ae94000 0 0x400>;
4865 reg-names = "dsi_ctrl";
4866
4867 interrupt-parent = <&mdss>;
4868 interrupts = <4>;
4869
4870 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4871 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4872 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4873 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4874 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4875 <&gcc GCC_DISP_HF_AXI_CLK>;
4876 clock-names = "byte",
4877 "byte_intf",
4878 "pixel",
4879 "core",
4880 "iface",
4881 "bus";
4882
4883 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4884 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4885
4886 operating-points-v2 = <&dsi_opp_table>;
4887 power-domains = <&rpmhpd RPMHPD_MMCX>;
4888
4889 phys = <&mdss_dsi0_phy>;
4890
4891 status = "disabled";
4892
4893 #address-cells = <1>;
4894 #size-cells = <0>;
4895
4896 ports {
4897 #address-cells = <1>;
4898 #size-cells = <0>;
4899
4900 port@0 {
4901 reg = <0>;
4902 mdss_dsi0_in: endpoint {
4903 remote-endpoint = <&dpu_intf1_out>;
4904 };
4905 };
4906
4907 port@1 {
4908 reg = <1>;
4909 mdss_dsi0_out: endpoint {
4910 };
4911 };
4912 };
4913
4914 dsi_opp_table: opp-table {
4915 compatible = "operating-points-v2";
4916
4917 opp-187500000 {
4918 opp-hz = /bits/ 64 <187500000>;
4919 required-opps = <&rpmhpd_opp_low_svs>;
4920 };
4921
4922 opp-300000000 {
4923 opp-hz = /bits/ 64 <300000000>;
4924 required-opps = <&rpmhpd_opp_svs>;
4925 };
4926
4927 opp-358000000 {
4928 opp-hz = /bits/ 64 <358000000>;
4929 required-opps = <&rpmhpd_opp_svs_l1>;
4930 };
4931 };
4932 };
4933
4934 mdss_dsi0_phy: phy@ae94400 {
4935 compatible = "qcom,dsi-phy-7nm";
4936 reg = <0 0x0ae94400 0 0x200>,
4937 <0 0x0ae94600 0 0x280>,
4938 <0 0x0ae94900 0 0x260>;
4939 reg-names = "dsi_phy",
4940 "dsi_phy_lane",
4941 "dsi_pll";
4942
4943 #clock-cells = <1>;
4944 #phy-cells = <0>;
4945
4946 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4947 <&rpmhcc RPMH_CXO_CLK>;
4948 clock-names = "iface", "ref";
4949
4950 status = "disabled";
4951 };
4952
4953 mdss_dsi1: dsi@ae96000 {
4954 compatible = "qcom,sm8250-dsi-ctrl",
4955 "qcom,mdss-dsi-ctrl";
4956 reg = <0 0x0ae96000 0 0x400>;
4957 reg-names = "dsi_ctrl";
4958
4959 interrupt-parent = <&mdss>;
4960 interrupts = <5>;
4961
4962 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4963 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4964 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4965 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4966 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4967 <&gcc GCC_DISP_HF_AXI_CLK>;
4968 clock-names = "byte",
4969 "byte_intf",
4970 "pixel",
4971 "core",
4972 "iface",
4973 "bus";
4974
4975 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4976 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4977
4978 operating-points-v2 = <&dsi_opp_table>;
4979 power-domains = <&rpmhpd RPMHPD_MMCX>;
4980
4981 phys = <&mdss_dsi1_phy>;
4982
4983 status = "disabled";
4984
4985 #address-cells = <1>;
4986 #size-cells = <0>;
4987
4988 ports {
4989 #address-cells = <1>;
4990 #size-cells = <0>;
4991
4992 port@0 {
4993 reg = <0>;
4994 mdss_dsi1_in: endpoint {
4995 remote-endpoint = <&dpu_intf2_out>;
4996 };
4997 };
4998
4999 port@1 {
5000 reg = <1>;
5001 mdss_dsi1_out: endpoint {
5002 };
5003 };
5004 };
5005 };
5006
5007 mdss_dsi1_phy: phy@ae96400 {
5008 compatible = "qcom,dsi-phy-7nm";
5009 reg = <0 0x0ae96400 0 0x200>,
5010 <0 0x0ae96600 0 0x280>,
5011 <0 0x0ae96900 0 0x260>;
5012 reg-names = "dsi_phy",
5013 "dsi_phy_lane",
5014 "dsi_pll";
5015
5016 #clock-cells = <1>;
5017 #phy-cells = <0>;
5018
5019 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
5020 <&rpmhcc RPMH_CXO_CLK>;
5021 clock-names = "iface", "ref";
5022
5023 status = "disabled";
5024 };
5025 };
5026
5027 dispcc: clock-controller@af00000 {
5028 compatible = "qcom,sm8250-dispcc";
5029 reg = <0 0x0af00000 0 0x10000>;
5030 power-domains = <&rpmhpd RPMHPD_MMCX>;
5031 required-opps = <&rpmhpd_opp_low_svs>;
5032 clocks = <&rpmhcc RPMH_CXO_CLK>,
5033 <&mdss_dsi0_phy 0>,
5034 <&mdss_dsi0_phy 1>,
5035 <&mdss_dsi1_phy 0>,
5036 <&mdss_dsi1_phy 1>,
5037 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5038 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
5039 clock-names = "bi_tcxo",
5040 "dsi0_phy_pll_out_byteclk",
5041 "dsi0_phy_pll_out_dsiclk",
5042 "dsi1_phy_pll_out_byteclk",
5043 "dsi1_phy_pll_out_dsiclk",
5044 "dp_phy_pll_link_clk",
5045 "dp_phy_pll_vco_div_clk";
5046 #clock-cells = <1>;
5047 #reset-cells = <1>;
5048 #power-domain-cells = <1>;
5049 };
5050
5051 pdc: interrupt-controller@b220000 {
5052 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5053 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5054 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5055 <125 63 1>, <126 716 12>;
5056 #interrupt-cells = <2>;
5057 interrupt-parent = <&intc>;
5058 interrupt-controller;
5059 };
5060
5061 tsens0: thermal-sensor@c263000 {
5062 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5063 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5064 <0 0x0c222000 0 0x1ff>; /* SROT */
5065 #qcom,sensors = <16>;
5066 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5067 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5068 interrupt-names = "uplow", "critical";
5069 #thermal-sensor-cells = <1>;
5070 };
5071
5072 tsens1: thermal-sensor@c265000 {
5073 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5074 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5075 <0 0x0c223000 0 0x1ff>; /* SROT */
5076 #qcom,sensors = <9>;
5077 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5078 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5079 interrupt-names = "uplow", "critical";
5080 #thermal-sensor-cells = <1>;
5081 };
5082
5083 aoss_qmp: power-management@c300000 {
5084 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5085 reg = <0 0x0c300000 0 0x400>;
5086 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5087 IPCC_MPROC_SIGNAL_GLINK_QMP
5088 IRQ_TYPE_EDGE_RISING>;
5089 mboxes = <&ipcc IPCC_CLIENT_AOP
5090 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5091
5092 #clock-cells = <0>;
5093 };
5094
5095 sram@c3f0000 {
5096 compatible = "qcom,rpmh-stats";
5097 reg = <0 0x0c3f0000 0 0x400>;
5098 };
5099
5100 spmi_bus: spmi@c440000 {
5101 compatible = "qcom,spmi-pmic-arb";
5102 reg = <0x0 0x0c440000 0x0 0x0001100>,
5103 <0x0 0x0c600000 0x0 0x2000000>,
5104 <0x0 0x0e600000 0x0 0x0100000>,
5105 <0x0 0x0e700000 0x0 0x00a0000>,
5106 <0x0 0x0c40a000 0x0 0x0026000>;
5107 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5108 interrupt-names = "periph_irq";
5109 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5110 qcom,ee = <0>;
5111 qcom,channel = <0>;
5112 #address-cells = <2>;
5113 #size-cells = <0>;
5114 interrupt-controller;
5115 #interrupt-cells = <4>;
5116 };
5117
5118 tlmm: pinctrl@f100000 {
5119 compatible = "qcom,sm8250-pinctrl";
5120 reg = <0 0x0f100000 0 0x300000>,
5121 <0 0x0f500000 0 0x300000>,
5122 <0 0x0f900000 0 0x300000>;
5123 reg-names = "west", "south", "north";
5124 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5125 gpio-controller;
5126 #gpio-cells = <2>;
5127 interrupt-controller;
5128 #interrupt-cells = <2>;
5129 gpio-ranges = <&tlmm 0 0 181>;
5130 wakeup-parent = <&pdc>;
5131
5132 cam2_default: cam2-default-state {
5133 rst-pins {
5134 pins = "gpio78";
5135 function = "gpio";
5136 drive-strength = <2>;
5137 bias-disable;
5138 };
5139
5140 mclk-pins {
5141 pins = "gpio96";
5142 function = "cam_mclk";
5143 drive-strength = <16>;
5144 bias-disable;
5145 };
5146 };
5147
5148 cam2_suspend: cam2-suspend-state {
5149 rst-pins {
5150 pins = "gpio78";
5151 function = "gpio";
5152 drive-strength = <2>;
5153 bias-pull-down;
5154 output-low;
5155 };
5156
5157 mclk-pins {
5158 pins = "gpio96";
5159 function = "cam_mclk";
5160 drive-strength = <2>;
5161 bias-disable;
5162 };
5163 };
5164
5165 cci0_default: cci0-default-state {
5166 cci0_i2c0_default: cci0-i2c0-default-pins {
5167 /* SDA, SCL */
5168 pins = "gpio101", "gpio102";
5169 function = "cci_i2c";
5170
5171 bias-pull-up;
5172 drive-strength = <2>; /* 2 mA */
5173 };
5174
5175 cci0_i2c1_default: cci0-i2c1-default-pins {
5176 /* SDA, SCL */
5177 pins = "gpio103", "gpio104";
5178 function = "cci_i2c";
5179
5180 bias-pull-up;
5181 drive-strength = <2>; /* 2 mA */
5182 };
5183 };
5184
5185 cci0_sleep: cci0-sleep-state {
5186 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5187 /* SDA, SCL */
5188 pins = "gpio101", "gpio102";
5189 function = "cci_i2c";
5190
5191 drive-strength = <2>; /* 2 mA */
5192 bias-pull-down;
5193 };
5194
5195 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5196 /* SDA, SCL */
5197 pins = "gpio103", "gpio104";
5198 function = "cci_i2c";
5199
5200 drive-strength = <2>; /* 2 mA */
5201 bias-pull-down;
5202 };
5203 };
5204
5205 cci1_default: cci1-default-state {
5206 cci1_i2c0_default: cci1-i2c0-default-pins {
5207 /* SDA, SCL */
5208 pins = "gpio105","gpio106";
5209 function = "cci_i2c";
5210
5211 bias-pull-up;
5212 drive-strength = <2>; /* 2 mA */
5213 };
5214
5215 cci1_i2c1_default: cci1-i2c1-default-pins {
5216 /* SDA, SCL */
5217 pins = "gpio107","gpio108";
5218 function = "cci_i2c";
5219
5220 bias-pull-up;
5221 drive-strength = <2>; /* 2 mA */
5222 };
5223 };
5224
5225 cci1_sleep: cci1-sleep-state {
5226 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5227 /* SDA, SCL */
5228 pins = "gpio105","gpio106";
5229 function = "cci_i2c";
5230
5231 bias-pull-down;
5232 drive-strength = <2>; /* 2 mA */
5233 };
5234
5235 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5236 /* SDA, SCL */
5237 pins = "gpio107","gpio108";
5238 function = "cci_i2c";
5239
5240 bias-pull-down;
5241 drive-strength = <2>; /* 2 mA */
5242 };
5243 };
5244
5245 pri_mi2s_active: pri-mi2s-active-state {
5246 sclk-pins {
5247 pins = "gpio138";
5248 function = "mi2s0_sck";
5249 drive-strength = <8>;
5250 bias-disable;
5251 };
5252
5253 ws-pins {
5254 pins = "gpio141";
5255 function = "mi2s0_ws";
5256 drive-strength = <8>;
5257 output-high;
5258 };
5259
5260 data0-pins {
5261 pins = "gpio139";
5262 function = "mi2s0_data0";
5263 drive-strength = <8>;
5264 bias-disable;
5265 output-high;
5266 };
5267
5268 data1-pins {
5269 pins = "gpio140";
5270 function = "mi2s0_data1";
5271 drive-strength = <8>;
5272 output-high;
5273 };
5274 };
5275
5276 qup_i2c0_default: qup-i2c0-default-state {
5277 pins = "gpio28", "gpio29";
5278 function = "qup0";
5279 drive-strength = <2>;
5280 bias-disable;
5281 };
5282
5283 qup_i2c1_default: qup-i2c1-default-state {
5284 pins = "gpio4", "gpio5";
5285 function = "qup1";
5286 drive-strength = <2>;
5287 bias-disable;
5288 };
5289
5290 qup_i2c2_default: qup-i2c2-default-state {
5291 pins = "gpio115", "gpio116";
5292 function = "qup2";
5293 drive-strength = <2>;
5294 bias-disable;
5295 };
5296
5297 qup_i2c3_default: qup-i2c3-default-state {
5298 pins = "gpio119", "gpio120";
5299 function = "qup3";
5300 drive-strength = <2>;
5301 bias-disable;
5302 };
5303
5304 qup_i2c4_default: qup-i2c4-default-state {
5305 pins = "gpio8", "gpio9";
5306 function = "qup4";
5307 drive-strength = <2>;
5308 bias-disable;
5309 };
5310
5311 qup_i2c5_default: qup-i2c5-default-state {
5312 pins = "gpio12", "gpio13";
5313 function = "qup5";
5314 drive-strength = <2>;
5315 bias-disable;
5316 };
5317
5318 qup_i2c6_default: qup-i2c6-default-state {
5319 pins = "gpio16", "gpio17";
5320 function = "qup6";
5321 drive-strength = <2>;
5322 bias-disable;
5323 };
5324
5325 qup_i2c7_default: qup-i2c7-default-state {
5326 pins = "gpio20", "gpio21";
5327 function = "qup7";
5328 drive-strength = <2>;
5329 bias-disable;
5330 };
5331
5332 qup_i2c8_default: qup-i2c8-default-state {
5333 pins = "gpio24", "gpio25";
5334 function = "qup8";
5335 drive-strength = <2>;
5336 bias-disable;
5337 };
5338
5339 qup_i2c9_default: qup-i2c9-default-state {
5340 pins = "gpio125", "gpio126";
5341 function = "qup9";
5342 drive-strength = <2>;
5343 bias-disable;
5344 };
5345
5346 qup_i2c10_default: qup-i2c10-default-state {
5347 pins = "gpio129", "gpio130";
5348 function = "qup10";
5349 drive-strength = <2>;
5350 bias-disable;
5351 };
5352
5353 qup_i2c11_default: qup-i2c11-default-state {
5354 pins = "gpio60", "gpio61";
5355 function = "qup11";
5356 drive-strength = <2>;
5357 bias-disable;
5358 };
5359
5360 qup_i2c12_default: qup-i2c12-default-state {
5361 pins = "gpio32", "gpio33";
5362 function = "qup12";
5363 drive-strength = <2>;
5364 bias-disable;
5365 };
5366
5367 qup_i2c13_default: qup-i2c13-default-state {
5368 pins = "gpio36", "gpio37";
5369 function = "qup13";
5370 drive-strength = <2>;
5371 bias-disable;
5372 };
5373
5374 qup_i2c14_default: qup-i2c14-default-state {
5375 pins = "gpio40", "gpio41";
5376 function = "qup14";
5377 drive-strength = <2>;
5378 bias-disable;
5379 };
5380
5381 qup_i2c15_default: qup-i2c15-default-state {
5382 pins = "gpio44", "gpio45";
5383 function = "qup15";
5384 drive-strength = <2>;
5385 bias-disable;
5386 };
5387
5388 qup_i2c16_default: qup-i2c16-default-state {
5389 pins = "gpio48", "gpio49";
5390 function = "qup16";
5391 drive-strength = <2>;
5392 bias-disable;
5393 };
5394
5395 qup_i2c17_default: qup-i2c17-default-state {
5396 pins = "gpio52", "gpio53";
5397 function = "qup17";
5398 drive-strength = <2>;
5399 bias-disable;
5400 };
5401
5402 qup_i2c18_default: qup-i2c18-default-state {
5403 pins = "gpio56", "gpio57";
5404 function = "qup18";
5405 drive-strength = <2>;
5406 bias-disable;
5407 };
5408
5409 qup_i2c19_default: qup-i2c19-default-state {
5410 pins = "gpio0", "gpio1";
5411 function = "qup19";
5412 drive-strength = <2>;
5413 bias-disable;
5414 };
5415
5416 qup_spi0_cs: qup-spi0-cs-state {
5417 pins = "gpio31";
5418 function = "qup0";
5419 };
5420
5421 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5422 pins = "gpio31";
5423 function = "gpio";
5424 };
5425
5426 qup_spi0_data_clk: qup-spi0-data-clk-state {
5427 pins = "gpio28", "gpio29",
5428 "gpio30";
5429 function = "qup0";
5430 };
5431
5432 qup_spi1_cs: qup-spi1-cs-state {
5433 pins = "gpio7";
5434 function = "qup1";
5435 };
5436
5437 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5438 pins = "gpio7";
5439 function = "gpio";
5440 };
5441
5442 qup_spi1_data_clk: qup-spi1-data-clk-state {
5443 pins = "gpio4", "gpio5",
5444 "gpio6";
5445 function = "qup1";
5446 };
5447
5448 qup_spi2_cs: qup-spi2-cs-state {
5449 pins = "gpio118";
5450 function = "qup2";
5451 };
5452
5453 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5454 pins = "gpio118";
5455 function = "gpio";
5456 };
5457
5458 qup_spi2_data_clk: qup-spi2-data-clk-state {
5459 pins = "gpio115", "gpio116",
5460 "gpio117";
5461 function = "qup2";
5462 };
5463
5464 qup_spi3_cs: qup-spi3-cs-state {
5465 pins = "gpio122";
5466 function = "qup3";
5467 };
5468
5469 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5470 pins = "gpio122";
5471 function = "gpio";
5472 };
5473
5474 qup_spi3_data_clk: qup-spi3-data-clk-state {
5475 pins = "gpio119", "gpio120",
5476 "gpio121";
5477 function = "qup3";
5478 };
5479
5480 qup_spi4_cs: qup-spi4-cs-state {
5481 pins = "gpio11";
5482 function = "qup4";
5483 };
5484
5485 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5486 pins = "gpio11";
5487 function = "gpio";
5488 };
5489
5490 qup_spi4_data_clk: qup-spi4-data-clk-state {
5491 pins = "gpio8", "gpio9",
5492 "gpio10";
5493 function = "qup4";
5494 };
5495
5496 qup_spi5_cs: qup-spi5-cs-state {
5497 pins = "gpio15";
5498 function = "qup5";
5499 };
5500
5501 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5502 pins = "gpio15";
5503 function = "gpio";
5504 };
5505
5506 qup_spi5_data_clk: qup-spi5-data-clk-state {
5507 pins = "gpio12", "gpio13",
5508 "gpio14";
5509 function = "qup5";
5510 };
5511
5512 qup_spi6_cs: qup-spi6-cs-state {
5513 pins = "gpio19";
5514 function = "qup6";
5515 };
5516
5517 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5518 pins = "gpio19";
5519 function = "gpio";
5520 };
5521
5522 qup_spi6_data_clk: qup-spi6-data-clk-state {
5523 pins = "gpio16", "gpio17",
5524 "gpio18";
5525 function = "qup6";
5526 };
5527
5528 qup_spi7_cs: qup-spi7-cs-state {
5529 pins = "gpio23";
5530 function = "qup7";
5531 };
5532
5533 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5534 pins = "gpio23";
5535 function = "gpio";
5536 };
5537
5538 qup_spi7_data_clk: qup-spi7-data-clk-state {
5539 pins = "gpio20", "gpio21",
5540 "gpio22";
5541 function = "qup7";
5542 };
5543
5544 qup_spi8_cs: qup-spi8-cs-state {
5545 pins = "gpio27";
5546 function = "qup8";
5547 };
5548
5549 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5550 pins = "gpio27";
5551 function = "gpio";
5552 };
5553
5554 qup_spi8_data_clk: qup-spi8-data-clk-state {
5555 pins = "gpio24", "gpio25",
5556 "gpio26";
5557 function = "qup8";
5558 };
5559
5560 qup_spi9_cs: qup-spi9-cs-state {
5561 pins = "gpio128";
5562 function = "qup9";
5563 };
5564
5565 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5566 pins = "gpio128";
5567 function = "gpio";
5568 };
5569
5570 qup_spi9_data_clk: qup-spi9-data-clk-state {
5571 pins = "gpio125", "gpio126",
5572 "gpio127";
5573 function = "qup9";
5574 };
5575
5576 qup_spi10_cs: qup-spi10-cs-state {
5577 pins = "gpio132";
5578 function = "qup10";
5579 };
5580
5581 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5582 pins = "gpio132";
5583 function = "gpio";
5584 };
5585
5586 qup_spi10_data_clk: qup-spi10-data-clk-state {
5587 pins = "gpio129", "gpio130",
5588 "gpio131";
5589 function = "qup10";
5590 };
5591
5592 qup_spi11_cs: qup-spi11-cs-state {
5593 pins = "gpio63";
5594 function = "qup11";
5595 };
5596
5597 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5598 pins = "gpio63";
5599 function = "gpio";
5600 };
5601
5602 qup_spi11_data_clk: qup-spi11-data-clk-state {
5603 pins = "gpio60", "gpio61",
5604 "gpio62";
5605 function = "qup11";
5606 };
5607
5608 qup_spi12_cs: qup-spi12-cs-state {
5609 pins = "gpio35";
5610 function = "qup12";
5611 };
5612
5613 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5614 pins = "gpio35";
5615 function = "gpio";
5616 };
5617
5618 qup_spi12_data_clk: qup-spi12-data-clk-state {
5619 pins = "gpio32", "gpio33",
5620 "gpio34";
5621 function = "qup12";
5622 };
5623
5624 qup_spi13_cs: qup-spi13-cs-state {
5625 pins = "gpio39";
5626 function = "qup13";
5627 };
5628
5629 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5630 pins = "gpio39";
5631 function = "gpio";
5632 };
5633
5634 qup_spi13_data_clk: qup-spi13-data-clk-state {
5635 pins = "gpio36", "gpio37",
5636 "gpio38";
5637 function = "qup13";
5638 };
5639
5640 qup_spi14_cs: qup-spi14-cs-state {
5641 pins = "gpio43";
5642 function = "qup14";
5643 };
5644
5645 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5646 pins = "gpio43";
5647 function = "gpio";
5648 };
5649
5650 qup_spi14_data_clk: qup-spi14-data-clk-state {
5651 pins = "gpio40", "gpio41",
5652 "gpio42";
5653 function = "qup14";
5654 };
5655
5656 qup_spi15_cs: qup-spi15-cs-state {
5657 pins = "gpio47";
5658 function = "qup15";
5659 };
5660
5661 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5662 pins = "gpio47";
5663 function = "gpio";
5664 };
5665
5666 qup_spi15_data_clk: qup-spi15-data-clk-state {
5667 pins = "gpio44", "gpio45",
5668 "gpio46";
5669 function = "qup15";
5670 };
5671
5672 qup_spi16_cs: qup-spi16-cs-state {
5673 pins = "gpio51";
5674 function = "qup16";
5675 };
5676
5677 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5678 pins = "gpio51";
5679 function = "gpio";
5680 };
5681
5682 qup_spi16_data_clk: qup-spi16-data-clk-state {
5683 pins = "gpio48", "gpio49",
5684 "gpio50";
5685 function = "qup16";
5686 };
5687
5688 qup_spi17_cs: qup-spi17-cs-state {
5689 pins = "gpio55";
5690 function = "qup17";
5691 };
5692
5693 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5694 pins = "gpio55";
5695 function = "gpio";
5696 };
5697
5698 qup_spi17_data_clk: qup-spi17-data-clk-state {
5699 pins = "gpio52", "gpio53",
5700 "gpio54";
5701 function = "qup17";
5702 };
5703
5704 qup_spi18_cs: qup-spi18-cs-state {
5705 pins = "gpio59";
5706 function = "qup18";
5707 };
5708
5709 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5710 pins = "gpio59";
5711 function = "gpio";
5712 };
5713
5714 qup_spi18_data_clk: qup-spi18-data-clk-state {
5715 pins = "gpio56", "gpio57",
5716 "gpio58";
5717 function = "qup18";
5718 };
5719
5720 qup_spi19_cs: qup-spi19-cs-state {
5721 pins = "gpio3";
5722 function = "qup19";
5723 };
5724
5725 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5726 pins = "gpio3";
5727 function = "gpio";
5728 };
5729
5730 qup_spi19_data_clk: qup-spi19-data-clk-state {
5731 pins = "gpio0", "gpio1",
5732 "gpio2";
5733 function = "qup19";
5734 };
5735
5736 qup_uart2_default: qup-uart2-default-state {
5737 pins = "gpio117", "gpio118";
5738 function = "qup2";
5739 };
5740
5741 qup_uart6_default: qup-uart6-default-state {
5742 pins = "gpio16", "gpio17", "gpio18", "gpio19";
5743 function = "qup6";
5744 };
5745
5746 qup_uart12_default: qup-uart12-default-state {
5747 pins = "gpio34", "gpio35";
5748 function = "qup12";
5749 };
5750
5751 qup_uart17_default: qup-uart17-default-state {
5752 pins = "gpio52", "gpio53", "gpio54", "gpio55";
5753 function = "qup17";
5754 };
5755
5756 qup_uart18_default: qup-uart18-default-state {
5757 pins = "gpio58", "gpio59";
5758 function = "qup18";
5759 };
5760
5761 tert_mi2s_active: tert-mi2s-active-state {
5762 sck-pins {
5763 pins = "gpio133";
5764 function = "mi2s2_sck";
5765 drive-strength = <8>;
5766 bias-disable;
5767 };
5768
5769 data0-pins {
5770 pins = "gpio134";
5771 function = "mi2s2_data0";
5772 drive-strength = <8>;
5773 bias-disable;
5774 output-high;
5775 };
5776
5777 ws-pins {
5778 pins = "gpio135";
5779 function = "mi2s2_ws";
5780 drive-strength = <8>;
5781 output-high;
5782 };
5783 };
5784
5785 sdc2_sleep_state: sdc2-sleep-state {
5786 clk-pins {
5787 pins = "sdc2_clk";
5788 drive-strength = <2>;
5789 bias-disable;
5790 };
5791
5792 cmd-pins {
5793 pins = "sdc2_cmd";
5794 drive-strength = <2>;
5795 bias-pull-up;
5796 };
5797
5798 data-pins {
5799 pins = "sdc2_data";
5800 drive-strength = <2>;
5801 bias-pull-up;
5802 };
5803 };
5804
5805 pcie0_default_state: pcie0-default-state {
5806 perst-pins {
5807 pins = "gpio79";
5808 function = "gpio";
5809 drive-strength = <2>;
5810 bias-pull-down;
5811 };
5812
5813 clkreq-pins {
5814 pins = "gpio80";
5815 function = "pci_e0";
5816 drive-strength = <2>;
5817 bias-pull-up;
5818 };
5819
5820 wake-pins {
5821 pins = "gpio81";
5822 function = "gpio";
5823 drive-strength = <2>;
5824 bias-pull-up;
5825 };
5826 };
5827
5828 pcie1_default_state: pcie1-default-state {
5829 perst-pins {
5830 pins = "gpio82";
5831 function = "gpio";
5832 drive-strength = <2>;
5833 bias-pull-down;
5834 };
5835
5836 clkreq-pins {
5837 pins = "gpio83";
5838 function = "pci_e1";
5839 drive-strength = <2>;
5840 bias-pull-up;
5841 };
5842
5843 wake-pins {
5844 pins = "gpio84";
5845 function = "gpio";
5846 drive-strength = <2>;
5847 bias-pull-up;
5848 };
5849 };
5850
5851 pcie2_default_state: pcie2-default-state {
5852 perst-pins {
5853 pins = "gpio85";
5854 function = "gpio";
5855 drive-strength = <2>;
5856 bias-pull-down;
5857 };
5858
5859 clkreq-pins {
5860 pins = "gpio86";
5861 function = "pci_e2";
5862 drive-strength = <2>;
5863 bias-pull-up;
5864 };
5865
5866 wake-pins {
5867 pins = "gpio87";
5868 function = "gpio";
5869 drive-strength = <2>;
5870 bias-pull-up;
5871 };
5872 };
5873 };
5874
5875 apps_smmu: iommu@15000000 {
5876 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5877 reg = <0 0x15000000 0 0x100000>;
5878 #iommu-cells = <2>;
5879 #global-interrupts = <2>;
5880 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5955 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5956 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5957 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5958 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5959 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5960 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5961 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5962 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5963 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5964 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5965 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5966 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5967 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5968 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5969 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5970 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5971 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5972 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5973 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5974 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5975 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5976 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5977 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5978 dma-coherent;
5979 };
5980
5981 adsp: remoteproc@17300000 {
5982 compatible = "qcom,sm8250-adsp-pas";
5983 reg = <0 0x17300000 0 0x100>;
5984
5985 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
5986 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5987 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5988 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5989 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5990 interrupt-names = "wdog", "fatal", "ready",
5991 "handover", "stop-ack";
5992
5993 clocks = <&rpmhcc RPMH_CXO_CLK>;
5994 clock-names = "xo";
5995
5996 power-domains = <&rpmhpd RPMHPD_LCX>,
5997 <&rpmhpd RPMHPD_LMX>;
5998 power-domain-names = "lcx", "lmx";
5999
6000 memory-region = <&adsp_mem>;
6001
6002 qcom,qmp = <&aoss_qmp>;
6003
6004 qcom,smem-states = <&smp2p_adsp_out 0>;
6005 qcom,smem-state-names = "stop";
6006
6007 status = "disabled";
6008
6009 glink-edge {
6010 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
6011 IPCC_MPROC_SIGNAL_GLINK_QMP
6012 IRQ_TYPE_EDGE_RISING>;
6013 mboxes = <&ipcc IPCC_CLIENT_LPASS
6014 IPCC_MPROC_SIGNAL_GLINK_QMP>;
6015
6016 label = "lpass";
6017 qcom,remote-pid = <2>;
6018
6019 apr {
6020 compatible = "qcom,apr-v2";
6021 qcom,glink-channels = "apr_audio_svc";
6022 qcom,domain = <APR_DOMAIN_ADSP>;
6023 #address-cells = <1>;
6024 #size-cells = <0>;
6025
6026 service@3 {
6027 reg = <APR_SVC_ADSP_CORE>;
6028 compatible = "qcom,q6core";
6029 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 };
6031
6032 q6afe: service@4 {
6033 compatible = "qcom,q6afe";
6034 reg = <APR_SVC_AFE>;
6035 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6036 q6afedai: dais {
6037 compatible = "qcom,q6afe-dais";
6038 #address-cells = <1>;
6039 #size-cells = <0>;
6040 #sound-dai-cells = <1>;
6041 };
6042
6043 q6afecc: clock-controller {
6044 compatible = "qcom,q6afe-clocks";
6045 #clock-cells = <2>;
6046 };
6047 };
6048
6049 q6asm: service@7 {
6050 compatible = "qcom,q6asm";
6051 reg = <APR_SVC_ASM>;
6052 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6053 q6asmdai: dais {
6054 compatible = "qcom,q6asm-dais";
6055 #address-cells = <1>;
6056 #size-cells = <0>;
6057 #sound-dai-cells = <1>;
6058 iommus = <&apps_smmu 0x1801 0x0>;
6059 };
6060 };
6061
6062 q6adm: service@8 {
6063 compatible = "qcom,q6adm";
6064 reg = <APR_SVC_ADM>;
6065 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6066 q6routing: routing {
6067 compatible = "qcom,q6adm-routing";
6068 #sound-dai-cells = <0>;
6069 };
6070 };
6071 };
6072
6073 fastrpc {
6074 compatible = "qcom,fastrpc";
6075 qcom,glink-channels = "fastrpcglink-apps-dsp";
6076 label = "adsp";
6077 qcom,non-secure-domain;
6078 #address-cells = <1>;
6079 #size-cells = <0>;
6080
6081 compute-cb@3 {
6082 compatible = "qcom,fastrpc-compute-cb";
6083 reg = <3>;
6084 iommus = <&apps_smmu 0x1803 0x0>;
6085 };
6086
6087 compute-cb@4 {
6088 compatible = "qcom,fastrpc-compute-cb";
6089 reg = <4>;
6090 iommus = <&apps_smmu 0x1804 0x0>;
6091 };
6092
6093 compute-cb@5 {
6094 compatible = "qcom,fastrpc-compute-cb";
6095 reg = <5>;
6096 iommus = <&apps_smmu 0x1805 0x0>;
6097 };
6098 };
6099 };
6100 };
6101
6102 intc: interrupt-controller@17a00000 {
6103 compatible = "arm,gic-v3";
6104 #interrupt-cells = <3>;
6105 interrupt-controller;
6106 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6107 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6108 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6109 };
6110
6111 watchdog@17c10000 {
6112 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6113 reg = <0 0x17c10000 0 0x1000>;
6114 clocks = <&sleep_clk>;
6115 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
6116 };
6117
6118 timer@17c20000 {
6119 #address-cells = <1>;
6120 #size-cells = <1>;
6121 ranges = <0 0 0 0x20000000>;
6122 compatible = "arm,armv7-timer-mem";
6123 reg = <0x0 0x17c20000 0x0 0x1000>;
6124 clock-frequency = <19200000>;
6125
6126 frame@17c21000 {
6127 frame-number = <0>;
6128 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6129 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6130 reg = <0x17c21000 0x1000>,
6131 <0x17c22000 0x1000>;
6132 };
6133
6134 frame@17c23000 {
6135 frame-number = <1>;
6136 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6137 reg = <0x17c23000 0x1000>;
6138 status = "disabled";
6139 };
6140
6141 frame@17c25000 {
6142 frame-number = <2>;
6143 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6144 reg = <0x17c25000 0x1000>;
6145 status = "disabled";
6146 };
6147
6148 frame@17c27000 {
6149 frame-number = <3>;
6150 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6151 reg = <0x17c27000 0x1000>;
6152 status = "disabled";
6153 };
6154
6155 frame@17c29000 {
6156 frame-number = <4>;
6157 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6158 reg = <0x17c29000 0x1000>;
6159 status = "disabled";
6160 };
6161
6162 frame@17c2b000 {
6163 frame-number = <5>;
6164 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6165 reg = <0x17c2b000 0x1000>;
6166 status = "disabled";
6167 };
6168
6169 frame@17c2d000 {
6170 frame-number = <6>;
6171 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6172 reg = <0x17c2d000 0x1000>;
6173 status = "disabled";
6174 };
6175 };
6176
6177 apps_rsc: rsc@18200000 {
6178 label = "apps_rsc";
6179 compatible = "qcom,rpmh-rsc";
6180 reg = <0x0 0x18200000 0x0 0x10000>,
6181 <0x0 0x18210000 0x0 0x10000>,
6182 <0x0 0x18220000 0x0 0x10000>;
6183 reg-names = "drv-0", "drv-1", "drv-2";
6184 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6185 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6186 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6187 qcom,tcs-offset = <0xd00>;
6188 qcom,drv-id = <2>;
6189 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6190 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6191 power-domains = <&CLUSTER_PD>;
6192
6193 rpmhcc: clock-controller {
6194 compatible = "qcom,sm8250-rpmh-clk";
6195 #clock-cells = <1>;
6196 clock-names = "xo";
6197 clocks = <&xo_board>;
6198 };
6199
6200 rpmhpd: power-controller {
6201 compatible = "qcom,sm8250-rpmhpd";
6202 #power-domain-cells = <1>;
6203 operating-points-v2 = <&rpmhpd_opp_table>;
6204
6205 rpmhpd_opp_table: opp-table {
6206 compatible = "operating-points-v2";
6207
6208 rpmhpd_opp_ret: opp1 {
6209 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6210 };
6211
6212 rpmhpd_opp_min_svs: opp2 {
6213 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6214 };
6215
6216 rpmhpd_opp_low_svs: opp3 {
6217 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6218 };
6219
6220 rpmhpd_opp_svs: opp4 {
6221 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6222 };
6223
6224 rpmhpd_opp_svs_l1: opp5 {
6225 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6226 };
6227
6228 rpmhpd_opp_nom: opp6 {
6229 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6230 };
6231
6232 rpmhpd_opp_nom_l1: opp7 {
6233 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6234 };
6235
6236 rpmhpd_opp_nom_l2: opp8 {
6237 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6238 };
6239
6240 rpmhpd_opp_turbo: opp9 {
6241 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6242 };
6243
6244 rpmhpd_opp_turbo_l1: opp10 {
6245 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6246 };
6247 };
6248 };
6249
6250 apps_bcm_voter: bcm-voter {
6251 compatible = "qcom,bcm-voter";
6252 };
6253 };
6254
6255 epss_l3: interconnect@18590000 {
6256 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6257 reg = <0 0x18590000 0 0x1000>;
6258
6259 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6260 clock-names = "xo", "alternate";
6261
6262 #interconnect-cells = <1>;
6263 };
6264
6265 cpufreq_hw: cpufreq@18591000 {
6266 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6267 reg = <0 0x18591000 0 0x1000>,
6268 <0 0x18592000 0 0x1000>,
6269 <0 0x18593000 0 0x1000>;
6270 reg-names = "freq-domain0", "freq-domain1",
6271 "freq-domain2";
6272
6273 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6274 clock-names = "xo", "alternate";
6275 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
6276 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
6277 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
6278 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6279 #freq-domain-cells = <1>;
6280 #clock-cells = <1>;
6281 };
6282 };
6283
6284 sound: sound {
6285 };
6286
6287 timer {
6288 compatible = "arm,armv8-timer";
6289 interrupts = <GIC_PPI 13
6290 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6291 <GIC_PPI 14
6292 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6293 <GIC_PPI 11
6294 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6295 <GIC_PPI 10
6296 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6297 };
6298
6299 thermal-zones {
6300 cpu0-thermal {
6301 polling-delay-passive = <250>;
6302
6303 thermal-sensors = <&tsens0 1>;
6304
6305 trips {
6306 cpu0_alert0: trip-point0 {
6307 temperature = <90000>;
6308 hysteresis = <2000>;
6309 type = "passive";
6310 };
6311
6312 cpu0_alert1: trip-point1 {
6313 temperature = <95000>;
6314 hysteresis = <2000>;
6315 type = "passive";
6316 };
6317
6318 cpu0_crit: cpu-crit {
6319 temperature = <110000>;
6320 hysteresis = <1000>;
6321 type = "critical";
6322 };
6323 };
6324
6325 cooling-maps {
6326 map0 {
6327 trip = <&cpu0_alert0>;
6328 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6329 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6330 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6331 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6332 };
6333 map1 {
6334 trip = <&cpu0_alert1>;
6335 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6336 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6337 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6338 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6339 };
6340 };
6341 };
6342
6343 cpu1-thermal {
6344 polling-delay-passive = <250>;
6345
6346 thermal-sensors = <&tsens0 2>;
6347
6348 trips {
6349 cpu1_alert0: trip-point0 {
6350 temperature = <90000>;
6351 hysteresis = <2000>;
6352 type = "passive";
6353 };
6354
6355 cpu1_alert1: trip-point1 {
6356 temperature = <95000>;
6357 hysteresis = <2000>;
6358 type = "passive";
6359 };
6360
6361 cpu1_crit: cpu-crit {
6362 temperature = <110000>;
6363 hysteresis = <1000>;
6364 type = "critical";
6365 };
6366 };
6367
6368 cooling-maps {
6369 map0 {
6370 trip = <&cpu1_alert0>;
6371 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6372 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6373 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6374 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6375 };
6376 map1 {
6377 trip = <&cpu1_alert1>;
6378 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6379 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6380 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6381 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6382 };
6383 };
6384 };
6385
6386 cpu2-thermal {
6387 polling-delay-passive = <250>;
6388
6389 thermal-sensors = <&tsens0 3>;
6390
6391 trips {
6392 cpu2_alert0: trip-point0 {
6393 temperature = <90000>;
6394 hysteresis = <2000>;
6395 type = "passive";
6396 };
6397
6398 cpu2_alert1: trip-point1 {
6399 temperature = <95000>;
6400 hysteresis = <2000>;
6401 type = "passive";
6402 };
6403
6404 cpu2_crit: cpu-crit {
6405 temperature = <110000>;
6406 hysteresis = <1000>;
6407 type = "critical";
6408 };
6409 };
6410
6411 cooling-maps {
6412 map0 {
6413 trip = <&cpu2_alert0>;
6414 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6415 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6416 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6417 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6418 };
6419 map1 {
6420 trip = <&cpu2_alert1>;
6421 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6422 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6423 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6424 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6425 };
6426 };
6427 };
6428
6429 cpu3-thermal {
6430 polling-delay-passive = <250>;
6431
6432 thermal-sensors = <&tsens0 4>;
6433
6434 trips {
6435 cpu3_alert0: trip-point0 {
6436 temperature = <90000>;
6437 hysteresis = <2000>;
6438 type = "passive";
6439 };
6440
6441 cpu3_alert1: trip-point1 {
6442 temperature = <95000>;
6443 hysteresis = <2000>;
6444 type = "passive";
6445 };
6446
6447 cpu3_crit: cpu-crit {
6448 temperature = <110000>;
6449 hysteresis = <1000>;
6450 type = "critical";
6451 };
6452 };
6453
6454 cooling-maps {
6455 map0 {
6456 trip = <&cpu3_alert0>;
6457 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6458 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6459 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6460 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6461 };
6462 map1 {
6463 trip = <&cpu3_alert1>;
6464 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6465 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6466 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6467 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6468 };
6469 };
6470 };
6471
6472 cpu4-top-thermal {
6473 polling-delay-passive = <250>;
6474
6475 thermal-sensors = <&tsens0 7>;
6476
6477 trips {
6478 cpu4_top_alert0: trip-point0 {
6479 temperature = <90000>;
6480 hysteresis = <2000>;
6481 type = "passive";
6482 };
6483
6484 cpu4_top_alert1: trip-point1 {
6485 temperature = <95000>;
6486 hysteresis = <2000>;
6487 type = "passive";
6488 };
6489
6490 cpu4_top_crit: cpu-crit {
6491 temperature = <110000>;
6492 hysteresis = <1000>;
6493 type = "critical";
6494 };
6495 };
6496
6497 cooling-maps {
6498 map0 {
6499 trip = <&cpu4_top_alert0>;
6500 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6501 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6502 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6503 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6504 };
6505 map1 {
6506 trip = <&cpu4_top_alert1>;
6507 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6508 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6509 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6510 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6511 };
6512 };
6513 };
6514
6515 cpu5-top-thermal {
6516 polling-delay-passive = <250>;
6517
6518 thermal-sensors = <&tsens0 8>;
6519
6520 trips {
6521 cpu5_top_alert0: trip-point0 {
6522 temperature = <90000>;
6523 hysteresis = <2000>;
6524 type = "passive";
6525 };
6526
6527 cpu5_top_alert1: trip-point1 {
6528 temperature = <95000>;
6529 hysteresis = <2000>;
6530 type = "passive";
6531 };
6532
6533 cpu5_top_crit: cpu-crit {
6534 temperature = <110000>;
6535 hysteresis = <1000>;
6536 type = "critical";
6537 };
6538 };
6539
6540 cooling-maps {
6541 map0 {
6542 trip = <&cpu5_top_alert0>;
6543 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6544 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6545 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6546 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6547 };
6548 map1 {
6549 trip = <&cpu5_top_alert1>;
6550 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6551 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6552 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6553 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6554 };
6555 };
6556 };
6557
6558 cpu6-top-thermal {
6559 polling-delay-passive = <250>;
6560
6561 thermal-sensors = <&tsens0 9>;
6562
6563 trips {
6564 cpu6_top_alert0: trip-point0 {
6565 temperature = <90000>;
6566 hysteresis = <2000>;
6567 type = "passive";
6568 };
6569
6570 cpu6_top_alert1: trip-point1 {
6571 temperature = <95000>;
6572 hysteresis = <2000>;
6573 type = "passive";
6574 };
6575
6576 cpu6_top_crit: cpu-crit {
6577 temperature = <110000>;
6578 hysteresis = <1000>;
6579 type = "critical";
6580 };
6581 };
6582
6583 cooling-maps {
6584 map0 {
6585 trip = <&cpu6_top_alert0>;
6586 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6587 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6588 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6589 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6590 };
6591 map1 {
6592 trip = <&cpu6_top_alert1>;
6593 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6594 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6595 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6596 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6597 };
6598 };
6599 };
6600
6601 cpu7-top-thermal {
6602 polling-delay-passive = <250>;
6603
6604 thermal-sensors = <&tsens0 10>;
6605
6606 trips {
6607 cpu7_top_alert0: trip-point0 {
6608 temperature = <90000>;
6609 hysteresis = <2000>;
6610 type = "passive";
6611 };
6612
6613 cpu7_top_alert1: trip-point1 {
6614 temperature = <95000>;
6615 hysteresis = <2000>;
6616 type = "passive";
6617 };
6618
6619 cpu7_top_crit: cpu-crit {
6620 temperature = <110000>;
6621 hysteresis = <1000>;
6622 type = "critical";
6623 };
6624 };
6625
6626 cooling-maps {
6627 map0 {
6628 trip = <&cpu7_top_alert0>;
6629 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6630 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6631 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6632 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6633 };
6634 map1 {
6635 trip = <&cpu7_top_alert1>;
6636 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6637 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6638 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6639 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6640 };
6641 };
6642 };
6643
6644 cpu4-bottom-thermal {
6645 polling-delay-passive = <250>;
6646
6647 thermal-sensors = <&tsens0 11>;
6648
6649 trips {
6650 cpu4_bottom_alert0: trip-point0 {
6651 temperature = <90000>;
6652 hysteresis = <2000>;
6653 type = "passive";
6654 };
6655
6656 cpu4_bottom_alert1: trip-point1 {
6657 temperature = <95000>;
6658 hysteresis = <2000>;
6659 type = "passive";
6660 };
6661
6662 cpu4_bottom_crit: cpu-crit {
6663 temperature = <110000>;
6664 hysteresis = <1000>;
6665 type = "critical";
6666 };
6667 };
6668
6669 cooling-maps {
6670 map0 {
6671 trip = <&cpu4_bottom_alert0>;
6672 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6673 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6674 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6675 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6676 };
6677 map1 {
6678 trip = <&cpu4_bottom_alert1>;
6679 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6680 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6681 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6682 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6683 };
6684 };
6685 };
6686
6687 cpu5-bottom-thermal {
6688 polling-delay-passive = <250>;
6689
6690 thermal-sensors = <&tsens0 12>;
6691
6692 trips {
6693 cpu5_bottom_alert0: trip-point0 {
6694 temperature = <90000>;
6695 hysteresis = <2000>;
6696 type = "passive";
6697 };
6698
6699 cpu5_bottom_alert1: trip-point1 {
6700 temperature = <95000>;
6701 hysteresis = <2000>;
6702 type = "passive";
6703 };
6704
6705 cpu5_bottom_crit: cpu-crit {
6706 temperature = <110000>;
6707 hysteresis = <1000>;
6708 type = "critical";
6709 };
6710 };
6711
6712 cooling-maps {
6713 map0 {
6714 trip = <&cpu5_bottom_alert0>;
6715 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6716 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6717 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6718 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6719 };
6720 map1 {
6721 trip = <&cpu5_bottom_alert1>;
6722 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6723 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6724 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6725 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6726 };
6727 };
6728 };
6729
6730 cpu6-bottom-thermal {
6731 polling-delay-passive = <250>;
6732
6733 thermal-sensors = <&tsens0 13>;
6734
6735 trips {
6736 cpu6_bottom_alert0: trip-point0 {
6737 temperature = <90000>;
6738 hysteresis = <2000>;
6739 type = "passive";
6740 };
6741
6742 cpu6_bottom_alert1: trip-point1 {
6743 temperature = <95000>;
6744 hysteresis = <2000>;
6745 type = "passive";
6746 };
6747
6748 cpu6_bottom_crit: cpu-crit {
6749 temperature = <110000>;
6750 hysteresis = <1000>;
6751 type = "critical";
6752 };
6753 };
6754
6755 cooling-maps {
6756 map0 {
6757 trip = <&cpu6_bottom_alert0>;
6758 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6759 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6760 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6761 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6762 };
6763 map1 {
6764 trip = <&cpu6_bottom_alert1>;
6765 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6766 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6767 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6768 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6769 };
6770 };
6771 };
6772
6773 cpu7-bottom-thermal {
6774 polling-delay-passive = <250>;
6775
6776 thermal-sensors = <&tsens0 14>;
6777
6778 trips {
6779 cpu7_bottom_alert0: trip-point0 {
6780 temperature = <90000>;
6781 hysteresis = <2000>;
6782 type = "passive";
6783 };
6784
6785 cpu7_bottom_alert1: trip-point1 {
6786 temperature = <95000>;
6787 hysteresis = <2000>;
6788 type = "passive";
6789 };
6790
6791 cpu7_bottom_crit: cpu-crit {
6792 temperature = <110000>;
6793 hysteresis = <1000>;
6794 type = "critical";
6795 };
6796 };
6797
6798 cooling-maps {
6799 map0 {
6800 trip = <&cpu7_bottom_alert0>;
6801 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6802 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6803 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6804 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6805 };
6806 map1 {
6807 trip = <&cpu7_bottom_alert1>;
6808 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6809 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6810 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6811 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6812 };
6813 };
6814 };
6815
6816 aoss0-thermal {
6817 polling-delay-passive = <250>;
6818
6819 thermal-sensors = <&tsens0 0>;
6820
6821 trips {
6822 aoss0_alert0: trip-point0 {
6823 temperature = <90000>;
6824 hysteresis = <2000>;
6825 type = "hot";
6826 };
6827 };
6828 };
6829
6830 cluster0-thermal {
6831 polling-delay-passive = <250>;
6832
6833 thermal-sensors = <&tsens0 5>;
6834
6835 trips {
6836 cluster0_alert0: trip-point0 {
6837 temperature = <90000>;
6838 hysteresis = <2000>;
6839 type = "hot";
6840 };
6841 cluster0_crit: cluster0-crit {
6842 temperature = <110000>;
6843 hysteresis = <2000>;
6844 type = "critical";
6845 };
6846 };
6847 };
6848
6849 cluster1-thermal {
6850 polling-delay-passive = <250>;
6851
6852 thermal-sensors = <&tsens0 6>;
6853
6854 trips {
6855 cluster1_alert0: trip-point0 {
6856 temperature = <90000>;
6857 hysteresis = <2000>;
6858 type = "hot";
6859 };
6860 cluster1_crit: cluster1-crit {
6861 temperature = <110000>;
6862 hysteresis = <2000>;
6863 type = "critical";
6864 };
6865 };
6866 };
6867
6868 gpu-top-thermal {
6869 polling-delay-passive = <250>;
6870
6871 thermal-sensors = <&tsens0 15>;
6872
6873 cooling-maps {
6874 map0 {
6875 trip = <&gpu_top_alert0>;
6876 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6877 };
6878 };
6879
6880 trips {
6881 gpu_top_alert0: trip-point0 {
6882 temperature = <85000>;
6883 hysteresis = <1000>;
6884 type = "passive";
6885 };
6886
6887 trip-point1 {
6888 temperature = <90000>;
6889 hysteresis = <1000>;
6890 type = "hot";
6891 };
6892
6893 trip-point2 {
6894 temperature = <110000>;
6895 hysteresis = <1000>;
6896 type = "critical";
6897 };
6898 };
6899 };
6900
6901 aoss1-thermal {
6902 polling-delay-passive = <250>;
6903
6904 thermal-sensors = <&tsens1 0>;
6905
6906 trips {
6907 aoss1_alert0: trip-point0 {
6908 temperature = <90000>;
6909 hysteresis = <2000>;
6910 type = "hot";
6911 };
6912 };
6913 };
6914
6915 wlan-thermal {
6916 polling-delay-passive = <250>;
6917
6918 thermal-sensors = <&tsens1 1>;
6919
6920 trips {
6921 wlan_alert0: trip-point0 {
6922 temperature = <90000>;
6923 hysteresis = <2000>;
6924 type = "hot";
6925 };
6926 };
6927 };
6928
6929 video-thermal {
6930 polling-delay-passive = <250>;
6931
6932 thermal-sensors = <&tsens1 2>;
6933
6934 trips {
6935 video_alert0: trip-point0 {
6936 temperature = <90000>;
6937 hysteresis = <2000>;
6938 type = "hot";
6939 };
6940 };
6941 };
6942
6943 mem-thermal {
6944 polling-delay-passive = <250>;
6945
6946 thermal-sensors = <&tsens1 3>;
6947
6948 trips {
6949 mem_alert0: trip-point0 {
6950 temperature = <90000>;
6951 hysteresis = <2000>;
6952 type = "hot";
6953 };
6954 };
6955 };
6956
6957 q6-hvx-thermal {
6958 polling-delay-passive = <250>;
6959
6960 thermal-sensors = <&tsens1 4>;
6961
6962 trips {
6963 q6_hvx_alert0: trip-point0 {
6964 temperature = <90000>;
6965 hysteresis = <2000>;
6966 type = "hot";
6967 };
6968 };
6969 };
6970
6971 camera-thermal {
6972 polling-delay-passive = <250>;
6973
6974 thermal-sensors = <&tsens1 5>;
6975
6976 trips {
6977 camera_alert0: trip-point0 {
6978 temperature = <90000>;
6979 hysteresis = <2000>;
6980 type = "hot";
6981 };
6982 };
6983 };
6984
6985 compute-thermal {
6986 polling-delay-passive = <250>;
6987
6988 thermal-sensors = <&tsens1 6>;
6989
6990 trips {
6991 compute_alert0: trip-point0 {
6992 temperature = <90000>;
6993 hysteresis = <2000>;
6994 type = "hot";
6995 };
6996 };
6997 };
6998
6999 npu-thermal {
7000 polling-delay-passive = <250>;
7001
7002 thermal-sensors = <&tsens1 7>;
7003
7004 trips {
7005 npu_alert0: trip-point0 {
7006 temperature = <90000>;
7007 hysteresis = <2000>;
7008 type = "hot";
7009 };
7010 };
7011 };
7012
7013 gpu-bottom-thermal {
7014 polling-delay-passive = <250>;
7015
7016 thermal-sensors = <&tsens1 8>;
7017
7018 cooling-maps {
7019 map0 {
7020 trip = <&gpu_bottom_alert0>;
7021 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7022 };
7023 };
7024
7025 trips {
7026 gpu_bottom_alert0: trip-point0 {
7027 temperature = <85000>;
7028 hysteresis = <1000>;
7029 type = "passive";
7030 };
7031
7032 trip-point1 {
7033 temperature = <90000>;
7034 hysteresis = <1000>;
7035 type = "hot";
7036 };
7037
7038 trip-point2 {
7039 temperature = <110000>;
7040 hysteresis = <1000>;
7041 type = "critical";
7042 };
7043 };
7044 };
7045 };
7046 };
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