1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2022, Linaro Limited
4 */
5
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
18 #include <dt-bindings/mailbox/qcom-ipcc.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/power/qcom,rpmhpd.h>
21 #include <dt-bindings/soc/qcom,gpr.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
24 #include <dt-bindings/phy/phy-qcom-qmp.h>
25 #include <dt-bindings/thermal/thermal.h>
26
27 / {
28 interrupt-parent = <&intc>;
29
30 #address-cells = <2>;
31 #size-cells = <2>;
32
33 chosen { };
34
35 clocks {
36 xo_board: xo-board {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 };
40
41 sleep_clk: sleep-clk {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 };
45
46 bi_tcxo_div2: bi-tcxo-div2-clk {
47 #clock-cells = <0>;
48 compatible = "fixed-factor-clock";
49 clocks = <&rpmhcc RPMH_CXO_CLK>;
50 clock-mult = <1>;
51 clock-div = <2>;
52 };
53
54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
55 #clock-cells = <0>;
56 compatible = "fixed-factor-clock";
57 clocks = <&rpmhcc RPMH_CXO_CLK_A>;
58 clock-mult = <1>;
59 clock-div = <2>;
60 };
61 };
62
63 cpus {
64 #address-cells = <2>;
65 #size-cells = <0>;
66
67 CPU0: cpu@0 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a510";
70 reg = <0 0>;
71 clocks = <&cpufreq_hw 0>;
72 enable-method = "psci";
73 next-level-cache = <&L2_0>;
74 power-domains = <&CPU_PD0>;
75 power-domain-names = "psci";
76 qcom,freq-domain = <&cpufreq_hw 0>;
77 capacity-dmips-mhz = <1024>;
78 dynamic-power-coefficient = <100>;
79 #cooling-cells = <2>;
80 L2_0: l2-cache {
81 compatible = "cache";
82 cache-level = <2>;
83 cache-unified;
84 next-level-cache = <&L3_0>;
85 L3_0: l3-cache {
86 compatible = "cache";
87 cache-level = <3>;
88 cache-unified;
89 };
90 };
91 };
92
93 CPU1: cpu@100 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a510";
96 reg = <0 0x100>;
97 clocks = <&cpufreq_hw 0>;
98 enable-method = "psci";
99 next-level-cache = <&L2_100>;
100 power-domains = <&CPU_PD1>;
101 power-domain-names = "psci";
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 capacity-dmips-mhz = <1024>;
104 dynamic-power-coefficient = <100>;
105 #cooling-cells = <2>;
106 L2_100: l2-cache {
107 compatible = "cache";
108 cache-level = <2>;
109 cache-unified;
110 next-level-cache = <&L3_0>;
111 };
112 };
113
114 CPU2: cpu@200 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a510";
117 reg = <0 0x200>;
118 clocks = <&cpufreq_hw 0>;
119 enable-method = "psci";
120 next-level-cache = <&L2_200>;
121 power-domains = <&CPU_PD2>;
122 power-domain-names = "psci";
123 qcom,freq-domain = <&cpufreq_hw 0>;
124 capacity-dmips-mhz = <1024>;
125 dynamic-power-coefficient = <100>;
126 #cooling-cells = <2>;
127 L2_200: l2-cache {
128 compatible = "cache";
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&L3_0>;
132 };
133 };
134
135 CPU3: cpu@300 {
136 device_type = "cpu";
137 compatible = "arm,cortex-a715";
138 reg = <0 0x300>;
139 clocks = <&cpufreq_hw 1>;
140 enable-method = "psci";
141 next-level-cache = <&L2_300>;
142 power-domains = <&CPU_PD3>;
143 power-domain-names = "psci";
144 qcom,freq-domain = <&cpufreq_hw 1>;
145 capacity-dmips-mhz = <1792>;
146 dynamic-power-coefficient = <270>;
147 #cooling-cells = <2>;
148 L2_300: l2-cache {
149 compatible = "cache";
150 cache-level = <2>;
151 cache-unified;
152 next-level-cache = <&L3_0>;
153 };
154 };
155
156 CPU4: cpu@400 {
157 device_type = "cpu";
158 compatible = "arm,cortex-a715";
159 reg = <0 0x400>;
160 clocks = <&cpufreq_hw 1>;
161 enable-method = "psci";
162 next-level-cache = <&L2_400>;
163 power-domains = <&CPU_PD4>;
164 power-domain-names = "psci";
165 qcom,freq-domain = <&cpufreq_hw 1>;
166 capacity-dmips-mhz = <1792>;
167 dynamic-power-coefficient = <270>;
168 #cooling-cells = <2>;
169 L2_400: l2-cache {
170 compatible = "cache";
171 cache-level = <2>;
172 cache-unified;
173 next-level-cache = <&L3_0>;
174 };
175 };
176
177 CPU5: cpu@500 {
178 device_type = "cpu";
179 compatible = "arm,cortex-a710";
180 reg = <0 0x500>;
181 clocks = <&cpufreq_hw 1>;
182 enable-method = "psci";
183 next-level-cache = <&L2_500>;
184 power-domains = <&CPU_PD5>;
185 power-domain-names = "psci";
186 qcom,freq-domain = <&cpufreq_hw 1>;
187 capacity-dmips-mhz = <1792>;
188 dynamic-power-coefficient = <270>;
189 #cooling-cells = <2>;
190 L2_500: l2-cache {
191 compatible = "cache";
192 cache-level = <2>;
193 cache-unified;
194 next-level-cache = <&L3_0>;
195 };
196 };
197
198 CPU6: cpu@600 {
199 device_type = "cpu";
200 compatible = "arm,cortex-a710";
201 reg = <0 0x600>;
202 clocks = <&cpufreq_hw 1>;
203 enable-method = "psci";
204 next-level-cache = <&L2_600>;
205 power-domains = <&CPU_PD6>;
206 power-domain-names = "psci";
207 qcom,freq-domain = <&cpufreq_hw 1>;
208 capacity-dmips-mhz = <1792>;
209 dynamic-power-coefficient = <270>;
210 #cooling-cells = <2>;
211 L2_600: l2-cache {
212 compatible = "cache";
213 cache-level = <2>;
214 cache-unified;
215 next-level-cache = <&L3_0>;
216 };
217 };
218
219 CPU7: cpu@700 {
220 device_type = "cpu";
221 compatible = "arm,cortex-x3";
222 reg = <0 0x700>;
223 clocks = <&cpufreq_hw 2>;
224 enable-method = "psci";
225 next-level-cache = <&L2_700>;
226 power-domains = <&CPU_PD7>;
227 power-domain-names = "psci";
228 qcom,freq-domain = <&cpufreq_hw 2>;
229 capacity-dmips-mhz = <1894>;
230 dynamic-power-coefficient = <588>;
231 #cooling-cells = <2>;
232 L2_700: l2-cache {
233 compatible = "cache";
234 cache-level = <2>;
235 cache-unified;
236 next-level-cache = <&L3_0>;
237 };
238 };
239
240 cpu-map {
241 cluster0 {
242 core0 {
243 cpu = <&CPU0>;
244 };
245
246 core1 {
247 cpu = <&CPU1>;
248 };
249
250 core2 {
251 cpu = <&CPU2>;
252 };
253
254 core3 {
255 cpu = <&CPU3>;
256 };
257
258 core4 {
259 cpu = <&CPU4>;
260 };
261
262 core5 {
263 cpu = <&CPU5>;
264 };
265
266 core6 {
267 cpu = <&CPU6>;
268 };
269
270 core7 {
271 cpu = <&CPU7>;
272 };
273 };
274 };
275
276 idle-states {
277 entry-method = "psci";
278
279 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
280 compatible = "arm,idle-state";
281 idle-state-name = "silver-rail-power-collapse";
282 arm,psci-suspend-param = <0x40000004>;
283 entry-latency-us = <550>;
284 exit-latency-us = <750>;
285 min-residency-us = <6700>;
286 local-timer-stop;
287 };
288
289 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
290 compatible = "arm,idle-state";
291 idle-state-name = "gold-rail-power-collapse";
292 arm,psci-suspend-param = <0x40000004>;
293 entry-latency-us = <600>;
294 exit-latency-us = <1300>;
295 min-residency-us = <8136>;
296 local-timer-stop;
297 };
298
299 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
300 compatible = "arm,idle-state";
301 idle-state-name = "goldplus-rail-power-collapse";
302 arm,psci-suspend-param = <0x40000004>;
303 entry-latency-us = <500>;
304 exit-latency-us = <1350>;
305 min-residency-us = <7480>;
306 local-timer-stop;
307 };
308 };
309
310 domain-idle-states {
311 CLUSTER_SLEEP_0: cluster-sleep-0 {
312 compatible = "domain-idle-state";
313 arm,psci-suspend-param = <0x41000044>;
314 entry-latency-us = <750>;
315 exit-latency-us = <2350>;
316 min-residency-us = <9144>;
317 };
318
319 CLUSTER_SLEEP_1: cluster-sleep-1 {
320 compatible = "domain-idle-state";
321 arm,psci-suspend-param = <0x4100c344>;
322 entry-latency-us = <2800>;
323 exit-latency-us = <4400>;
324 min-residency-us = <10150>;
325 };
326 };
327 };
328
329 firmware {
330 scm: scm {
331 compatible = "qcom,scm-sm8550", "qcom,scm";
332 qcom,dload-mode = <&tcsr 0x19000>;
333 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
334 };
335 };
336
337 clk_virt: interconnect-0 {
338 compatible = "qcom,sm8550-clk-virt";
339 #interconnect-cells = <2>;
340 qcom,bcm-voters = <&apps_bcm_voter>;
341 };
342
343 mc_virt: interconnect-1 {
344 compatible = "qcom,sm8550-mc-virt";
345 #interconnect-cells = <2>;
346 qcom,bcm-voters = <&apps_bcm_voter>;
347 };
348
349 memory@a0000000 {
350 device_type = "memory";
351 /* We expect the bootloader to fill in the size */
352 reg = <0 0xa0000000 0 0>;
353 };
354
355 pmu-a510 {
356 compatible = "arm,cortex-a510-pmu";
357 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
358 };
359
360 pmu-a710 {
361 compatible = "arm,cortex-a710-pmu";
362 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
363 };
364
365 pmu-a715 {
366 compatible = "arm,cortex-a715-pmu";
367 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
368 };
369
370 pmu-x3 {
371 compatible = "arm,cortex-x3-pmu";
372 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
373 };
374
375 psci {
376 compatible = "arm,psci-1.0";
377 method = "smc";
378
379 CPU_PD0: power-domain-cpu0 {
380 #power-domain-cells = <0>;
381 power-domains = <&CLUSTER_PD>;
382 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
383 };
384
385 CPU_PD1: power-domain-cpu1 {
386 #power-domain-cells = <0>;
387 power-domains = <&CLUSTER_PD>;
388 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
389 };
390
391 CPU_PD2: power-domain-cpu2 {
392 #power-domain-cells = <0>;
393 power-domains = <&CLUSTER_PD>;
394 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
395 };
396
397 CPU_PD3: power-domain-cpu3 {
398 #power-domain-cells = <0>;
399 power-domains = <&CLUSTER_PD>;
400 domain-idle-states = <&BIG_CPU_SLEEP_0>;
401 };
402
403 CPU_PD4: power-domain-cpu4 {
404 #power-domain-cells = <0>;
405 power-domains = <&CLUSTER_PD>;
406 domain-idle-states = <&BIG_CPU_SLEEP_0>;
407 };
408
409 CPU_PD5: power-domain-cpu5 {
410 #power-domain-cells = <0>;
411 power-domains = <&CLUSTER_PD>;
412 domain-idle-states = <&BIG_CPU_SLEEP_0>;
413 };
414
415 CPU_PD6: power-domain-cpu6 {
416 #power-domain-cells = <0>;
417 power-domains = <&CLUSTER_PD>;
418 domain-idle-states = <&BIG_CPU_SLEEP_0>;
419 };
420
421 CPU_PD7: power-domain-cpu7 {
422 #power-domain-cells = <0>;
423 power-domains = <&CLUSTER_PD>;
424 domain-idle-states = <&PRIME_CPU_SLEEP_0>;
425 };
426
427 CLUSTER_PD: power-domain-cluster {
428 #power-domain-cells = <0>;
429 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
430 };
431 };
432
433 reserved_memory: reserved-memory {
434 #address-cells = <2>;
435 #size-cells = <2>;
436 ranges;
437
438 hyp_mem: hyp-region@80000000 {
439 reg = <0 0x80000000 0 0xa00000>;
440 no-map;
441 };
442
443 cpusys_vm_mem: cpusys-vm-region@80a00000 {
444 reg = <0 0x80a00000 0 0x400000>;
445 no-map;
446 };
447
448 hyp_tags_mem: hyp-tags-region@80e00000 {
449 reg = <0 0x80e00000 0 0x3d0000>;
450 no-map;
451 };
452
453 xbl_sc_mem: xbl-sc-region@d8100000 {
454 reg = <0 0xd8100000 0 0x40000>;
455 no-map;
456 };
457
458 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
459 reg = <0 0x811d0000 0 0x30000>;
460 no-map;
461 };
462
463 /* merged xbl_dt_log, xbl_ramdump, aop_image */
464 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
465 reg = <0 0x81a00000 0 0x260000>;
466 no-map;
467 };
468
469 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
470 compatible = "qcom,cmd-db";
471 reg = <0 0x81c60000 0 0x20000>;
472 no-map;
473 };
474
475 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */
476 aop_config_merged_mem: aop-config-merged-region@81c80000 {
477 reg = <0 0x81c80000 0 0x74000>;
478 no-map;
479 };
480
481 /* secdata region can be reused by apps */
482 smem: smem@81d00000 {
483 compatible = "qcom,smem";
484 reg = <0 0x81d00000 0 0x200000>;
485 hwlocks = <&tcsr_mutex 3>;
486 no-map;
487 };
488
489 adsp_mhi_mem: adsp-mhi-region@81f00000 {
490 reg = <0 0x81f00000 0 0x20000>;
491 no-map;
492 };
493
494 global_sync_mem: global-sync-region@82600000 {
495 reg = <0 0x82600000 0 0x100000>;
496 no-map;
497 };
498
499 tz_stat_mem: tz-stat-region@82700000 {
500 reg = <0 0x82700000 0 0x100000>;
501 no-map;
502 };
503
504 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
505 reg = <0 0x82800000 0 0x4600000>;
506 no-map;
507 };
508
509 mpss_mem: mpss-region@8a800000 {
510 reg = <0 0x8a800000 0 0x10800000>;
511 no-map;
512 };
513
514 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
515 reg = <0 0x9b000000 0 0x80000>;
516 no-map;
517 };
518
519 ipa_fw_mem: ipa-fw-region@9b080000 {
520 reg = <0 0x9b080000 0 0x10000>;
521 no-map;
522 };
523
524 ipa_gsi_mem: ipa-gsi-region@9b090000 {
525 reg = <0 0x9b090000 0 0xa000>;
526 no-map;
527 };
528
529 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
530 reg = <0 0x9b09a000 0 0x2000>;
531 no-map;
532 };
533
534 spss_region_mem: spss-region@9b100000 {
535 reg = <0 0x9b100000 0 0x180000>;
536 no-map;
537 };
538
539 /* First part of the "SPU secure shared memory" region */
540 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
541 reg = <0 0x9b280000 0 0x60000>;
542 no-map;
543 };
544
545 /* Second part of the "SPU secure shared memory" region */
546 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
547 reg = <0 0x9b2e0000 0 0x20000>;
548 no-map;
549 };
550
551 camera_mem: camera-region@9b300000 {
552 reg = <0 0x9b300000 0 0x800000>;
553 no-map;
554 };
555
556 video_mem: video-region@9bb00000 {
557 reg = <0 0x9bb00000 0 0x700000>;
558 no-map;
559 };
560
561 cvp_mem: cvp-region@9c200000 {
562 reg = <0 0x9c200000 0 0x700000>;
563 no-map;
564 };
565
566 cdsp_mem: cdsp-region@9c900000 {
567 reg = <0 0x9c900000 0 0x2000000>;
568 no-map;
569 };
570
571 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
572 reg = <0 0x9e900000 0 0x80000>;
573 no-map;
574 };
575
576 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
577 reg = <0 0x9e980000 0 0x80000>;
578 no-map;
579 };
580
581 adspslpi_mem: adspslpi-region@9ea00000 {
582 reg = <0 0x9ea00000 0 0x4080000>;
583 no-map;
584 };
585
586 /* uefi region can be reused by apps */
587
588 /* Linux kernel image is loaded at 0xa8000000 */
589
590 rmtfs_mem: rmtfs-region@d4a80000 {
591 compatible = "qcom,rmtfs-mem";
592 reg = <0x0 0xd4a80000 0x0 0x280000>;
593 no-map;
594
595 qcom,client-id = <1>;
596 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
597 };
598
599 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
600 reg = <0 0xd4d00000 0 0x3300000>;
601 no-map;
602 };
603
604 tz_reserved_mem: tz-reserved-region@d8000000 {
605 reg = <0 0xd8000000 0 0x100000>;
606 no-map;
607 };
608
609 cpucp_fw_mem: cpucp-fw-region@d8140000 {
610 reg = <0 0xd8140000 0 0x1c0000>;
611 no-map;
612 };
613
614 qtee_mem: qtee-region@d8300000 {
615 reg = <0 0xd8300000 0 0x500000>;
616 no-map;
617 };
618
619 ta_mem: ta-region@d8800000 {
620 reg = <0 0xd8800000 0 0x8a00000>;
621 no-map;
622 };
623
624 tz_tags_mem: tz-tags-region@e1200000 {
625 reg = <0 0xe1200000 0 0x2740000>;
626 no-map;
627 };
628
629 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
630 reg = <0 0xe6440000 0 0x279000>;
631 no-map;
632 };
633
634 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
635 reg = <0 0xf3600000 0 0x4aee000>;
636 no-map;
637 };
638
639 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
640 reg = <0 0xf80ee000 0 0x1000>;
641 no-map;
642 };
643
644 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
645 reg = <0 0xf80ef000 0 0x9000>;
646 no-map;
647 };
648
649 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
650 reg = <0 0xf80f8000 0 0x4000>;
651 no-map;
652 };
653
654 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
655 reg = <0 0xf80fc000 0 0x4000>;
656 no-map;
657 };
658
659 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
660 reg = <0 0xf8100000 0 0x100000>;
661 no-map;
662 };
663
664 oem_vm_mem: oem-vm-region@f8400000 {
665 reg = <0 0xf8400000 0 0x4800000>;
666 no-map;
667 };
668
669 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
670 reg = <0 0xfcc00000 0 0x4000>;
671 no-map;
672 };
673
674 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
675 reg = <0 0xfcc04000 0 0x100000>;
676 no-map;
677 };
678
679 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
680 reg = <0 0xfce00000 0 0x2900000>;
681 no-map;
682 };
683
684 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
685 reg = <0 0xff700000 0 0x100000>;
686 no-map;
687 };
688 };
689
690 smp2p-adsp {
691 compatible = "qcom,smp2p";
692 qcom,smem = <443>, <429>;
693 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
694 IPCC_MPROC_SIGNAL_SMP2P
695 IRQ_TYPE_EDGE_RISING>;
696 mboxes = <&ipcc IPCC_CLIENT_LPASS
697 IPCC_MPROC_SIGNAL_SMP2P>;
698
699 qcom,local-pid = <0>;
700 qcom,remote-pid = <2>;
701
702 smp2p_adsp_out: master-kernel {
703 qcom,entry-name = "master-kernel";
704 #qcom,smem-state-cells = <1>;
705 };
706
707 smp2p_adsp_in: slave-kernel {
708 qcom,entry-name = "slave-kernel";
709 interrupt-controller;
710 #interrupt-cells = <2>;
711 };
712 };
713
714 smp2p-cdsp {
715 compatible = "qcom,smp2p";
716 qcom,smem = <94>, <432>;
717 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
718 IPCC_MPROC_SIGNAL_SMP2P
719 IRQ_TYPE_EDGE_RISING>;
720 mboxes = <&ipcc IPCC_CLIENT_CDSP
721 IPCC_MPROC_SIGNAL_SMP2P>;
722
723 qcom,local-pid = <0>;
724 qcom,remote-pid = <5>;
725
726 smp2p_cdsp_out: master-kernel {
727 qcom,entry-name = "master-kernel";
728 #qcom,smem-state-cells = <1>;
729 };
730
731 smp2p_cdsp_in: slave-kernel {
732 qcom,entry-name = "slave-kernel";
733 interrupt-controller;
734 #interrupt-cells = <2>;
735 };
736 };
737
738 smp2p-modem {
739 compatible = "qcom,smp2p";
740 qcom,smem = <435>, <428>;
741 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
742 IPCC_MPROC_SIGNAL_SMP2P
743 IRQ_TYPE_EDGE_RISING>;
744 mboxes = <&ipcc IPCC_CLIENT_MPSS
745 IPCC_MPROC_SIGNAL_SMP2P>;
746
747 qcom,local-pid = <0>;
748 qcom,remote-pid = <1>;
749
750 smp2p_modem_out: master-kernel {
751 qcom,entry-name = "master-kernel";
752 #qcom,smem-state-cells = <1>;
753 };
754
755 smp2p_modem_in: slave-kernel {
756 qcom,entry-name = "slave-kernel";
757 interrupt-controller;
758 #interrupt-cells = <2>;
759 };
760
761 ipa_smp2p_out: ipa-ap-to-modem {
762 qcom,entry-name = "ipa";
763 #qcom,smem-state-cells = <1>;
764 };
765
766 ipa_smp2p_in: ipa-modem-to-ap {
767 qcom,entry-name = "ipa";
768 interrupt-controller;
769 #interrupt-cells = <2>;
770 };
771 };
772
773 soc: soc@0 {
774 compatible = "simple-bus";
775 ranges = <0 0 0 0 0x10 0>;
776 dma-ranges = <0 0 0 0 0x10 0>;
777
778 #address-cells = <2>;
779 #size-cells = <2>;
780
781 gcc: clock-controller@100000 {
782 compatible = "qcom,sm8550-gcc";
783 reg = <0 0x00100000 0 0x1f4200>;
784 #clock-cells = <1>;
785 #reset-cells = <1>;
786 #power-domain-cells = <1>;
787 clocks = <&bi_tcxo_div2>, <&sleep_clk>,
788 <&pcie0_phy>,
789 <&pcie1_phy QMP_PCIE_PIPE_CLK>,
790 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
791 <&ufs_mem_phy 0>,
792 <&ufs_mem_phy 1>,
793 <&ufs_mem_phy 2>,
794 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
795 };
796
797 ipcc: mailbox@408000 {
798 compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
799 reg = <0 0x00408000 0 0x1000>;
800 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
801 interrupt-controller;
802 #interrupt-cells = <3>;
803 #mbox-cells = <2>;
804 };
805
806 gpi_dma2: dma-controller@800000 {
807 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
808 #dma-cells = <3>;
809 reg = <0 0x00800000 0 0x60000>;
810 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
814 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
816 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
818 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
819 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
822 dma-channels = <12>;
823 dma-channel-mask = <0x3e>;
824 iommus = <&apps_smmu 0x436 0>;
825 dma-coherent;
826 status = "disabled";
827 };
828
829 qupv3_id_1: geniqup@8c0000 {
830 compatible = "qcom,geni-se-qup";
831 reg = <0 0x008c0000 0 0x2000>;
832 ranges;
833 clock-names = "m-ahb", "s-ahb";
834 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
835 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
836 iommus = <&apps_smmu 0x423 0>;
837 dma-coherent;
838 #address-cells = <2>;
839 #size-cells = <2>;
840 status = "disabled";
841
842 i2c8: i2c@880000 {
843 compatible = "qcom,geni-i2c";
844 reg = <0 0x00880000 0 0x4000>;
845 clock-names = "se";
846 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
847 pinctrl-names = "default";
848 pinctrl-0 = <&qup_i2c8_data_clk>;
849 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
850 #address-cells = <1>;
851 #size-cells = <0>;
852 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
853 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
854 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
855 interconnect-names = "qup-core", "qup-config", "qup-memory";
856 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
857 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
858 dma-names = "tx", "rx";
859 status = "disabled";
860 };
861
862 spi8: spi@880000 {
863 compatible = "qcom,geni-spi";
864 reg = <0 0x00880000 0 0x4000>;
865 clock-names = "se";
866 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
867 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
868 pinctrl-names = "default";
869 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
870 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
871 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
872 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
873 interconnect-names = "qup-core", "qup-config", "qup-memory";
874 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
875 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
876 dma-names = "tx", "rx";
877 #address-cells = <1>;
878 #size-cells = <0>;
879 status = "disabled";
880 };
881
882 i2c9: i2c@884000 {
883 compatible = "qcom,geni-i2c";
884 reg = <0 0x00884000 0 0x4000>;
885 clock-names = "se";
886 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
887 pinctrl-names = "default";
888 pinctrl-0 = <&qup_i2c9_data_clk>;
889 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
890 #address-cells = <1>;
891 #size-cells = <0>;
892 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
893 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
894 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
895 interconnect-names = "qup-core", "qup-config", "qup-memory";
896 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
897 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
898 dma-names = "tx", "rx";
899 status = "disabled";
900 };
901
902 spi9: spi@884000 {
903 compatible = "qcom,geni-spi";
904 reg = <0 0x00884000 0 0x4000>;
905 clock-names = "se";
906 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
907 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
908 pinctrl-names = "default";
909 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
910 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
911 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
912 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
913 interconnect-names = "qup-core", "qup-config", "qup-memory";
914 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
915 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
916 dma-names = "tx", "rx";
917 #address-cells = <1>;
918 #size-cells = <0>;
919 status = "disabled";
920 };
921
922 i2c10: i2c@888000 {
923 compatible = "qcom,geni-i2c";
924 reg = <0 0x00888000 0 0x4000>;
925 clock-names = "se";
926 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
927 pinctrl-names = "default";
928 pinctrl-0 = <&qup_i2c10_data_clk>;
929 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
930 #address-cells = <1>;
931 #size-cells = <0>;
932 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
933 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
934 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
935 interconnect-names = "qup-core", "qup-config", "qup-memory";
936 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
937 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
938 dma-names = "tx", "rx";
939 status = "disabled";
940 };
941
942 spi10: spi@888000 {
943 compatible = "qcom,geni-spi";
944 reg = <0 0x00888000 0 0x4000>;
945 clock-names = "se";
946 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
947 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
952 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
953 interconnect-names = "qup-core", "qup-config", "qup-memory";
954 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
955 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
956 dma-names = "tx", "rx";
957 #address-cells = <1>;
958 #size-cells = <0>;
959 status = "disabled";
960 };
961
962 i2c11: i2c@88c000 {
963 compatible = "qcom,geni-i2c";
964 reg = <0 0x0088c000 0 0x4000>;
965 clock-names = "se";
966 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
967 pinctrl-names = "default";
968 pinctrl-0 = <&qup_i2c11_data_clk>;
969 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
970 #address-cells = <1>;
971 #size-cells = <0>;
972 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
974 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
975 interconnect-names = "qup-core", "qup-config", "qup-memory";
976 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
977 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
978 dma-names = "tx", "rx";
979 status = "disabled";
980 };
981
982 spi11: spi@88c000 {
983 compatible = "qcom,geni-spi";
984 reg = <0 0x0088c000 0 0x4000>;
985 clock-names = "se";
986 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
987 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
988 pinctrl-names = "default";
989 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
990 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
991 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
992 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
993 interconnect-names = "qup-core", "qup-config", "qup-memory";
994 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
995 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
996 dma-names = "tx", "rx";
997 #address-cells = <1>;
998 #size-cells = <0>;
999 status = "disabled";
1000 };
1001
1002 i2c12: i2c@890000 {
1003 compatible = "qcom,geni-i2c";
1004 reg = <0 0x00890000 0 0x4000>;
1005 clock-names = "se";
1006 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&qup_i2c12_data_clk>;
1009 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1012 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1013 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1014 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1015 interconnect-names = "qup-core", "qup-config", "qup-memory";
1016 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1017 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1018 dma-names = "tx", "rx";
1019 status = "disabled";
1020 };
1021
1022 spi12: spi@890000 {
1023 compatible = "qcom,geni-spi";
1024 reg = <0 0x00890000 0 0x4000>;
1025 clock-names = "se";
1026 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1027 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1030 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1031 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1032 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1033 interconnect-names = "qup-core", "qup-config", "qup-memory";
1034 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1035 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1036 dma-names = "tx", "rx";
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1039 status = "disabled";
1040 };
1041
1042 i2c13: i2c@894000 {
1043 compatible = "qcom,geni-i2c";
1044 reg = <0 0x00894000 0 0x4000>;
1045 clock-names = "se";
1046 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1047 pinctrl-names = "default";
1048 pinctrl-0 = <&qup_i2c13_data_clk>;
1049 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1050 #address-cells = <1>;
1051 #size-cells = <0>;
1052 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1053 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1054 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1055 interconnect-names = "qup-core", "qup-config", "qup-memory";
1056 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1057 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1058 dma-names = "tx", "rx";
1059 status = "disabled";
1060 };
1061
1062 spi13: spi@894000 {
1063 compatible = "qcom,geni-spi";
1064 reg = <0 0x00894000 0 0x4000>;
1065 clock-names = "se";
1066 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1067 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1068 pinctrl-names = "default";
1069 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1070 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1071 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1072 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1073 interconnect-names = "qup-core", "qup-config", "qup-memory";
1074 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1075 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1076 dma-names = "tx", "rx";
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1079 status = "disabled";
1080 };
1081
1082 uart14: serial@898000 {
1083 compatible = "qcom,geni-uart";
1084 reg = <0 0x898000 0 0x4000>;
1085 clock-names = "se";
1086 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1087 pinctrl-names = "default";
1088 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1089 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1090 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1091 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
1092 interconnect-names = "qup-core", "qup-config";
1093 status = "disabled";
1094 };
1095
1096 i2c15: i2c@89c000 {
1097 compatible = "qcom,geni-i2c";
1098 reg = <0 0x0089c000 0 0x4000>;
1099 clock-names = "se";
1100 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&qup_i2c15_data_clk>;
1103 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1106 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1107 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1108 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1109 interconnect-names = "qup-core", "qup-config", "qup-memory";
1110 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1111 <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1112 dma-names = "tx", "rx";
1113 status = "disabled";
1114 };
1115
1116 spi15: spi@89c000 {
1117 compatible = "qcom,geni-spi";
1118 reg = <0 0x0089c000 0 0x4000>;
1119 clock-names = "se";
1120 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1121 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1122 pinctrl-names = "default";
1123 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1124 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1125 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1126 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1127 interconnect-names = "qup-core", "qup-config", "qup-memory";
1128 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1129 <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1130 dma-names = "tx", "rx";
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133 status = "disabled";
1134 };
1135 };
1136
1137 i2c_master_hub_0: geniqup@9c0000 {
1138 compatible = "qcom,geni-se-i2c-master-hub";
1139 reg = <0x0 0x009c0000 0x0 0x2000>;
1140 clock-names = "s-ahb";
1141 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
1142 #address-cells = <2>;
1143 #size-cells = <2>;
1144 ranges;
1145 status = "disabled";
1146
1147 i2c_hub_0: i2c@980000 {
1148 compatible = "qcom,geni-i2c-master-hub";
1149 reg = <0x0 0x00980000 0x0 0x4000>;
1150 clock-names = "se", "core";
1151 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
1152 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1153 pinctrl-names = "default";
1154 pinctrl-0 = <&hub_i2c0_data_clk>;
1155 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
1156 #address-cells = <1>;
1157 #size-cells = <0>;
1158 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1159 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1160 interconnect-names = "qup-core", "qup-config";
1161 status = "disabled";
1162 };
1163
1164 i2c_hub_1: i2c@984000 {
1165 compatible = "qcom,geni-i2c-master-hub";
1166 reg = <0x0 0x00984000 0x0 0x4000>;
1167 clock-names = "se", "core";
1168 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
1169 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1170 pinctrl-names = "default";
1171 pinctrl-0 = <&hub_i2c1_data_clk>;
1172 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1175 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1176 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1177 interconnect-names = "qup-core", "qup-config";
1178 status = "disabled";
1179 };
1180
1181 i2c_hub_2: i2c@988000 {
1182 compatible = "qcom,geni-i2c-master-hub";
1183 reg = <0x0 0x00988000 0x0 0x4000>;
1184 clock-names = "se", "core";
1185 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
1186 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1187 pinctrl-names = "default";
1188 pinctrl-0 = <&hub_i2c2_data_clk>;
1189 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1192 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1193 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1194 interconnect-names = "qup-core", "qup-config";
1195 status = "disabled";
1196 };
1197
1198 i2c_hub_3: i2c@98c000 {
1199 compatible = "qcom,geni-i2c-master-hub";
1200 reg = <0x0 0x0098c000 0x0 0x4000>;
1201 clock-names = "se", "core";
1202 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
1203 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1204 pinctrl-names = "default";
1205 pinctrl-0 = <&hub_i2c3_data_clk>;
1206 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1207 #address-cells = <1>;
1208 #size-cells = <0>;
1209 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1210 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1211 interconnect-names = "qup-core", "qup-config";
1212 status = "disabled";
1213 };
1214
1215 i2c_hub_4: i2c@990000 {
1216 compatible = "qcom,geni-i2c-master-hub";
1217 reg = <0x0 0x00990000 0x0 0x4000>;
1218 clock-names = "se", "core";
1219 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
1220 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1221 pinctrl-names = "default";
1222 pinctrl-0 = <&hub_i2c4_data_clk>;
1223 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1226 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1227 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1228 interconnect-names = "qup-core", "qup-config";
1229 status = "disabled";
1230 };
1231
1232 i2c_hub_5: i2c@994000 {
1233 compatible = "qcom,geni-i2c-master-hub";
1234 reg = <0 0x00994000 0 0x4000>;
1235 clock-names = "se", "core";
1236 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
1237 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1238 pinctrl-names = "default";
1239 pinctrl-0 = <&hub_i2c5_data_clk>;
1240 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1243 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1244 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1245 interconnect-names = "qup-core", "qup-config";
1246 status = "disabled";
1247 };
1248
1249 i2c_hub_6: i2c@998000 {
1250 compatible = "qcom,geni-i2c-master-hub";
1251 reg = <0 0x00998000 0 0x4000>;
1252 clock-names = "se", "core";
1253 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
1254 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1255 pinctrl-names = "default";
1256 pinctrl-0 = <&hub_i2c6_data_clk>;
1257 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
1258 #address-cells = <1>;
1259 #size-cells = <0>;
1260 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1261 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1262 interconnect-names = "qup-core", "qup-config";
1263 status = "disabled";
1264 };
1265
1266 i2c_hub_7: i2c@99c000 {
1267 compatible = "qcom,geni-i2c-master-hub";
1268 reg = <0 0x0099c000 0 0x4000>;
1269 clock-names = "se", "core";
1270 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
1271 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&hub_i2c7_data_clk>;
1274 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
1275 #address-cells = <1>;
1276 #size-cells = <0>;
1277 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1278 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1279 interconnect-names = "qup-core", "qup-config";
1280 status = "disabled";
1281 };
1282
1283 i2c_hub_8: i2c@9a0000 {
1284 compatible = "qcom,geni-i2c-master-hub";
1285 reg = <0 0x009a0000 0 0x4000>;
1286 clock-names = "se", "core";
1287 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
1288 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1289 pinctrl-names = "default";
1290 pinctrl-0 = <&hub_i2c8_data_clk>;
1291 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1294 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1295 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1296 interconnect-names = "qup-core", "qup-config";
1297 status = "disabled";
1298 };
1299
1300 i2c_hub_9: i2c@9a4000 {
1301 compatible = "qcom,geni-i2c-master-hub";
1302 reg = <0 0x009a4000 0 0x4000>;
1303 clock-names = "se", "core";
1304 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
1305 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1306 pinctrl-names = "default";
1307 pinctrl-0 = <&hub_i2c9_data_clk>;
1308 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1311 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1312 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1313 interconnect-names = "qup-core", "qup-config";
1314 status = "disabled";
1315 };
1316 };
1317
1318 gpi_dma1: dma-controller@a00000 {
1319 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1320 #dma-cells = <3>;
1321 reg = <0 0x00a00000 0 0x60000>;
1322 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1323 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1324 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1325 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1326 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1327 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1328 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1329 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1334 dma-channels = <12>;
1335 dma-channel-mask = <0x1e>;
1336 iommus = <&apps_smmu 0xb6 0>;
1337 dma-coherent;
1338 status = "disabled";
1339 };
1340
1341 qupv3_id_0: geniqup@ac0000 {
1342 compatible = "qcom,geni-se-qup";
1343 reg = <0 0x00ac0000 0 0x2000>;
1344 ranges;
1345 clock-names = "m-ahb", "s-ahb";
1346 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1347 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1348 iommus = <&apps_smmu 0xa3 0>;
1349 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1350 interconnect-names = "qup-core";
1351 dma-coherent;
1352 #address-cells = <2>;
1353 #size-cells = <2>;
1354 status = "disabled";
1355
1356 i2c0: i2c@a80000 {
1357 compatible = "qcom,geni-i2c";
1358 reg = <0 0x00a80000 0 0x4000>;
1359 clock-names = "se";
1360 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1361 pinctrl-names = "default";
1362 pinctrl-0 = <&qup_i2c0_data_clk>;
1363 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1364 #address-cells = <1>;
1365 #size-cells = <0>;
1366 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1367 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1368 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1369 interconnect-names = "qup-core", "qup-config", "qup-memory";
1370 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1371 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1372 dma-names = "tx", "rx";
1373 status = "disabled";
1374 };
1375
1376 spi0: spi@a80000 {
1377 compatible = "qcom,geni-spi";
1378 reg = <0 0x00a80000 0 0x4000>;
1379 clock-names = "se";
1380 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1381 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1382 pinctrl-names = "default";
1383 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1384 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1385 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1386 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1387 interconnect-names = "qup-core", "qup-config", "qup-memory";
1388 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1389 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1390 dma-names = "tx", "rx";
1391 #address-cells = <1>;
1392 #size-cells = <0>;
1393 status = "disabled";
1394 };
1395
1396 i2c1: i2c@a84000 {
1397 compatible = "qcom,geni-i2c";
1398 reg = <0 0x00a84000 0 0x4000>;
1399 clock-names = "se";
1400 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1401 pinctrl-names = "default";
1402 pinctrl-0 = <&qup_i2c1_data_clk>;
1403 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1404 #address-cells = <1>;
1405 #size-cells = <0>;
1406 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1407 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1408 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1409 interconnect-names = "qup-core", "qup-config", "qup-memory";
1410 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1411 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1412 dma-names = "tx", "rx";
1413 status = "disabled";
1414 };
1415
1416 spi1: spi@a84000 {
1417 compatible = "qcom,geni-spi";
1418 reg = <0 0x00a84000 0 0x4000>;
1419 clock-names = "se";
1420 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1421 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1422 pinctrl-names = "default";
1423 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1424 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1425 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1426 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1427 interconnect-names = "qup-core", "qup-config", "qup-memory";
1428 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1429 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1430 dma-names = "tx", "rx";
1431 #address-cells = <1>;
1432 #size-cells = <0>;
1433 status = "disabled";
1434 };
1435
1436 i2c2: i2c@a88000 {
1437 compatible = "qcom,geni-i2c";
1438 reg = <0 0x00a88000 0 0x4000>;
1439 clock-names = "se";
1440 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1441 pinctrl-names = "default";
1442 pinctrl-0 = <&qup_i2c2_data_clk>;
1443 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1444 #address-cells = <1>;
1445 #size-cells = <0>;
1446 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1447 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1448 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1449 interconnect-names = "qup-core", "qup-config", "qup-memory";
1450 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1451 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1452 dma-names = "tx", "rx";
1453 status = "disabled";
1454 };
1455
1456 spi2: spi@a88000 {
1457 compatible = "qcom,geni-spi";
1458 reg = <0 0x00a88000 0 0x4000>;
1459 clock-names = "se";
1460 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1461 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1462 pinctrl-names = "default";
1463 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1464 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1465 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1466 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1467 interconnect-names = "qup-core", "qup-config", "qup-memory";
1468 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1469 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1470 dma-names = "tx", "rx";
1471 #address-cells = <1>;
1472 #size-cells = <0>;
1473 status = "disabled";
1474 };
1475
1476 i2c3: i2c@a8c000 {
1477 compatible = "qcom,geni-i2c";
1478 reg = <0 0x00a8c000 0 0x4000>;
1479 clock-names = "se";
1480 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1481 pinctrl-names = "default";
1482 pinctrl-0 = <&qup_i2c3_data_clk>;
1483 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1484 #address-cells = <1>;
1485 #size-cells = <0>;
1486 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1487 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1488 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1489 interconnect-names = "qup-core", "qup-config", "qup-memory";
1490 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1491 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1492 dma-names = "tx", "rx";
1493 status = "disabled";
1494 };
1495
1496 spi3: spi@a8c000 {
1497 compatible = "qcom,geni-spi";
1498 reg = <0 0x00a8c000 0 0x4000>;
1499 clock-names = "se";
1500 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1501 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1502 pinctrl-names = "default";
1503 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1504 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1505 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1506 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1507 interconnect-names = "qup-core", "qup-config", "qup-memory";
1508 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1509 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1510 dma-names = "tx", "rx";
1511 #address-cells = <1>;
1512 #size-cells = <0>;
1513 status = "disabled";
1514 };
1515
1516 i2c4: i2c@a90000 {
1517 compatible = "qcom,geni-i2c";
1518 reg = <0 0x00a90000 0 0x4000>;
1519 clock-names = "se";
1520 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1521 pinctrl-names = "default";
1522 pinctrl-0 = <&qup_i2c4_data_clk>;
1523 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1524 #address-cells = <1>;
1525 #size-cells = <0>;
1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1527 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1528 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1529 interconnect-names = "qup-core", "qup-config", "qup-memory";
1530 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1531 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1532 dma-names = "tx", "rx";
1533 status = "disabled";
1534 };
1535
1536 spi4: spi@a90000 {
1537 compatible = "qcom,geni-spi";
1538 reg = <0 0x00a90000 0 0x4000>;
1539 clock-names = "se";
1540 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1541 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1542 pinctrl-names = "default";
1543 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1544 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1545 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1546 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1547 interconnect-names = "qup-core", "qup-config", "qup-memory";
1548 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1549 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1550 dma-names = "tx", "rx";
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1553 status = "disabled";
1554 };
1555
1556 i2c5: i2c@a94000 {
1557 compatible = "qcom,geni-i2c";
1558 reg = <0 0x00a94000 0 0x4000>;
1559 clock-names = "se";
1560 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1561 pinctrl-names = "default";
1562 pinctrl-0 = <&qup_i2c5_data_clk>;
1563 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1564 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1565 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1566 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1567 interconnect-names = "qup-core", "qup-config", "qup-memory";
1568 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1569 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1570 dma-names = "tx", "rx";
1571 #address-cells = <1>;
1572 #size-cells = <0>;
1573 status = "disabled";
1574 };
1575
1576 spi5: spi@a94000 {
1577 compatible = "qcom,geni-spi";
1578 reg = <0 0x00a94000 0 0x4000>;
1579 clock-names = "se";
1580 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1581 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1582 pinctrl-names = "default";
1583 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1584 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1585 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1586 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1587 interconnect-names = "qup-core", "qup-config", "qup-memory";
1588 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1589 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1590 dma-names = "tx", "rx";
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1593 status = "disabled";
1594 };
1595
1596 i2c6: i2c@a98000 {
1597 compatible = "qcom,geni-i2c";
1598 reg = <0 0x00a98000 0 0x4000>;
1599 clock-names = "se";
1600 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1601 pinctrl-names = "default";
1602 pinctrl-0 = <&qup_i2c6_data_clk>;
1603 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1605 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1606 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1607 interconnect-names = "qup-core", "qup-config", "qup-memory";
1608 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1609 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1610 dma-names = "tx", "rx";
1611 #address-cells = <1>;
1612 #size-cells = <0>;
1613 status = "disabled";
1614 };
1615
1616 spi6: spi@a98000 {
1617 compatible = "qcom,geni-spi";
1618 reg = <0 0x00a98000 0 0x4000>;
1619 clock-names = "se";
1620 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1621 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1622 pinctrl-names = "default";
1623 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1624 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1625 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1626 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1627 interconnect-names = "qup-core", "qup-config", "qup-memory";
1628 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1629 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1630 dma-names = "tx", "rx";
1631 #address-cells = <1>;
1632 #size-cells = <0>;
1633 status = "disabled";
1634 };
1635
1636 uart7: serial@a9c000 {
1637 compatible = "qcom,geni-debug-uart";
1638 reg = <0 0x00a9c000 0 0x4000>;
1639 clock-names = "se";
1640 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1641 pinctrl-names = "default";
1642 pinctrl-0 = <&qup_uart7_default>;
1643 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1644 interconnect-names = "qup-core", "qup-config";
1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1647 status = "disabled";
1648 };
1649 };
1650
1651 cnoc_main: interconnect@1500000 {
1652 compatible = "qcom,sm8550-cnoc-main";
1653 reg = <0 0x01500000 0 0x13080>;
1654 #interconnect-cells = <2>;
1655 qcom,bcm-voters = <&apps_bcm_voter>;
1656 };
1657
1658 config_noc: interconnect@1600000 {
1659 compatible = "qcom,sm8550-config-noc";
1660 reg = <0 0x01600000 0 0x6200>;
1661 #interconnect-cells = <2>;
1662 qcom,bcm-voters = <&apps_bcm_voter>;
1663 };
1664
1665 system_noc: interconnect@1680000 {
1666 compatible = "qcom,sm8550-system-noc";
1667 reg = <0 0x01680000 0 0x1d080>;
1668 #interconnect-cells = <2>;
1669 qcom,bcm-voters = <&apps_bcm_voter>;
1670 };
1671
1672 pcie_noc: interconnect@16c0000 {
1673 compatible = "qcom,sm8550-pcie-anoc";
1674 reg = <0 0x016c0000 0 0x12200>;
1675 #interconnect-cells = <2>;
1676 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1677 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
1678 qcom,bcm-voters = <&apps_bcm_voter>;
1679 };
1680
1681 aggre1_noc: interconnect@16e0000 {
1682 compatible = "qcom,sm8550-aggre1-noc";
1683 reg = <0 0x016e0000 0 0x14400>;
1684 #interconnect-cells = <2>;
1685 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1686 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
1687 qcom,bcm-voters = <&apps_bcm_voter>;
1688 };
1689
1690 aggre2_noc: interconnect@1700000 {
1691 compatible = "qcom,sm8550-aggre2-noc";
1692 reg = <0 0x01700000 0 0x1e400>;
1693 #interconnect-cells = <2>;
1694 clocks = <&rpmhcc RPMH_IPA_CLK>;
1695 qcom,bcm-voters = <&apps_bcm_voter>;
1696 };
1697
1698 mmss_noc: interconnect@1780000 {
1699 compatible = "qcom,sm8550-mmss-noc";
1700 reg = <0 0x01780000 0 0x5b800>;
1701 #interconnect-cells = <2>;
1702 qcom,bcm-voters = <&apps_bcm_voter>;
1703 };
1704
1705 rng: rng@10c3000 {
1706 compatible = "qcom,sm8550-trng", "qcom,trng";
1707 reg = <0 0x010c3000 0 0x1000>;
1708 };
1709
1710 pcie0: pcie@1c00000 {
1711 device_type = "pci";
1712 compatible = "qcom,pcie-sm8550";
1713 reg = <0 0x01c00000 0 0x3000>,
1714 <0 0x60000000 0 0xf1d>,
1715 <0 0x60000f20 0 0xa8>,
1716 <0 0x60001000 0 0x1000>,
1717 <0 0x60100000 0 0x100000>;
1718 reg-names = "parf", "dbi", "elbi", "atu", "config";
1719 #address-cells = <3>;
1720 #size-cells = <2>;
1721 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1722 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1723 bus-range = <0x00 0xff>;
1724
1725 dma-coherent;
1726
1727 linux,pci-domain = <0>;
1728 num-lanes = <2>;
1729
1730 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1738 interrupt-names = "msi0",
1739 "msi1",
1740 "msi2",
1741 "msi3",
1742 "msi4",
1743 "msi5",
1744 "msi6",
1745 "msi7";
1746 #interrupt-cells = <1>;
1747 interrupt-map-mask = <0 0 0 0x7>;
1748 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1749 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1750 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1751 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1752
1753 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1754 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1755 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1756 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1757 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1758 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1759 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
1760 clock-names = "aux",
1761 "cfg",
1762 "bus_master",
1763 "bus_slave",
1764 "slave_q2a",
1765 "ddrss_sf_tbu",
1766 "noc_aggr";
1767
1768 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
1769 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1770 interconnect-names = "pcie-mem", "cpu-pcie";
1771
1772 msi-map = <0x0 &gic_its 0x1400 0x1>,
1773 <0x100 &gic_its 0x1401 0x1>;
1774 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1775 <0x100 &apps_smmu 0x1401 0x1>;
1776
1777 resets = <&gcc GCC_PCIE_0_BCR>;
1778 reset-names = "pci";
1779
1780 power-domains = <&gcc PCIE_0_GDSC>;
1781
1782 phys = <&pcie0_phy>;
1783 phy-names = "pciephy";
1784
1785 status = "disabled";
1786
1787 pcieport0: pcie@0 {
1788 device_type = "pci";
1789 reg = <0x0 0x0 0x0 0x0 0x0>;
1790 bus-range = <0x01 0xff>;
1791
1792 #address-cells = <3>;
1793 #size-cells = <2>;
1794 ranges;
1795 };
1796 };
1797
1798 pcie0_phy: phy@1c06000 {
1799 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1800 reg = <0 0x01c06000 0 0x2000>;
1801
1802 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1803 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1804 <&tcsr TCSR_PCIE_0_CLKREF_EN>,
1805 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1806 <&gcc GCC_PCIE_0_PIPE_CLK>;
1807 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1808 "pipe";
1809
1810 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1811 reset-names = "phy";
1812
1813 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1814 assigned-clock-rates = <100000000>;
1815
1816 power-domains = <&gcc PCIE_0_PHY_GDSC>;
1817
1818 #clock-cells = <0>;
1819 clock-output-names = "pcie0_pipe_clk";
1820
1821 #phy-cells = <0>;
1822
1823 status = "disabled";
1824 };
1825
1826 pcie1: pcie@1c08000 {
1827 device_type = "pci";
1828 compatible = "qcom,pcie-sm8550";
1829 reg = <0x0 0x01c08000 0x0 0x3000>,
1830 <0x0 0x40000000 0x0 0xf1d>,
1831 <0x0 0x40000f20 0x0 0xa8>,
1832 <0x0 0x40001000 0x0 0x1000>,
1833 <0x0 0x40100000 0x0 0x100000>;
1834 reg-names = "parf", "dbi", "elbi", "atu", "config";
1835 #address-cells = <3>;
1836 #size-cells = <2>;
1837 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1838 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1839 bus-range = <0x00 0xff>;
1840
1841 dma-coherent;
1842
1843 linux,pci-domain = <1>;
1844 num-lanes = <2>;
1845
1846 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1847 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1848 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1849 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1850 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1851 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1852 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1853 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1854 interrupt-names = "msi0",
1855 "msi1",
1856 "msi2",
1857 "msi3",
1858 "msi4",
1859 "msi5",
1860 "msi6",
1861 "msi7";
1862 #interrupt-cells = <1>;
1863 interrupt-map-mask = <0 0 0 0x7>;
1864 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1865 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1866 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1867 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1868
1869 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1870 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1871 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1872 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1873 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1874 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1875 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1876 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
1877 clock-names = "aux",
1878 "cfg",
1879 "bus_master",
1880 "bus_slave",
1881 "slave_q2a",
1882 "ddrss_sf_tbu",
1883 "noc_aggr",
1884 "cnoc_sf_axi";
1885
1886 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1887 assigned-clock-rates = <19200000>;
1888
1889 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
1890 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1891 interconnect-names = "pcie-mem", "cpu-pcie";
1892
1893 msi-map = <0x0 &gic_its 0x1480 0x1>,
1894 <0x100 &gic_its 0x1481 0x1>;
1895 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1896 <0x100 &apps_smmu 0x1481 0x1>;
1897
1898 resets = <&gcc GCC_PCIE_1_BCR>,
1899 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
1900 reset-names = "pci", "link_down";
1901
1902 power-domains = <&gcc PCIE_1_GDSC>;
1903
1904 phys = <&pcie1_phy>;
1905 phy-names = "pciephy";
1906
1907 status = "disabled";
1908
1909 pcie@0 {
1910 device_type = "pci";
1911 reg = <0x0 0x0 0x0 0x0 0x0>;
1912 bus-range = <0x01 0xff>;
1913
1914 #address-cells = <3>;
1915 #size-cells = <2>;
1916 ranges;
1917 };
1918 };
1919
1920 pcie1_phy: phy@1c0e000 {
1921 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1922 reg = <0x0 0x01c0e000 0x0 0x2000>;
1923
1924 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1925 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1926 <&tcsr TCSR_PCIE_1_CLKREF_EN>,
1927 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
1928 <&gcc GCC_PCIE_1_PIPE_CLK>;
1929 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1930 "pipe";
1931
1932 resets = <&gcc GCC_PCIE_1_PHY_BCR>,
1933 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
1934 reset-names = "phy", "phy_nocsr";
1935
1936 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1937 assigned-clock-rates = <100000000>;
1938
1939 power-domains = <&gcc PCIE_1_PHY_GDSC>;
1940
1941 #clock-cells = <1>;
1942 clock-output-names = "pcie1_pipe_clk";
1943
1944 #phy-cells = <0>;
1945
1946 status = "disabled";
1947 };
1948
1949 cryptobam: dma-controller@1dc4000 {
1950 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1951 reg = <0x0 0x01dc4000 0x0 0x28000>;
1952 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1953 #dma-cells = <1>;
1954 qcom,ee = <0>;
1955 qcom,controlled-remotely;
1956 iommus = <&apps_smmu 0x480 0x0>,
1957 <&apps_smmu 0x481 0x0>;
1958 };
1959
1960 crypto: crypto@1dfa000 {
1961 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1962 reg = <0x0 0x01dfa000 0x0 0x6000>;
1963 dmas = <&cryptobam 4>, <&cryptobam 5>;
1964 dma-names = "rx", "tx";
1965 iommus = <&apps_smmu 0x480 0x0>,
1966 <&apps_smmu 0x481 0x0>;
1967 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1968 interconnect-names = "memory";
1969 };
1970
1971 ufs_mem_phy: phy@1d80000 {
1972 compatible = "qcom,sm8550-qmp-ufs-phy";
1973 reg = <0x0 0x01d80000 0x0 0x2000>;
1974 clocks = <&rpmhcc RPMH_CXO_CLK>,
1975 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1976 <&tcsr TCSR_UFS_CLKREF_EN>;
1977 clock-names = "ref",
1978 "ref_aux",
1979 "qref";
1980
1981 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1982
1983 resets = <&ufs_mem_hc 0>;
1984 reset-names = "ufsphy";
1985
1986 #clock-cells = <1>;
1987 #phy-cells = <0>;
1988
1989 status = "disabled";
1990 };
1991
1992 ufs_mem_hc: ufs@1d84000 {
1993 compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1994 "jedec,ufs-2.0";
1995 reg = <0x0 0x01d84000 0x0 0x3000>;
1996 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1997 phys = <&ufs_mem_phy>;
1998 phy-names = "ufsphy";
1999 lanes-per-direction = <2>;
2000 #reset-cells = <1>;
2001 resets = <&gcc GCC_UFS_PHY_BCR>;
2002 reset-names = "rst";
2003
2004 power-domains = <&gcc UFS_PHY_GDSC>;
2005 required-opps = <&rpmhpd_opp_nom>;
2006
2007 iommus = <&apps_smmu 0x60 0x0>;
2008 dma-coherent;
2009
2010 operating-points-v2 = <&ufs_opp_table>;
2011 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
2012 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2013
2014 interconnect-names = "ufs-ddr", "cpu-ufs";
2015 clock-names = "core_clk",
2016 "bus_aggr_clk",
2017 "iface_clk",
2018 "core_clk_unipro",
2019 "ref_clk",
2020 "tx_lane0_sync_clk",
2021 "rx_lane0_sync_clk",
2022 "rx_lane1_sync_clk";
2023 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2024 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2025 <&gcc GCC_UFS_PHY_AHB_CLK>,
2026 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2027 <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
2028 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2029 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2030 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2031 qcom,ice = <&ice>;
2032
2033 status = "disabled";
2034
2035 ufs_opp_table: opp-table {
2036 compatible = "operating-points-v2";
2037
2038 opp-75000000 {
2039 opp-hz = /bits/ 64 <75000000>,
2040 /bits/ 64 <0>,
2041 /bits/ 64 <0>,
2042 /bits/ 64 <75000000>,
2043 /bits/ 64 <0>,
2044 /bits/ 64 <0>,
2045 /bits/ 64 <0>,
2046 /bits/ 64 <0>;
2047 required-opps = <&rpmhpd_opp_low_svs>;
2048 };
2049
2050 opp-150000000 {
2051 opp-hz = /bits/ 64 <150000000>,
2052 /bits/ 64 <0>,
2053 /bits/ 64 <0>,
2054 /bits/ 64 <150000000>,
2055 /bits/ 64 <0>,
2056 /bits/ 64 <0>,
2057 /bits/ 64 <0>,
2058 /bits/ 64 <0>;
2059 required-opps = <&rpmhpd_opp_svs>;
2060 };
2061
2062 opp-300000000 {
2063 opp-hz = /bits/ 64 <300000000>,
2064 /bits/ 64 <0>,
2065 /bits/ 64 <0>,
2066 /bits/ 64 <300000000>,
2067 /bits/ 64 <0>,
2068 /bits/ 64 <0>,
2069 /bits/ 64 <0>,
2070 /bits/ 64 <0>;
2071 required-opps = <&rpmhpd_opp_nom>;
2072 };
2073 };
2074 };
2075
2076 ice: crypto@1d88000 {
2077 compatible = "qcom,sm8550-inline-crypto-engine",
2078 "qcom,inline-crypto-engine";
2079 reg = <0 0x01d88000 0 0x8000>;
2080 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2081 };
2082
2083 tcsr_mutex: hwlock@1f40000 {
2084 compatible = "qcom,tcsr-mutex";
2085 reg = <0 0x01f40000 0 0x20000>;
2086 #hwlock-cells = <1>;
2087 };
2088
2089 tcsr: clock-controller@1fc0000 {
2090 compatible = "qcom,sm8550-tcsr", "syscon";
2091 reg = <0 0x01fc0000 0 0x30000>;
2092 clocks = <&rpmhcc RPMH_CXO_CLK>;
2093 #clock-cells = <1>;
2094 #reset-cells = <1>;
2095 };
2096
2097 gpu: gpu@3d00000 {
2098 compatible = "qcom,adreno-43050a01", "qcom,adreno";
2099 reg = <0x0 0x03d00000 0x0 0x40000>,
2100 <0x0 0x03d9e000 0x0 0x1000>,
2101 <0x0 0x03d61000 0x0 0x800>;
2102 reg-names = "kgsl_3d0_reg_memory",
2103 "cx_mem",
2104 "cx_dbgc";
2105
2106 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2107
2108 iommus = <&adreno_smmu 0 0x0>,
2109 <&adreno_smmu 1 0x0>;
2110
2111 operating-points-v2 = <&gpu_opp_table>;
2112
2113 qcom,gmu = <&gmu>;
2114 #cooling-cells = <2>;
2115
2116 status = "disabled";
2117
2118 zap-shader {
2119 memory-region = <&gpu_micro_code_mem>;
2120 };
2121
2122 /* Speedbin needs more work on A740+, keep only lower freqs */
2123 gpu_opp_table: opp-table {
2124 compatible = "operating-points-v2";
2125
2126 opp-680000000 {
2127 opp-hz = /bits/ 64 <680000000>;
2128 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2129 };
2130
2131 opp-615000000 {
2132 opp-hz = /bits/ 64 <615000000>;
2133 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2134 };
2135
2136 opp-550000000 {
2137 opp-hz = /bits/ 64 <550000000>;
2138 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2139 };
2140
2141 opp-475000000 {
2142 opp-hz = /bits/ 64 <475000000>;
2143 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2144 };
2145
2146 opp-401000000 {
2147 opp-hz = /bits/ 64 <401000000>;
2148 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2149 };
2150
2151 opp-348000000 {
2152 opp-hz = /bits/ 64 <348000000>;
2153 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2154 };
2155
2156 opp-295000000 {
2157 opp-hz = /bits/ 64 <295000000>;
2158 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2159 };
2160
2161 opp-220000000 {
2162 opp-hz = /bits/ 64 <220000000>;
2163 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2164 };
2165 };
2166 };
2167
2168 gmu: gmu@3d6a000 {
2169 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
2170 reg = <0x0 0x03d6a000 0x0 0x35000>,
2171 <0x0 0x03d50000 0x0 0x10000>,
2172 <0x0 0x0b280000 0x0 0x10000>;
2173 reg-names = "gmu", "rscc", "gmu_pdc";
2174
2175 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2176 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2177 interrupt-names = "hfi", "gmu";
2178
2179 clocks = <&gpucc GPU_CC_AHB_CLK>,
2180 <&gpucc GPU_CC_CX_GMU_CLK>,
2181 <&gpucc GPU_CC_CXO_CLK>,
2182 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2183 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2184 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2185 <&gpucc GPU_CC_DEMET_CLK>;
2186 clock-names = "ahb",
2187 "gmu",
2188 "cxo",
2189 "axi",
2190 "memnoc",
2191 "hub",
2192 "demet";
2193
2194 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2195 <&gpucc GPU_CC_GX_GDSC>;
2196 power-domain-names = "cx",
2197 "gx";
2198
2199 iommus = <&adreno_smmu 5 0x0>;
2200
2201 qcom,qmp = <&aoss_qmp>;
2202
2203 operating-points-v2 = <&gmu_opp_table>;
2204
2205 gmu_opp_table: opp-table {
2206 compatible = "operating-points-v2";
2207
2208 opp-500000000 {
2209 opp-hz = /bits/ 64 <500000000>;
2210 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2211 };
2212
2213 opp-200000000 {
2214 opp-hz = /bits/ 64 <200000000>;
2215 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2216 };
2217 };
2218 };
2219
2220 gpucc: clock-controller@3d90000 {
2221 compatible = "qcom,sm8550-gpucc";
2222 reg = <0 0x03d90000 0 0xa000>;
2223 clocks = <&bi_tcxo_div2>,
2224 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2225 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2226 #clock-cells = <1>;
2227 #reset-cells = <1>;
2228 #power-domain-cells = <1>;
2229 };
2230
2231 adreno_smmu: iommu@3da0000 {
2232 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu",
2233 "qcom,smmu-500", "arm,mmu-500";
2234 reg = <0x0 0x03da0000 0x0 0x40000>;
2235 #iommu-cells = <2>;
2236 #global-interrupts = <1>;
2237 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2238 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>,
2239 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2240 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2241 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2242 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2243 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2244 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2245 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2246 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2247 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2248 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2249 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2250 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
2253 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2254 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
2255 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
2256 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
2257 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
2258 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
2259 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
2260 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
2261 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
2262 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
2263 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2264 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2265 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2266 <&gpucc GPU_CC_AHB_CLK>;
2267 clock-names = "hlos",
2268 "bus",
2269 "iface",
2270 "ahb";
2271 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2272 dma-coherent;
2273 };
2274
2275 ipa: ipa@3f40000 {
2276 compatible = "qcom,sm8550-ipa";
2277
2278 iommus = <&apps_smmu 0x4a0 0x0>,
2279 <&apps_smmu 0x4a2 0x0>;
2280 reg = <0 0x3f40000 0 0x10000>,
2281 <0 0x3f50000 0 0x5000>,
2282 <0 0x3e04000 0 0xfc000>;
2283 reg-names = "ipa-reg",
2284 "ipa-shared",
2285 "gsi";
2286
2287 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2288 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2289 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2290 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2291 interrupt-names = "ipa",
2292 "gsi",
2293 "ipa-clock-query",
2294 "ipa-setup-ready";
2295
2296 clocks = <&rpmhcc RPMH_IPA_CLK>;
2297 clock-names = "core";
2298
2299 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2300 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2301 interconnect-names = "memory",
2302 "config";
2303
2304 qcom,qmp = <&aoss_qmp>;
2305
2306 qcom,smem-states = <&ipa_smp2p_out 0>,
2307 <&ipa_smp2p_out 1>;
2308 qcom,smem-state-names = "ipa-clock-enabled-valid",
2309 "ipa-clock-enabled";
2310
2311 status = "disabled";
2312 };
2313
2314 remoteproc_mpss: remoteproc@4080000 {
2315 compatible = "qcom,sm8550-mpss-pas";
2316 reg = <0x0 0x04080000 0x0 0x4040>;
2317
2318 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2319 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2320 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2321 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2322 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2323 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2324 interrupt-names = "wdog", "fatal", "ready", "handover",
2325 "stop-ack", "shutdown-ack";
2326
2327 clocks = <&rpmhcc RPMH_CXO_CLK>;
2328 clock-names = "xo";
2329
2330 power-domains = <&rpmhpd RPMHPD_CX>,
2331 <&rpmhpd RPMHPD_MSS>;
2332 power-domain-names = "cx", "mss";
2333
2334 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2335
2336 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2337
2338 qcom,qmp = <&aoss_qmp>;
2339
2340 qcom,smem-states = <&smp2p_modem_out 0>;
2341 qcom,smem-state-names = "stop";
2342
2343 status = "disabled";
2344
2345 glink-edge {
2346 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2347 IPCC_MPROC_SIGNAL_GLINK_QMP
2348 IRQ_TYPE_EDGE_RISING>;
2349 mboxes = <&ipcc IPCC_CLIENT_MPSS
2350 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2351 label = "mpss";
2352 qcom,remote-pid = <1>;
2353 };
2354 };
2355
2356 lpass_wsa2macro: codec@6aa0000 {
2357 compatible = "qcom,sm8550-lpass-wsa-macro";
2358 reg = <0 0x06aa0000 0 0x1000>;
2359 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2360 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2361 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2362 <&lpass_vamacro>;
2363 clock-names = "mclk", "macro", "dcodec", "fsgen";
2364
2365 #clock-cells = <0>;
2366 clock-output-names = "wsa2-mclk";
2367 #sound-dai-cells = <1>;
2368 };
2369
2370 swr3: soundwire@6ab0000 {
2371 compatible = "qcom,soundwire-v2.0.0";
2372 reg = <0 0x06ab0000 0 0x10000>;
2373 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&lpass_wsa2macro>;
2375 clock-names = "iface";
2376 label = "WSA2";
2377
2378 pinctrl-0 = <&wsa2_swr_active>;
2379 pinctrl-names = "default";
2380
2381 qcom,din-ports = <4>;
2382 qcom,dout-ports = <9>;
2383
2384 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2385 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2386 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2387 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2388 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2389 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2390 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2391 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2392 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2393
2394 #address-cells = <2>;
2395 #size-cells = <0>;
2396 #sound-dai-cells = <1>;
2397 status = "disabled";
2398 };
2399
2400 lpass_rxmacro: codec@6ac0000 {
2401 compatible = "qcom,sm8550-lpass-rx-macro";
2402 reg = <0 0x06ac0000 0 0x1000>;
2403 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2404 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2405 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2406 <&lpass_vamacro>;
2407 clock-names = "mclk", "macro", "dcodec", "fsgen";
2408
2409 #clock-cells = <0>;
2410 clock-output-names = "mclk";
2411 #sound-dai-cells = <1>;
2412 };
2413
2414 swr1: soundwire@6ad0000 {
2415 compatible = "qcom,soundwire-v2.0.0";
2416 reg = <0 0x06ad0000 0 0x10000>;
2417 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2418 clocks = <&lpass_rxmacro>;
2419 clock-names = "iface";
2420 label = "RX";
2421
2422 pinctrl-0 = <&rx_swr_active>;
2423 pinctrl-names = "default";
2424
2425 qcom,din-ports = <1>;
2426 qcom,dout-ports = <11>;
2427
2428 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
2429 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2430 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2431 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2432 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2433 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
2434 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2435 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2436 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2437
2438 #address-cells = <2>;
2439 #size-cells = <0>;
2440 #sound-dai-cells = <1>;
2441 status = "disabled";
2442 };
2443
2444 lpass_txmacro: codec@6ae0000 {
2445 compatible = "qcom,sm8550-lpass-tx-macro";
2446 reg = <0 0x06ae0000 0 0x1000>;
2447 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2448 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2449 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2450 <&lpass_vamacro>;
2451 clock-names = "mclk", "macro", "dcodec", "fsgen";
2452
2453 #clock-cells = <0>;
2454 clock-output-names = "mclk";
2455 #sound-dai-cells = <1>;
2456 };
2457
2458 lpass_wsamacro: codec@6b00000 {
2459 compatible = "qcom,sm8550-lpass-wsa-macro";
2460 reg = <0 0x06b00000 0 0x1000>;
2461 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2462 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2463 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2464 <&lpass_vamacro>;
2465 clock-names = "mclk", "macro", "dcodec", "fsgen";
2466
2467 #clock-cells = <0>;
2468 clock-output-names = "mclk";
2469 #sound-dai-cells = <1>;
2470 };
2471
2472 swr0: soundwire@6b10000 {
2473 compatible = "qcom,soundwire-v2.0.0";
2474 reg = <0 0x06b10000 0 0x10000>;
2475 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2476 clocks = <&lpass_wsamacro>;
2477 clock-names = "iface";
2478 label = "WSA";
2479
2480 pinctrl-0 = <&wsa_swr_active>;
2481 pinctrl-names = "default";
2482
2483 qcom,din-ports = <4>;
2484 qcom,dout-ports = <9>;
2485
2486 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2487 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2488 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2489 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2490 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2491 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2492 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2493 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2494 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2495
2496 #address-cells = <2>;
2497 #size-cells = <0>;
2498 #sound-dai-cells = <1>;
2499 status = "disabled";
2500 };
2501
2502 swr2: soundwire@6d30000 {
2503 compatible = "qcom,soundwire-v2.0.0";
2504 reg = <0 0x06d30000 0 0x10000>;
2505 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2506 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2507 interrupt-names = "core", "wakeup";
2508 clocks = <&lpass_txmacro>;
2509 clock-names = "iface";
2510 label = "TX";
2511
2512 pinctrl-0 = <&tx_swr_active>;
2513 pinctrl-names = "default";
2514
2515 qcom,din-ports = <4>;
2516 qcom,dout-ports = <0>;
2517 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2518 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2519 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2520 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2521 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2522 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2523 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2524 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2525 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2526
2527 #address-cells = <2>;
2528 #size-cells = <0>;
2529 #sound-dai-cells = <1>;
2530 status = "disabled";
2531 };
2532
2533 lpass_vamacro: codec@6d44000 {
2534 compatible = "qcom,sm8550-lpass-va-macro";
2535 reg = <0 0x06d44000 0 0x1000>;
2536 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2537 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2538 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2539 clock-names = "mclk", "macro", "dcodec";
2540
2541 #clock-cells = <0>;
2542 clock-output-names = "fsgen";
2543 #sound-dai-cells = <1>;
2544 };
2545
2546 lpass_tlmm: pinctrl@6e80000 {
2547 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2548 reg = <0 0x06e80000 0 0x20000>,
2549 <0 0x07250000 0 0x10000>;
2550 gpio-controller;
2551 #gpio-cells = <2>;
2552 gpio-ranges = <&lpass_tlmm 0 0 23>;
2553
2554 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2555 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2556 clock-names = "core", "audio";
2557
2558 tx_swr_active: tx-swr-active-state {
2559 clk-pins {
2560 pins = "gpio0";
2561 function = "swr_tx_clk";
2562 drive-strength = <2>;
2563 slew-rate = <1>;
2564 bias-disable;
2565 };
2566
2567 data-pins {
2568 pins = "gpio1", "gpio2", "gpio14";
2569 function = "swr_tx_data";
2570 drive-strength = <2>;
2571 slew-rate = <1>;
2572 bias-bus-hold;
2573 };
2574 };
2575
2576 rx_swr_active: rx-swr-active-state {
2577 clk-pins {
2578 pins = "gpio3";
2579 function = "swr_rx_clk";
2580 drive-strength = <2>;
2581 slew-rate = <1>;
2582 bias-disable;
2583 };
2584
2585 data-pins {
2586 pins = "gpio4", "gpio5";
2587 function = "swr_rx_data";
2588 drive-strength = <2>;
2589 slew-rate = <1>;
2590 bias-bus-hold;
2591 };
2592 };
2593
2594 dmic01_default: dmic01-default-state {
2595 clk-pins {
2596 pins = "gpio6";
2597 function = "dmic1_clk";
2598 drive-strength = <8>;
2599 output-high;
2600 };
2601
2602 data-pins {
2603 pins = "gpio7";
2604 function = "dmic1_data";
2605 drive-strength = <8>;
2606 input-enable;
2607 };
2608 };
2609
2610 dmic23_default: dmic23-default-state {
2611 clk-pins {
2612 pins = "gpio8";
2613 function = "dmic2_clk";
2614 drive-strength = <8>;
2615 output-high;
2616 };
2617
2618 data-pins {
2619 pins = "gpio9";
2620 function = "dmic2_data";
2621 drive-strength = <8>;
2622 input-enable;
2623 };
2624 };
2625
2626 wsa_swr_active: wsa-swr-active-state {
2627 clk-pins {
2628 pins = "gpio10";
2629 function = "wsa_swr_clk";
2630 drive-strength = <2>;
2631 slew-rate = <1>;
2632 bias-disable;
2633 };
2634
2635 data-pins {
2636 pins = "gpio11";
2637 function = "wsa_swr_data";
2638 drive-strength = <2>;
2639 slew-rate = <1>;
2640 bias-bus-hold;
2641 };
2642 };
2643
2644 wsa2_swr_active: wsa2-swr-active-state {
2645 clk-pins {
2646 pins = "gpio15";
2647 function = "wsa2_swr_clk";
2648 drive-strength = <2>;
2649 slew-rate = <1>;
2650 bias-disable;
2651 };
2652
2653 data-pins {
2654 pins = "gpio16";
2655 function = "wsa2_swr_data";
2656 drive-strength = <2>;
2657 slew-rate = <1>;
2658 bias-bus-hold;
2659 };
2660 };
2661 };
2662
2663 lpass_lpiaon_noc: interconnect@7400000 {
2664 compatible = "qcom,sm8550-lpass-lpiaon-noc";
2665 reg = <0 0x07400000 0 0x19080>;
2666 #interconnect-cells = <2>;
2667 qcom,bcm-voters = <&apps_bcm_voter>;
2668 };
2669
2670 lpass_lpicx_noc: interconnect@7430000 {
2671 compatible = "qcom,sm8550-lpass-lpicx-noc";
2672 reg = <0 0x07430000 0 0x3a200>;
2673 #interconnect-cells = <2>;
2674 qcom,bcm-voters = <&apps_bcm_voter>;
2675 };
2676
2677 lpass_ag_noc: interconnect@7e40000 {
2678 compatible = "qcom,sm8550-lpass-ag-noc";
2679 reg = <0 0x07e40000 0 0xe080>;
2680 #interconnect-cells = <2>;
2681 qcom,bcm-voters = <&apps_bcm_voter>;
2682 };
2683
2684 sdhc_2: mmc@8804000 {
2685 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2686 reg = <0 0x08804000 0 0x1000>;
2687
2688 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
2689 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2690 interrupt-names = "hc_irq", "pwr_irq";
2691
2692 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2693 <&gcc GCC_SDCC2_APPS_CLK>,
2694 <&rpmhcc RPMH_CXO_CLK>;
2695 clock-names = "iface", "core", "xo";
2696 iommus = <&apps_smmu 0x540 0>;
2697 qcom,dll-config = <0x0007642c>;
2698 qcom,ddr-config = <0x80040868>;
2699 power-domains = <&rpmhpd RPMHPD_CX>;
2700 operating-points-v2 = <&sdhc2_opp_table>;
2701
2702 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2703 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2704 interconnect-names = "sdhc-ddr", "cpu-sdhc";
2705 bus-width = <4>;
2706 dma-coherent;
2707
2708 /* Forbid SDR104/SDR50 - broken hw! */
2709 sdhci-caps-mask = <0x3 0>;
2710
2711 status = "disabled";
2712
2713 sdhc2_opp_table: opp-table {
2714 compatible = "operating-points-v2";
2715
2716 opp-19200000 {
2717 opp-hz = /bits/ 64 <19200000>;
2718 required-opps = <&rpmhpd_opp_min_svs>;
2719 };
2720
2721 opp-50000000 {
2722 opp-hz = /bits/ 64 <50000000>;
2723 required-opps = <&rpmhpd_opp_low_svs>;
2724 };
2725
2726 opp-100000000 {
2727 opp-hz = /bits/ 64 <100000000>;
2728 required-opps = <&rpmhpd_opp_svs>;
2729 };
2730
2731 opp-202000000 {
2732 opp-hz = /bits/ 64 <202000000>;
2733 required-opps = <&rpmhpd_opp_svs_l1>;
2734 };
2735 };
2736 };
2737
2738 videocc: clock-controller@aaf0000 {
2739 compatible = "qcom,sm8550-videocc";
2740 reg = <0 0x0aaf0000 0 0x10000>;
2741 clocks = <&bi_tcxo_div2>,
2742 <&gcc GCC_VIDEO_AHB_CLK>;
2743 power-domains = <&rpmhpd RPMHPD_MMCX>;
2744 required-opps = <&rpmhpd_opp_low_svs>;
2745 #clock-cells = <1>;
2746 #reset-cells = <1>;
2747 #power-domain-cells = <1>;
2748 };
2749
2750 camcc: clock-controller@ade0000 {
2751 compatible = "qcom,sm8550-camcc";
2752 reg = <0 0x0ade0000 0 0x20000>;
2753 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
2754 <&bi_tcxo_div2>,
2755 <&bi_tcxo_ao_div2>,
2756 <&sleep_clk>;
2757 power-domains = <&rpmhpd SM8550_MMCX>;
2758 required-opps = <&rpmhpd_opp_low_svs>;
2759 #clock-cells = <1>;
2760 #reset-cells = <1>;
2761 #power-domain-cells = <1>;
2762 };
2763
2764 mdss: display-subsystem@ae00000 {
2765 compatible = "qcom,sm8550-mdss";
2766 reg = <0 0x0ae00000 0 0x1000>;
2767 reg-names = "mdss";
2768
2769 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2770 interrupt-controller;
2771 #interrupt-cells = <1>;
2772
2773 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2774 <&gcc GCC_DISP_AHB_CLK>,
2775 <&gcc GCC_DISP_HF_AXI_CLK>,
2776 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2777
2778 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2779
2780 power-domains = <&dispcc MDSS_GDSC>;
2781
2782 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
2783 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2784 interconnect-names = "mdp0-mem", "mdp1-mem";
2785
2786 iommus = <&apps_smmu 0x1c00 0x2>;
2787
2788 #address-cells = <2>;
2789 #size-cells = <2>;
2790 ranges;
2791
2792 status = "disabled";
2793
2794 mdss_mdp: display-controller@ae01000 {
2795 compatible = "qcom,sm8550-dpu";
2796 reg = <0 0x0ae01000 0 0x8f000>,
2797 <0 0x0aeb0000 0 0x2008>;
2798 reg-names = "mdp", "vbif";
2799
2800 interrupt-parent = <&mdss>;
2801 interrupts = <0>;
2802
2803 clocks = <&gcc GCC_DISP_AHB_CLK>,
2804 <&gcc GCC_DISP_HF_AXI_CLK>,
2805 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2806 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2807 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2808 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2809 clock-names = "bus",
2810 "nrt_bus",
2811 "iface",
2812 "lut",
2813 "core",
2814 "vsync";
2815
2816 power-domains = <&rpmhpd RPMHPD_MMCX>;
2817
2818 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2819 assigned-clock-rates = <19200000>;
2820
2821 operating-points-v2 = <&mdp_opp_table>;
2822
2823 ports {
2824 #address-cells = <1>;
2825 #size-cells = <0>;
2826
2827 port@0 {
2828 reg = <0>;
2829 dpu_intf1_out: endpoint {
2830 remote-endpoint = <&mdss_dsi0_in>;
2831 };
2832 };
2833
2834 port@1 {
2835 reg = <1>;
2836 dpu_intf2_out: endpoint {
2837 remote-endpoint = <&mdss_dsi1_in>;
2838 };
2839 };
2840
2841 port@2 {
2842 reg = <2>;
2843 dpu_intf0_out: endpoint {
2844 remote-endpoint = <&mdss_dp0_in>;
2845 };
2846 };
2847 };
2848
2849 mdp_opp_table: opp-table {
2850 compatible = "operating-points-v2";
2851
2852 opp-200000000 {
2853 opp-hz = /bits/ 64 <200000000>;
2854 required-opps = <&rpmhpd_opp_low_svs>;
2855 };
2856
2857 opp-325000000 {
2858 opp-hz = /bits/ 64 <325000000>;
2859 required-opps = <&rpmhpd_opp_svs>;
2860 };
2861
2862 opp-375000000 {
2863 opp-hz = /bits/ 64 <375000000>;
2864 required-opps = <&rpmhpd_opp_svs_l1>;
2865 };
2866
2867 opp-514000000 {
2868 opp-hz = /bits/ 64 <514000000>;
2869 required-opps = <&rpmhpd_opp_nom>;
2870 };
2871 };
2872 };
2873
2874 mdss_dp0: displayport-controller@ae90000 {
2875 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
2876 reg = <0 0xae90000 0 0x200>,
2877 <0 0xae90200 0 0x200>,
2878 <0 0xae90400 0 0xc00>,
2879 <0 0xae91000 0 0x400>,
2880 <0 0xae91400 0 0x400>;
2881 interrupt-parent = <&mdss>;
2882 interrupts = <12>;
2883 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2884 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
2885 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
2886 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
2887 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
2888 clock-names = "core_iface",
2889 "core_aux",
2890 "ctrl_link",
2891 "ctrl_link_iface",
2892 "stream_pixel";
2893
2894 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2895 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
2896 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2897 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2898
2899 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
2900 phy-names = "dp";
2901
2902 #sound-dai-cells = <0>;
2903
2904 operating-points-v2 = <&dp_opp_table>;
2905 power-domains = <&rpmhpd RPMHPD_MMCX>;
2906
2907 status = "disabled";
2908
2909 ports {
2910 #address-cells = <1>;
2911 #size-cells = <0>;
2912
2913 port@0 {
2914 reg = <0>;
2915 mdss_dp0_in: endpoint {
2916 remote-endpoint = <&dpu_intf0_out>;
2917 };
2918 };
2919
2920 port@1 {
2921 reg = <1>;
2922 mdss_dp0_out: endpoint {
2923 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
2924 };
2925 };
2926 };
2927
2928 dp_opp_table: opp-table {
2929 compatible = "operating-points-v2";
2930
2931 opp-162000000 {
2932 opp-hz = /bits/ 64 <162000000>;
2933 required-opps = <&rpmhpd_opp_low_svs_d1>;
2934 };
2935
2936 opp-270000000 {
2937 opp-hz = /bits/ 64 <270000000>;
2938 required-opps = <&rpmhpd_opp_low_svs>;
2939 };
2940
2941 opp-540000000 {
2942 opp-hz = /bits/ 64 <540000000>;
2943 required-opps = <&rpmhpd_opp_svs_l1>;
2944 };
2945
2946 opp-810000000 {
2947 opp-hz = /bits/ 64 <810000000>;
2948 required-opps = <&rpmhpd_opp_nom>;
2949 };
2950 };
2951 };
2952
2953 mdss_dsi0: dsi@ae94000 {
2954 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2955 reg = <0 0x0ae94000 0 0x400>;
2956 reg-names = "dsi_ctrl";
2957
2958 interrupt-parent = <&mdss>;
2959 interrupts = <4>;
2960
2961 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2962 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2963 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2964 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2965 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2966 <&gcc GCC_DISP_HF_AXI_CLK>;
2967 clock-names = "byte",
2968 "byte_intf",
2969 "pixel",
2970 "core",
2971 "iface",
2972 "bus";
2973
2974 power-domains = <&rpmhpd RPMHPD_MMCX>;
2975
2976 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2977 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2978 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2979 <&mdss_dsi0_phy 1>;
2980
2981 operating-points-v2 = <&mdss_dsi_opp_table>;
2982
2983 phys = <&mdss_dsi0_phy>;
2984 phy-names = "dsi";
2985
2986 #address-cells = <1>;
2987 #size-cells = <0>;
2988
2989 status = "disabled";
2990
2991 ports {
2992 #address-cells = <1>;
2993 #size-cells = <0>;
2994
2995 port@0 {
2996 reg = <0>;
2997 mdss_dsi0_in: endpoint {
2998 remote-endpoint = <&dpu_intf1_out>;
2999 };
3000 };
3001
3002 port@1 {
3003 reg = <1>;
3004 mdss_dsi0_out: endpoint {
3005 };
3006 };
3007 };
3008
3009 mdss_dsi_opp_table: opp-table {
3010 compatible = "operating-points-v2";
3011
3012 opp-187500000 {
3013 opp-hz = /bits/ 64 <187500000>;
3014 required-opps = <&rpmhpd_opp_low_svs>;
3015 };
3016
3017 opp-300000000 {
3018 opp-hz = /bits/ 64 <300000000>;
3019 required-opps = <&rpmhpd_opp_svs>;
3020 };
3021
3022 opp-358000000 {
3023 opp-hz = /bits/ 64 <358000000>;
3024 required-opps = <&rpmhpd_opp_svs_l1>;
3025 };
3026 };
3027 };
3028
3029 mdss_dsi0_phy: phy@ae95000 {
3030 compatible = "qcom,sm8550-dsi-phy-4nm";
3031 reg = <0 0x0ae95000 0 0x200>,
3032 <0 0x0ae95200 0 0x280>,
3033 <0 0x0ae95500 0 0x400>;
3034 reg-names = "dsi_phy",
3035 "dsi_phy_lane",
3036 "dsi_pll";
3037
3038 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3039 <&rpmhcc RPMH_CXO_CLK>;
3040 clock-names = "iface", "ref";
3041
3042 #clock-cells = <1>;
3043 #phy-cells = <0>;
3044
3045 status = "disabled";
3046 };
3047
3048 mdss_dsi1: dsi@ae96000 {
3049 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3050 reg = <0 0x0ae96000 0 0x400>;
3051 reg-names = "dsi_ctrl";
3052
3053 interrupt-parent = <&mdss>;
3054 interrupts = <5>;
3055
3056 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3057 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3058 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3059 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3060 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3061 <&gcc GCC_DISP_HF_AXI_CLK>;
3062 clock-names = "byte",
3063 "byte_intf",
3064 "pixel",
3065 "core",
3066 "iface",
3067 "bus";
3068
3069 power-domains = <&rpmhpd RPMHPD_MMCX>;
3070
3071 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3072 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3073 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3074 <&mdss_dsi1_phy 1>;
3075
3076 operating-points-v2 = <&mdss_dsi_opp_table>;
3077
3078 phys = <&mdss_dsi1_phy>;
3079 phy-names = "dsi";
3080
3081 #address-cells = <1>;
3082 #size-cells = <0>;
3083
3084 status = "disabled";
3085
3086 ports {
3087 #address-cells = <1>;
3088 #size-cells = <0>;
3089
3090 port@0 {
3091 reg = <0>;
3092 mdss_dsi1_in: endpoint {
3093 remote-endpoint = <&dpu_intf2_out>;
3094 };
3095 };
3096
3097 port@1 {
3098 reg = <1>;
3099 mdss_dsi1_out: endpoint {
3100 };
3101 };
3102 };
3103 };
3104
3105 mdss_dsi1_phy: phy@ae97000 {
3106 compatible = "qcom,sm8550-dsi-phy-4nm";
3107 reg = <0 0x0ae97000 0 0x200>,
3108 <0 0x0ae97200 0 0x280>,
3109 <0 0x0ae97500 0 0x400>;
3110 reg-names = "dsi_phy",
3111 "dsi_phy_lane",
3112 "dsi_pll";
3113
3114 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3115 <&rpmhcc RPMH_CXO_CLK>;
3116 clock-names = "iface", "ref";
3117
3118 #clock-cells = <1>;
3119 #phy-cells = <0>;
3120
3121 status = "disabled";
3122 };
3123 };
3124
3125 dispcc: clock-controller@af00000 {
3126 compatible = "qcom,sm8550-dispcc";
3127 reg = <0 0x0af00000 0 0x20000>;
3128 clocks = <&bi_tcxo_div2>,
3129 <&bi_tcxo_ao_div2>,
3130 <&gcc GCC_DISP_AHB_CLK>,
3131 <&sleep_clk>,
3132 <&mdss_dsi0_phy 0>,
3133 <&mdss_dsi0_phy 1>,
3134 <&mdss_dsi1_phy 0>,
3135 <&mdss_dsi1_phy 1>,
3136 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3137 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3138 <0>, /* dp1 */
3139 <0>,
3140 <0>, /* dp2 */
3141 <0>,
3142 <0>, /* dp3 */
3143 <0>;
3144 power-domains = <&rpmhpd RPMHPD_MMCX>;
3145 required-opps = <&rpmhpd_opp_low_svs>;
3146 #clock-cells = <1>;
3147 #reset-cells = <1>;
3148 #power-domain-cells = <1>;
3149 };
3150
3151 usb_1_hsphy: phy@88e3000 {
3152 compatible = "qcom,sm8550-snps-eusb2-phy";
3153 reg = <0x0 0x088e3000 0x0 0x154>;
3154 #phy-cells = <0>;
3155
3156 clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
3157 clock-names = "ref";
3158
3159 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3160
3161 status = "disabled";
3162 };
3163
3164 usb_dp_qmpphy: phy@88e8000 {
3165 compatible = "qcom,sm8550-qmp-usb3-dp-phy";
3166 reg = <0x0 0x088e8000 0x0 0x3000>;
3167
3168 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3169 <&rpmhcc RPMH_CXO_CLK>,
3170 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3171 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3172 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3173
3174 power-domains = <&gcc USB3_PHY_GDSC>;
3175
3176 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3177 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
3178 reset-names = "phy", "common";
3179
3180 #clock-cells = <1>;
3181 #phy-cells = <1>;
3182
3183 orientation-switch;
3184
3185 status = "disabled";
3186
3187 ports {
3188 #address-cells = <1>;
3189 #size-cells = <0>;
3190
3191 port@0 {
3192 reg = <0>;
3193
3194 usb_dp_qmpphy_out: endpoint {
3195 };
3196 };
3197
3198 port@1 {
3199 reg = <1>;
3200
3201 usb_dp_qmpphy_usb_ss_in: endpoint {
3202 remote-endpoint = <&usb_1_dwc3_ss>;
3203 };
3204 };
3205
3206 port@2 {
3207 reg = <2>;
3208
3209 usb_dp_qmpphy_dp_in: endpoint {
3210 remote-endpoint = <&mdss_dp0_out>;
3211 };
3212 };
3213 };
3214 };
3215
3216 usb_1: usb@a6f8800 {
3217 compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
3218 reg = <0x0 0x0a6f8800 0x0 0x400>;
3219 #address-cells = <2>;
3220 #size-cells = <2>;
3221 ranges;
3222
3223 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3224 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3225 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3226 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3227 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3228 <&tcsr TCSR_USB3_CLKREF_EN>;
3229 clock-names = "cfg_noc",
3230 "core",
3231 "iface",
3232 "sleep",
3233 "mock_utmi",
3234 "xo";
3235
3236 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3237 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3238 assigned-clock-rates = <19200000>, <200000000>;
3239
3240 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3241 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3242 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3243 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3244 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
3245 interrupt-names = "pwr_event",
3246 "hs_phy_irq",
3247 "dp_hs_phy_irq",
3248 "dm_hs_phy_irq",
3249 "ss_phy_irq";
3250
3251 power-domains = <&gcc USB30_PRIM_GDSC>;
3252 required-opps = <&rpmhpd_opp_nom>;
3253
3254 resets = <&gcc GCC_USB30_PRIM_BCR>;
3255
3256 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3257 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3258 interconnect-names = "usb-ddr", "apps-usb";
3259
3260 status = "disabled";
3261
3262 usb_1_dwc3: usb@a600000 {
3263 compatible = "snps,dwc3";
3264 reg = <0x0 0x0a600000 0x0 0xcd00>;
3265 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3266 iommus = <&apps_smmu 0x40 0x0>;
3267 phys = <&usb_1_hsphy>,
3268 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
3269 phy-names = "usb2-phy", "usb3-phy";
3270 snps,hird-threshold = /bits/ 8 <0x0>;
3271 snps,usb2-gadget-lpm-disable;
3272 snps,dis_u2_susphy_quirk;
3273 snps,dis_enblslpm_quirk;
3274 snps,dis-u1-entry-quirk;
3275 snps,dis-u2-entry-quirk;
3276 snps,is-utmi-l1-suspend;
3277 snps,usb3_lpm_capable;
3278 snps,usb2-lpm-disable;
3279 snps,has-lpm-erratum;
3280 tx-fifo-resize;
3281 dma-coherent;
3282 usb-role-switch;
3283
3284 ports {
3285 #address-cells = <1>;
3286 #size-cells = <0>;
3287
3288 port@0 {
3289 reg = <0>;
3290
3291 usb_1_dwc3_hs: endpoint {
3292 };
3293 };
3294
3295 port@1 {
3296 reg = <1>;
3297
3298 usb_1_dwc3_ss: endpoint {
3299 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
3300 };
3301 };
3302 };
3303 };
3304 };
3305
3306 pdc: interrupt-controller@b220000 {
3307 compatible = "qcom,sm8550-pdc", "qcom,pdc";
3308 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3309 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3310 <125 63 1>, <126 716 12>,
3311 <138 251 5>;
3312 #interrupt-cells = <2>;
3313 interrupt-parent = <&intc>;
3314 interrupt-controller;
3315 };
3316
3317 tsens0: thermal-sensor@c271000 {
3318 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3319 reg = <0 0x0c271000 0 0x1000>, /* TM */
3320 <0 0x0c222000 0 0x1000>; /* SROT */
3321 #qcom,sensors = <16>;
3322 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3323 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
3324 interrupt-names = "uplow", "critical";
3325 #thermal-sensor-cells = <1>;
3326 };
3327
3328 tsens1: thermal-sensor@c272000 {
3329 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3330 reg = <0 0x0c272000 0 0x1000>, /* TM */
3331 <0 0x0c223000 0 0x1000>; /* SROT */
3332 #qcom,sensors = <16>;
3333 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3334 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
3335 interrupt-names = "uplow", "critical";
3336 #thermal-sensor-cells = <1>;
3337 };
3338
3339 tsens2: thermal-sensor@c273000 {
3340 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3341 reg = <0 0x0c273000 0 0x1000>, /* TM */
3342 <0 0x0c224000 0 0x1000>; /* SROT */
3343 #qcom,sensors = <16>;
3344 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
3345 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
3346 interrupt-names = "uplow", "critical";
3347 #thermal-sensor-cells = <1>;
3348 };
3349
3350 aoss_qmp: power-management@c300000 {
3351 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
3352 reg = <0 0x0c300000 0 0x400>;
3353 interrupt-parent = <&ipcc>;
3354 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3355 IRQ_TYPE_EDGE_RISING>;
3356 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3357
3358 #clock-cells = <0>;
3359 };
3360
3361 sram@c3f0000 {
3362 compatible = "qcom,rpmh-stats";
3363 reg = <0 0x0c3f0000 0 0x400>;
3364 };
3365
3366 spmi_bus: spmi@c400000 {
3367 compatible = "qcom,spmi-pmic-arb";
3368 reg = <0 0x0c400000 0 0x3000>,
3369 <0 0x0c500000 0 0x400000>,
3370 <0 0x0c440000 0 0x80000>,
3371 <0 0x0c4c0000 0 0x20000>,
3372 <0 0x0c42d000 0 0x4000>;
3373 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3374 interrupt-names = "periph_irq";
3375 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3376 qcom,ee = <0>;
3377 qcom,channel = <0>;
3378 qcom,bus-id = <0>;
3379 #address-cells = <2>;
3380 #size-cells = <0>;
3381 interrupt-controller;
3382 #interrupt-cells = <4>;
3383 };
3384
3385 tlmm: pinctrl@f100000 {
3386 compatible = "qcom,sm8550-tlmm";
3387 reg = <0 0x0f100000 0 0x300000>;
3388 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3389 gpio-controller;
3390 #gpio-cells = <2>;
3391 interrupt-controller;
3392 #interrupt-cells = <2>;
3393 gpio-ranges = <&tlmm 0 0 211>;
3394 wakeup-parent = <&pdc>;
3395
3396 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3397 /* SDA, SCL */
3398 pins = "gpio16", "gpio17";
3399 function = "i2chub0_se0";
3400 drive-strength = <2>;
3401 bias-pull-up;
3402 };
3403
3404 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3405 /* SDA, SCL */
3406 pins = "gpio18", "gpio19";
3407 function = "i2chub0_se1";
3408 drive-strength = <2>;
3409 bias-pull-up;
3410 };
3411
3412 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3413 /* SDA, SCL */
3414 pins = "gpio20", "gpio21";
3415 function = "i2chub0_se2";
3416 drive-strength = <2>;
3417 bias-pull-up;
3418 };
3419
3420 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3421 /* SDA, SCL */
3422 pins = "gpio22", "gpio23";
3423 function = "i2chub0_se3";
3424 drive-strength = <2>;
3425 bias-pull-up;
3426 };
3427
3428 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3429 /* SDA, SCL */
3430 pins = "gpio4", "gpio5";
3431 function = "i2chub0_se4";
3432 drive-strength = <2>;
3433 bias-pull-up;
3434 };
3435
3436 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3437 /* SDA, SCL */
3438 pins = "gpio6", "gpio7";
3439 function = "i2chub0_se5";
3440 drive-strength = <2>;
3441 bias-pull-up;
3442 };
3443
3444 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3445 /* SDA, SCL */
3446 pins = "gpio8", "gpio9";
3447 function = "i2chub0_se6";
3448 drive-strength = <2>;
3449 bias-pull-up;
3450 };
3451
3452 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3453 /* SDA, SCL */
3454 pins = "gpio10", "gpio11";
3455 function = "i2chub0_se7";
3456 drive-strength = <2>;
3457 bias-pull-up;
3458 };
3459
3460 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3461 /* SDA, SCL */
3462 pins = "gpio206", "gpio207";
3463 function = "i2chub0_se8";
3464 drive-strength = <2>;
3465 bias-pull-up;
3466 };
3467
3468 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3469 /* SDA, SCL */
3470 pins = "gpio84", "gpio85";
3471 function = "i2chub0_se9";
3472 drive-strength = <2>;
3473 bias-pull-up;
3474 };
3475
3476 pcie0_default_state: pcie0-default-state {
3477 perst-pins {
3478 pins = "gpio94";
3479 function = "gpio";
3480 drive-strength = <2>;
3481 bias-pull-down;
3482 };
3483
3484 clkreq-pins {
3485 pins = "gpio95";
3486 function = "pcie0_clk_req_n";
3487 drive-strength = <2>;
3488 bias-pull-up;
3489 };
3490
3491 wake-pins {
3492 pins = "gpio96";
3493 function = "gpio";
3494 drive-strength = <2>;
3495 bias-pull-up;
3496 };
3497 };
3498
3499 pcie1_default_state: pcie1-default-state {
3500 perst-pins {
3501 pins = "gpio97";
3502 function = "gpio";
3503 drive-strength = <2>;
3504 bias-pull-down;
3505 };
3506
3507 clkreq-pins {
3508 pins = "gpio98";
3509 function = "pcie1_clk_req_n";
3510 drive-strength = <2>;
3511 bias-pull-up;
3512 };
3513
3514 wake-pins {
3515 pins = "gpio99";
3516 function = "gpio";
3517 drive-strength = <2>;
3518 bias-pull-up;
3519 };
3520 };
3521
3522 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3523 /* SDA, SCL */
3524 pins = "gpio28", "gpio29";
3525 function = "qup1_se0";
3526 drive-strength = <2>;
3527 bias-pull-up = <2200>;
3528 };
3529
3530 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3531 /* SDA, SCL */
3532 pins = "gpio32", "gpio33";
3533 function = "qup1_se1";
3534 drive-strength = <2>;
3535 bias-pull-up = <2200>;
3536 };
3537
3538 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3539 /* SDA, SCL */
3540 pins = "gpio36", "gpio37";
3541 function = "qup1_se2";
3542 drive-strength = <2>;
3543 bias-pull-up = <2200>;
3544 };
3545
3546 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3547 /* SDA, SCL */
3548 pins = "gpio40", "gpio41";
3549 function = "qup1_se3";
3550 drive-strength = <2>;
3551 bias-pull-up = <2200>;
3552 };
3553
3554 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3555 /* SDA, SCL */
3556 pins = "gpio44", "gpio45";
3557 function = "qup1_se4";
3558 drive-strength = <2>;
3559 bias-pull-up = <2200>;
3560 };
3561
3562 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3563 /* SDA, SCL */
3564 pins = "gpio52", "gpio53";
3565 function = "qup1_se5";
3566 drive-strength = <2>;
3567 bias-pull-up = <2200>;
3568 };
3569
3570 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3571 /* SDA, SCL */
3572 pins = "gpio48", "gpio49";
3573 function = "qup1_se6";
3574 drive-strength = <2>;
3575 bias-pull-up = <2200>;
3576 };
3577
3578 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3579 scl-pins {
3580 pins = "gpio57";
3581 function = "qup2_se0_l1_mira";
3582 drive-strength = <2>;
3583 bias-pull-up = <2200>;
3584 };
3585
3586 sda-pins {
3587 pins = "gpio56";
3588 function = "qup2_se0_l0_mira";
3589 drive-strength = <2>;
3590 bias-pull-up = <2200>;
3591 };
3592 };
3593
3594 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3595 /* SDA, SCL */
3596 pins = "gpio60", "gpio61";
3597 function = "qup2_se1";
3598 drive-strength = <2>;
3599 bias-pull-up = <2200>;
3600 };
3601
3602 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3603 /* SDA, SCL */
3604 pins = "gpio64", "gpio65";
3605 function = "qup2_se2";
3606 drive-strength = <2>;
3607 bias-pull-up = <2200>;
3608 };
3609
3610 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3611 /* SDA, SCL */
3612 pins = "gpio68", "gpio69";
3613 function = "qup2_se3";
3614 drive-strength = <2>;
3615 bias-pull-up = <2200>;
3616 };
3617
3618 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3619 /* SDA, SCL */
3620 pins = "gpio2", "gpio3";
3621 function = "qup2_se4";
3622 drive-strength = <2>;
3623 bias-pull-up = <2200>;
3624 };
3625
3626 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3627 /* SDA, SCL */
3628 pins = "gpio80", "gpio81";
3629 function = "qup2_se5";
3630 drive-strength = <2>;
3631 bias-pull-up = <2200>;
3632 };
3633
3634 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3635 /* SDA, SCL */
3636 pins = "gpio72", "gpio106";
3637 function = "qup2_se7";
3638 drive-strength = <2>;
3639 bias-pull-up = <2200>;
3640 };
3641
3642 qup_spi0_cs: qup-spi0-cs-state {
3643 pins = "gpio31";
3644 function = "qup1_se0";
3645 drive-strength = <6>;
3646 bias-disable;
3647 };
3648
3649 qup_spi0_data_clk: qup-spi0-data-clk-state {
3650 /* MISO, MOSI, CLK */
3651 pins = "gpio28", "gpio29", "gpio30";
3652 function = "qup1_se0";
3653 drive-strength = <6>;
3654 bias-disable;
3655 };
3656
3657 qup_spi1_cs: qup-spi1-cs-state {
3658 pins = "gpio35";
3659 function = "qup1_se1";
3660 drive-strength = <6>;
3661 bias-disable;
3662 };
3663
3664 qup_spi1_data_clk: qup-spi1-data-clk-state {
3665 /* MISO, MOSI, CLK */
3666 pins = "gpio32", "gpio33", "gpio34";
3667 function = "qup1_se1";
3668 drive-strength = <6>;
3669 bias-disable;
3670 };
3671
3672 qup_spi2_cs: qup-spi2-cs-state {
3673 pins = "gpio39";
3674 function = "qup1_se2";
3675 drive-strength = <6>;
3676 bias-disable;
3677 };
3678
3679 qup_spi2_data_clk: qup-spi2-data-clk-state {
3680 /* MISO, MOSI, CLK */
3681 pins = "gpio36", "gpio37", "gpio38";
3682 function = "qup1_se2";
3683 drive-strength = <6>;
3684 bias-disable;
3685 };
3686
3687 qup_spi3_cs: qup-spi3-cs-state {
3688 pins = "gpio43";
3689 function = "qup1_se3";
3690 drive-strength = <6>;
3691 bias-disable;
3692 };
3693
3694 qup_spi3_data_clk: qup-spi3-data-clk-state {
3695 /* MISO, MOSI, CLK */
3696 pins = "gpio40", "gpio41", "gpio42";
3697 function = "qup1_se3";
3698 drive-strength = <6>;
3699 bias-disable;
3700 };
3701
3702 qup_spi4_cs: qup-spi4-cs-state {
3703 pins = "gpio47";
3704 function = "qup1_se4";
3705 drive-strength = <6>;
3706 bias-disable;
3707 };
3708
3709 qup_spi4_data_clk: qup-spi4-data-clk-state {
3710 /* MISO, MOSI, CLK */
3711 pins = "gpio44", "gpio45", "gpio46";
3712 function = "qup1_se4";
3713 drive-strength = <6>;
3714 bias-disable;
3715 };
3716
3717 qup_spi5_cs: qup-spi5-cs-state {
3718 pins = "gpio55";
3719 function = "qup1_se5";
3720 drive-strength = <6>;
3721 bias-disable;
3722 };
3723
3724 qup_spi5_data_clk: qup-spi5-data-clk-state {
3725 /* MISO, MOSI, CLK */
3726 pins = "gpio52", "gpio53", "gpio54";
3727 function = "qup1_se5";
3728 drive-strength = <6>;
3729 bias-disable;
3730 };
3731
3732 qup_spi6_cs: qup-spi6-cs-state {
3733 pins = "gpio51";
3734 function = "qup1_se6";
3735 drive-strength = <6>;
3736 bias-disable;
3737 };
3738
3739 qup_spi6_data_clk: qup-spi6-data-clk-state {
3740 /* MISO, MOSI, CLK */
3741 pins = "gpio48", "gpio49", "gpio50";
3742 function = "qup1_se6";
3743 drive-strength = <6>;
3744 bias-disable;
3745 };
3746
3747 qup_spi8_cs: qup-spi8-cs-state {
3748 pins = "gpio59";
3749 function = "qup2_se0_l3_mira";
3750 drive-strength = <6>;
3751 bias-disable;
3752 };
3753
3754 qup_spi8_data_clk: qup-spi8-data-clk-state {
3755 /* MISO, MOSI, CLK */
3756 pins = "gpio56", "gpio57", "gpio58";
3757 function = "qup2_se0_l2_mira";
3758 drive-strength = <6>;
3759 bias-disable;
3760 };
3761
3762 qup_spi9_cs: qup-spi9-cs-state {
3763 pins = "gpio63";
3764 function = "qup2_se1";
3765 drive-strength = <6>;
3766 bias-disable;
3767 };
3768
3769 qup_spi9_data_clk: qup-spi9-data-clk-state {
3770 /* MISO, MOSI, CLK */
3771 pins = "gpio60", "gpio61", "gpio62";
3772 function = "qup2_se1";
3773 drive-strength = <6>;
3774 bias-disable;
3775 };
3776
3777 qup_spi10_cs: qup-spi10-cs-state {
3778 pins = "gpio67";
3779 function = "qup2_se2";
3780 drive-strength = <6>;
3781 bias-disable;
3782 };
3783
3784 qup_spi10_data_clk: qup-spi10-data-clk-state {
3785 /* MISO, MOSI, CLK */
3786 pins = "gpio64", "gpio65", "gpio66";
3787 function = "qup2_se2";
3788 drive-strength = <6>;
3789 bias-disable;
3790 };
3791
3792 qup_spi11_cs: qup-spi11-cs-state {
3793 pins = "gpio71";
3794 function = "qup2_se3";
3795 drive-strength = <6>;
3796 bias-disable;
3797 };
3798
3799 qup_spi11_data_clk: qup-spi11-data-clk-state {
3800 /* MISO, MOSI, CLK */
3801 pins = "gpio68", "gpio69", "gpio70";
3802 function = "qup2_se3";
3803 drive-strength = <6>;
3804 bias-disable;
3805 };
3806
3807 qup_spi12_cs: qup-spi12-cs-state {
3808 pins = "gpio119";
3809 function = "qup2_se4";
3810 drive-strength = <6>;
3811 bias-disable;
3812 };
3813
3814 qup_spi12_data_clk: qup-spi12-data-clk-state {
3815 /* MISO, MOSI, CLK */
3816 pins = "gpio2", "gpio3", "gpio118";
3817 function = "qup2_se4";
3818 drive-strength = <6>;
3819 bias-disable;
3820 };
3821
3822 qup_spi13_cs: qup-spi13-cs-state {
3823 pins = "gpio83";
3824 function = "qup2_se5";
3825 drive-strength = <6>;
3826 bias-disable;
3827 };
3828
3829 qup_spi13_data_clk: qup-spi13-data-clk-state {
3830 /* MISO, MOSI, CLK */
3831 pins = "gpio80", "gpio81", "gpio82";
3832 function = "qup2_se5";
3833 drive-strength = <6>;
3834 bias-disable;
3835 };
3836
3837 qup_spi15_cs: qup-spi15-cs-state {
3838 pins = "gpio75";
3839 function = "qup2_se7";
3840 drive-strength = <6>;
3841 bias-disable;
3842 };
3843
3844 qup_spi15_data_clk: qup-spi15-data-clk-state {
3845 /* MISO, MOSI, CLK */
3846 pins = "gpio72", "gpio106", "gpio74";
3847 function = "qup2_se7";
3848 drive-strength = <6>;
3849 bias-disable;
3850 };
3851
3852 qup_uart7_default: qup-uart7-default-state {
3853 /* TX, RX */
3854 pins = "gpio26", "gpio27";
3855 function = "qup1_se7";
3856 drive-strength = <2>;
3857 bias-disable;
3858 };
3859
3860 qup_uart14_default: qup-uart14-default-state {
3861 /* TX, RX */
3862 pins = "gpio78", "gpio79";
3863 function = "qup2_se6";
3864 drive-strength = <2>;
3865 bias-pull-up;
3866 };
3867
3868 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
3869 /* CTS, RTS */
3870 pins = "gpio76", "gpio77";
3871 function = "qup2_se6";
3872 drive-strength = <2>;
3873 bias-pull-down;
3874 };
3875
3876 sdc2_sleep: sdc2-sleep-state {
3877 clk-pins {
3878 pins = "sdc2_clk";
3879 bias-disable;
3880 drive-strength = <2>;
3881 };
3882
3883 cmd-pins {
3884 pins = "sdc2_cmd";
3885 bias-pull-up;
3886 drive-strength = <2>;
3887 };
3888
3889 data-pins {
3890 pins = "sdc2_data";
3891 bias-pull-up;
3892 drive-strength = <2>;
3893 };
3894 };
3895
3896 sdc2_default: sdc2-default-state {
3897 clk-pins {
3898 pins = "sdc2_clk";
3899 bias-disable;
3900 drive-strength = <16>;
3901 };
3902
3903 cmd-pins {
3904 pins = "sdc2_cmd";
3905 bias-pull-up;
3906 drive-strength = <10>;
3907 };
3908
3909 data-pins {
3910 pins = "sdc2_data";
3911 bias-pull-up;
3912 drive-strength = <10>;
3913 };
3914 };
3915 };
3916
3917 apps_smmu: iommu@15000000 {
3918 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3919 reg = <0 0x15000000 0 0x100000>;
3920 #iommu-cells = <2>;
3921 #global-interrupts = <1>;
3922 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3923 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3924 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3925 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3926 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3927 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3928 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3929 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3930 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3931 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3932 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3933 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3934 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3935 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3936 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3937 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3938 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3939 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3940 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3941 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3942 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3943 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3944 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3945 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3946 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3947 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3948 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3949 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3950 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3951 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3952 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3953 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3954 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3955 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3956 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3957 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3958 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3959 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3960 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3961 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3962 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3963 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3964 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3965 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3966 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3967 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3968 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3969 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3970 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3971 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3972 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3973 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3975 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3976 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3977 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3978 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3979 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3980 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3981 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3982 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3983 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3984 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3985 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3986 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3987 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3988 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3989 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3990 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3991 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3992 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3993 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3994 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3995 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3996 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3997 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3998 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3999 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4000 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4001 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4002 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4003 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4004 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4005 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4006 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4007 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
4008 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4009 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4010 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4011 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
4012 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4013 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4014 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4015 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4016 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4017 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4018 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
4019 dma-coherent;
4020 };
4021
4022 intc: interrupt-controller@17100000 {
4023 compatible = "arm,gic-v3";
4024 reg = <0 0x17100000 0 0x10000>, /* GICD */
4025 <0 0x17180000 0 0x200000>; /* GICR * 8 */
4026 ranges;
4027 #interrupt-cells = <3>;
4028 interrupt-controller;
4029 #redistributor-regions = <1>;
4030 redistributor-stride = <0 0x40000>;
4031 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
4032 #address-cells = <2>;
4033 #size-cells = <2>;
4034
4035 gic_its: msi-controller@17140000 {
4036 compatible = "arm,gic-v3-its";
4037 reg = <0 0x17140000 0 0x20000>;
4038 msi-controller;
4039 #msi-cells = <1>;
4040 };
4041 };
4042
4043 timer@17420000 {
4044 compatible = "arm,armv7-timer-mem";
4045 reg = <0 0x17420000 0 0x1000>;
4046 ranges = <0 0 0 0x20000000>;
4047 #address-cells = <1>;
4048 #size-cells = <1>;
4049
4050 frame@17421000 {
4051 reg = <0x17421000 0x1000>,
4052 <0x17422000 0x1000>;
4053 frame-number = <0>;
4054 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4055 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4056 };
4057
4058 frame@17423000 {
4059 reg = <0x17423000 0x1000>;
4060 frame-number = <1>;
4061 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4062 status = "disabled";
4063 };
4064
4065 frame@17425000 {
4066 reg = <0x17425000 0x1000>;
4067 frame-number = <2>;
4068 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4069 status = "disabled";
4070 };
4071
4072 frame@17427000 {
4073 reg = <0x17427000 0x1000>;
4074 frame-number = <3>;
4075 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4076 status = "disabled";
4077 };
4078
4079 frame@17429000 {
4080 reg = <0x17429000 0x1000>;
4081 frame-number = <4>;
4082 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4083 status = "disabled";
4084 };
4085
4086 frame@1742b000 {
4087 reg = <0x1742b000 0x1000>;
4088 frame-number = <5>;
4089 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4090 status = "disabled";
4091 };
4092
4093 frame@1742d000 {
4094 reg = <0x1742d000 0x1000>;
4095 frame-number = <6>;
4096 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4097 status = "disabled";
4098 };
4099 };
4100
4101 apps_rsc: rsc@17a00000 {
4102 label = "apps_rsc";
4103 compatible = "qcom,rpmh-rsc";
4104 reg = <0 0x17a00000 0 0x10000>,
4105 <0 0x17a10000 0 0x10000>,
4106 <0 0x17a20000 0 0x10000>,
4107 <0 0x17a30000 0 0x10000>;
4108 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4109 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4110 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4111 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4112 qcom,tcs-offset = <0xd00>;
4113 qcom,drv-id = <2>;
4114 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4115 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4116 power-domains = <&CLUSTER_PD>;
4117
4118 apps_bcm_voter: bcm-voter {
4119 compatible = "qcom,bcm-voter";
4120 };
4121
4122 rpmhcc: clock-controller {
4123 compatible = "qcom,sm8550-rpmh-clk";
4124 #clock-cells = <1>;
4125 clock-names = "xo";
4126 clocks = <&xo_board>;
4127 };
4128
4129 rpmhpd: power-controller {
4130 compatible = "qcom,sm8550-rpmhpd";
4131 #power-domain-cells = <1>;
4132 operating-points-v2 = <&rpmhpd_opp_table>;
4133
4134 rpmhpd_opp_table: opp-table {
4135 compatible = "operating-points-v2";
4136
4137 rpmhpd_opp_ret: opp-16 {
4138 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4139 };
4140
4141 rpmhpd_opp_min_svs: opp-48 {
4142 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4143 };
4144
4145 rpmhpd_opp_low_svs_d2: opp-52 {
4146 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
4147 };
4148
4149 rpmhpd_opp_low_svs_d1: opp-56 {
4150 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4151 };
4152
4153 rpmhpd_opp_low_svs_d0: opp-60 {
4154 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
4155 };
4156
4157 rpmhpd_opp_low_svs: opp-64 {
4158 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4159 };
4160
4161 rpmhpd_opp_low_svs_l1: opp-80 {
4162 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4163 };
4164
4165 rpmhpd_opp_svs: opp-128 {
4166 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4167 };
4168
4169 rpmhpd_opp_svs_l0: opp-144 {
4170 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4171 };
4172
4173 rpmhpd_opp_svs_l1: opp-192 {
4174 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4175 };
4176
4177 rpmhpd_opp_nom: opp-256 {
4178 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4179 };
4180
4181 rpmhpd_opp_nom_l1: opp-320 {
4182 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4183 };
4184
4185 rpmhpd_opp_nom_l2: opp-336 {
4186 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4187 };
4188
4189 rpmhpd_opp_turbo: opp-384 {
4190 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4191 };
4192
4193 rpmhpd_opp_turbo_l1: opp-416 {
4194 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4195 };
4196 };
4197 };
4198 };
4199
4200 cpufreq_hw: cpufreq@17d91000 {
4201 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
4202 reg = <0 0x17d91000 0 0x1000>,
4203 <0 0x17d92000 0 0x1000>,
4204 <0 0x17d93000 0 0x1000>;
4205 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4206 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
4207 clock-names = "xo", "alternate";
4208 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4211 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4212 #freq-domain-cells = <1>;
4213 #clock-cells = <1>;
4214 };
4215
4216 pmu@24091000 {
4217 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4218 reg = <0 0x24091000 0 0x1000>;
4219 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
4220 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
4221
4222 operating-points-v2 = <&llcc_bwmon_opp_table>;
4223
4224 llcc_bwmon_opp_table: opp-table {
4225 compatible = "operating-points-v2";
4226
4227 opp-0 {
4228 opp-peak-kBps = <2086000>;
4229 };
4230
4231 opp-1 {
4232 opp-peak-kBps = <2929000>;
4233 };
4234
4235 opp-2 {
4236 opp-peak-kBps = <5931000>;
4237 };
4238
4239 opp-3 {
4240 opp-peak-kBps = <6515000>;
4241 };
4242
4243 opp-4 {
4244 opp-peak-kBps = <7980000>;
4245 };
4246
4247 opp-5 {
4248 opp-peak-kBps = <10437000>;
4249 };
4250
4251 opp-6 {
4252 opp-peak-kBps = <12157000>;
4253 };
4254
4255 opp-7 {
4256 opp-peak-kBps = <14060000>;
4257 };
4258
4259 opp-8 {
4260 opp-peak-kBps = <16113000>;
4261 };
4262 };
4263 };
4264
4265 pmu@240b6400 {
4266 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
4267 reg = <0 0x240b6400 0 0x600>;
4268 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
4269 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
4270
4271 operating-points-v2 = <&cpu_bwmon_opp_table>;
4272
4273 cpu_bwmon_opp_table: opp-table {
4274 compatible = "operating-points-v2";
4275
4276 opp-0 {
4277 opp-peak-kBps = <4577000>;
4278 };
4279
4280 opp-1 {
4281 opp-peak-kBps = <7110000>;
4282 };
4283
4284 opp-2 {
4285 opp-peak-kBps = <9155000>;
4286 };
4287
4288 opp-3 {
4289 opp-peak-kBps = <12298000>;
4290 };
4291
4292 opp-4 {
4293 opp-peak-kBps = <14236000>;
4294 };
4295
4296 opp-5 {
4297 opp-peak-kBps = <16265000>;
4298 };
4299 };
4300 };
4301
4302 gem_noc: interconnect@24100000 {
4303 compatible = "qcom,sm8550-gem-noc";
4304 reg = <0 0x24100000 0 0xbb800>;
4305 #interconnect-cells = <2>;
4306 qcom,bcm-voters = <&apps_bcm_voter>;
4307 };
4308
4309 system-cache-controller@25000000 {
4310 compatible = "qcom,sm8550-llcc";
4311 reg = <0 0x25000000 0 0x200000>,
4312 <0 0x25200000 0 0x200000>,
4313 <0 0x25400000 0 0x200000>,
4314 <0 0x25600000 0 0x200000>,
4315 <0 0x25800000 0 0x200000>,
4316 <0 0x25a00000 0 0x200000>;
4317 reg-names = "llcc0_base",
4318 "llcc1_base",
4319 "llcc2_base",
4320 "llcc3_base",
4321 "llcc_broadcast_base",
4322 "llcc_broadcast_and_base";
4323 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4324 };
4325
4326 remoteproc_adsp: remoteproc@30000000 {
4327 compatible = "qcom,sm8550-adsp-pas";
4328 reg = <0x0 0x30000000 0x0 0x100>;
4329
4330 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4331 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4332 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
4333 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
4334 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
4335 interrupt-names = "wdog", "fatal", "ready",
4336 "handover", "stop-ack";
4337
4338 clocks = <&rpmhcc RPMH_CXO_CLK>;
4339 clock-names = "xo";
4340
4341 power-domains = <&rpmhpd RPMHPD_LCX>,
4342 <&rpmhpd RPMHPD_LMX>;
4343 power-domain-names = "lcx", "lmx";
4344
4345 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
4346
4347 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
4348
4349 qcom,qmp = <&aoss_qmp>;
4350
4351 qcom,smem-states = <&smp2p_adsp_out 0>;
4352 qcom,smem-state-names = "stop";
4353
4354 status = "disabled";
4355
4356 remoteproc_adsp_glink: glink-edge {
4357 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4358 IPCC_MPROC_SIGNAL_GLINK_QMP
4359 IRQ_TYPE_EDGE_RISING>;
4360 mboxes = <&ipcc IPCC_CLIENT_LPASS
4361 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4362
4363 label = "lpass";
4364 qcom,remote-pid = <2>;
4365
4366 fastrpc {
4367 compatible = "qcom,fastrpc";
4368 qcom,glink-channels = "fastrpcglink-apps-dsp";
4369 label = "adsp";
4370 qcom,non-secure-domain;
4371 #address-cells = <1>;
4372 #size-cells = <0>;
4373
4374 compute-cb@3 {
4375 compatible = "qcom,fastrpc-compute-cb";
4376 reg = <3>;
4377 iommus = <&apps_smmu 0x1003 0x80>,
4378 <&apps_smmu 0x1063 0x0>;
4379 dma-coherent;
4380 };
4381
4382 compute-cb@4 {
4383 compatible = "qcom,fastrpc-compute-cb";
4384 reg = <4>;
4385 iommus = <&apps_smmu 0x1004 0x80>,
4386 <&apps_smmu 0x1064 0x0>;
4387 dma-coherent;
4388 };
4389
4390 compute-cb@5 {
4391 compatible = "qcom,fastrpc-compute-cb";
4392 reg = <5>;
4393 iommus = <&apps_smmu 0x1005 0x80>,
4394 <&apps_smmu 0x1065 0x0>;
4395 dma-coherent;
4396 };
4397
4398 compute-cb@6 {
4399 compatible = "qcom,fastrpc-compute-cb";
4400 reg = <6>;
4401 iommus = <&apps_smmu 0x1006 0x80>,
4402 <&apps_smmu 0x1066 0x0>;
4403 dma-coherent;
4404 };
4405
4406 compute-cb@7 {
4407 compatible = "qcom,fastrpc-compute-cb";
4408 reg = <7>;
4409 iommus = <&apps_smmu 0x1007 0x80>,
4410 <&apps_smmu 0x1067 0x0>;
4411 dma-coherent;
4412 };
4413 };
4414
4415 gpr {
4416 compatible = "qcom,gpr";
4417 qcom,glink-channels = "adsp_apps";
4418 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
4419 qcom,intents = <512 20>;
4420 #address-cells = <1>;
4421 #size-cells = <0>;
4422
4423 q6apm: service@1 {
4424 compatible = "qcom,q6apm";
4425 reg = <GPR_APM_MODULE_IID>;
4426 #sound-dai-cells = <0>;
4427 qcom,protection-domain = "avs/audio",
4428 "msm/adsp/audio_pd";
4429
4430 q6apmdai: dais {
4431 compatible = "qcom,q6apm-dais";
4432 iommus = <&apps_smmu 0x1001 0x80>,
4433 <&apps_smmu 0x1061 0x0>;
4434 };
4435
4436 q6apmbedai: bedais {
4437 compatible = "qcom,q6apm-lpass-dais";
4438 #sound-dai-cells = <1>;
4439 };
4440 };
4441
4442 q6prm: service@2 {
4443 compatible = "qcom,q6prm";
4444 reg = <GPR_PRM_MODULE_IID>;
4445 qcom,protection-domain = "avs/audio",
4446 "msm/adsp/audio_pd";
4447
4448 q6prmcc: clock-controller {
4449 compatible = "qcom,q6prm-lpass-clocks";
4450 #clock-cells = <2>;
4451 };
4452 };
4453 };
4454 };
4455 };
4456
4457 nsp_noc: interconnect@320c0000 {
4458 compatible = "qcom,sm8550-nsp-noc";
4459 reg = <0 0x320c0000 0 0xe080>;
4460 #interconnect-cells = <2>;
4461 qcom,bcm-voters = <&apps_bcm_voter>;
4462 };
4463
4464 remoteproc_cdsp: remoteproc@32300000 {
4465 compatible = "qcom,sm8550-cdsp-pas";
4466 reg = <0x0 0x32300000 0x0 0x1400000>;
4467
4468 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4469 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
4470 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
4471 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
4472 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
4473 interrupt-names = "wdog", "fatal", "ready",
4474 "handover", "stop-ack";
4475
4476 clocks = <&rpmhcc RPMH_CXO_CLK>;
4477 clock-names = "xo";
4478
4479 power-domains = <&rpmhpd RPMHPD_CX>,
4480 <&rpmhpd RPMHPD_MXC>,
4481 <&rpmhpd RPMHPD_NSP>;
4482 power-domain-names = "cx", "mxc", "nsp";
4483
4484 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4485
4486 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
4487
4488 qcom,qmp = <&aoss_qmp>;
4489
4490 qcom,smem-states = <&smp2p_cdsp_out 0>;
4491 qcom,smem-state-names = "stop";
4492
4493 status = "disabled";
4494
4495 glink-edge {
4496 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4497 IPCC_MPROC_SIGNAL_GLINK_QMP
4498 IRQ_TYPE_EDGE_RISING>;
4499 mboxes = <&ipcc IPCC_CLIENT_CDSP
4500 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4501
4502 label = "cdsp";
4503 qcom,remote-pid = <5>;
4504
4505 fastrpc {
4506 compatible = "qcom,fastrpc";
4507 qcom,glink-channels = "fastrpcglink-apps-dsp";
4508 label = "cdsp";
4509 qcom,non-secure-domain;
4510 #address-cells = <1>;
4511 #size-cells = <0>;
4512
4513 compute-cb@1 {
4514 compatible = "qcom,fastrpc-compute-cb";
4515 reg = <1>;
4516 iommus = <&apps_smmu 0x1961 0x0>,
4517 <&apps_smmu 0x0c01 0x20>,
4518 <&apps_smmu 0x19c1 0x10>;
4519 dma-coherent;
4520 };
4521
4522 compute-cb@2 {
4523 compatible = "qcom,fastrpc-compute-cb";
4524 reg = <2>;
4525 iommus = <&apps_smmu 0x1962 0x0>,
4526 <&apps_smmu 0x0c02 0x20>,
4527 <&apps_smmu 0x19c2 0x10>;
4528 dma-coherent;
4529 };
4530
4531 compute-cb@3 {
4532 compatible = "qcom,fastrpc-compute-cb";
4533 reg = <3>;
4534 iommus = <&apps_smmu 0x1963 0x0>,
4535 <&apps_smmu 0x0c03 0x20>,
4536 <&apps_smmu 0x19c3 0x10>;
4537 dma-coherent;
4538 };
4539
4540 compute-cb@4 {
4541 compatible = "qcom,fastrpc-compute-cb";
4542 reg = <4>;
4543 iommus = <&apps_smmu 0x1964 0x0>,
4544 <&apps_smmu 0x0c04 0x20>,
4545 <&apps_smmu 0x19c4 0x10>;
4546 dma-coherent;
4547 };
4548
4549 compute-cb@5 {
4550 compatible = "qcom,fastrpc-compute-cb";
4551 reg = <5>;
4552 iommus = <&apps_smmu 0x1965 0x0>,
4553 <&apps_smmu 0x0c05 0x20>,
4554 <&apps_smmu 0x19c5 0x10>;
4555 dma-coherent;
4556 };
4557
4558 compute-cb@6 {
4559 compatible = "qcom,fastrpc-compute-cb";
4560 reg = <6>;
4561 iommus = <&apps_smmu 0x1966 0x0>,
4562 <&apps_smmu 0x0c06 0x20>,
4563 <&apps_smmu 0x19c6 0x10>;
4564 dma-coherent;
4565 };
4566
4567 compute-cb@7 {
4568 compatible = "qcom,fastrpc-compute-cb";
4569 reg = <7>;
4570 iommus = <&apps_smmu 0x1967 0x0>,
4571 <&apps_smmu 0x0c07 0x20>,
4572 <&apps_smmu 0x19c7 0x10>;
4573 dma-coherent;
4574 };
4575
4576 compute-cb@8 {
4577 compatible = "qcom,fastrpc-compute-cb";
4578 reg = <8>;
4579 iommus = <&apps_smmu 0x1968 0x0>,
4580 <&apps_smmu 0x0c08 0x20>,
4581 <&apps_smmu 0x19c8 0x10>;
4582 dma-coherent;
4583 };
4584
4585 /* note: secure cb9 in downstream */
4586 };
4587 };
4588 };
4589 };
4590
4591 thermal-zones {
4592 aoss0-thermal {
4593 thermal-sensors = <&tsens0 0>;
4594
4595 trips {
4596 thermal-engine-config {
4597 temperature = <125000>;
4598 hysteresis = <1000>;
4599 type = "passive";
4600 };
4601
4602 reset-mon-config {
4603 temperature = <115000>;
4604 hysteresis = <5000>;
4605 type = "passive";
4606 };
4607 };
4608 };
4609
4610 cpuss0-thermal {
4611 thermal-sensors = <&tsens0 1>;
4612
4613 trips {
4614 thermal-engine-config {
4615 temperature = <125000>;
4616 hysteresis = <1000>;
4617 type = "passive";
4618 };
4619
4620 reset-mon-config {
4621 temperature = <115000>;
4622 hysteresis = <5000>;
4623 type = "passive";
4624 };
4625 };
4626 };
4627
4628 cpuss1-thermal {
4629 thermal-sensors = <&tsens0 2>;
4630
4631 trips {
4632 thermal-engine-config {
4633 temperature = <125000>;
4634 hysteresis = <1000>;
4635 type = "passive";
4636 };
4637
4638 reset-mon-config {
4639 temperature = <115000>;
4640 hysteresis = <5000>;
4641 type = "passive";
4642 };
4643 };
4644 };
4645
4646 cpuss2-thermal {
4647 thermal-sensors = <&tsens0 3>;
4648
4649 trips {
4650 thermal-engine-config {
4651 temperature = <125000>;
4652 hysteresis = <1000>;
4653 type = "passive";
4654 };
4655
4656 reset-mon-config {
4657 temperature = <115000>;
4658 hysteresis = <5000>;
4659 type = "passive";
4660 };
4661 };
4662 };
4663
4664 cpuss3-thermal {
4665 thermal-sensors = <&tsens0 4>;
4666
4667 trips {
4668 thermal-engine-config {
4669 temperature = <125000>;
4670 hysteresis = <1000>;
4671 type = "passive";
4672 };
4673
4674 reset-mon-config {
4675 temperature = <115000>;
4676 hysteresis = <5000>;
4677 type = "passive";
4678 };
4679 };
4680 };
4681
4682 cpu3-top-thermal {
4683 thermal-sensors = <&tsens0 5>;
4684
4685 trips {
4686 cpu3_top_alert0: trip-point0 {
4687 temperature = <90000>;
4688 hysteresis = <2000>;
4689 type = "passive";
4690 };
4691
4692 cpu3_top_alert1: trip-point1 {
4693 temperature = <95000>;
4694 hysteresis = <2000>;
4695 type = "passive";
4696 };
4697
4698 cpu3_top_crit: cpu-critical {
4699 temperature = <110000>;
4700 hysteresis = <1000>;
4701 type = "critical";
4702 };
4703 };
4704 };
4705
4706 cpu3-bottom-thermal {
4707 thermal-sensors = <&tsens0 6>;
4708
4709 trips {
4710 cpu3_bottom_alert0: trip-point0 {
4711 temperature = <90000>;
4712 hysteresis = <2000>;
4713 type = "passive";
4714 };
4715
4716 cpu3_bottom_alert1: trip-point1 {
4717 temperature = <95000>;
4718 hysteresis = <2000>;
4719 type = "passive";
4720 };
4721
4722 cpu3_bottom_crit: cpu-critical {
4723 temperature = <110000>;
4724 hysteresis = <1000>;
4725 type = "critical";
4726 };
4727 };
4728 };
4729
4730 cpu4-top-thermal {
4731 thermal-sensors = <&tsens0 7>;
4732
4733 trips {
4734 cpu4_top_alert0: trip-point0 {
4735 temperature = <90000>;
4736 hysteresis = <2000>;
4737 type = "passive";
4738 };
4739
4740 cpu4_top_alert1: trip-point1 {
4741 temperature = <95000>;
4742 hysteresis = <2000>;
4743 type = "passive";
4744 };
4745
4746 cpu4_top_crit: cpu-critical {
4747 temperature = <110000>;
4748 hysteresis = <1000>;
4749 type = "critical";
4750 };
4751 };
4752 };
4753
4754 cpu4-bottom-thermal {
4755 thermal-sensors = <&tsens0 8>;
4756
4757 trips {
4758 cpu4_bottom_alert0: trip-point0 {
4759 temperature = <90000>;
4760 hysteresis = <2000>;
4761 type = "passive";
4762 };
4763
4764 cpu4_bottom_alert1: trip-point1 {
4765 temperature = <95000>;
4766 hysteresis = <2000>;
4767 type = "passive";
4768 };
4769
4770 cpu4_bottom_crit: cpu-critical {
4771 temperature = <110000>;
4772 hysteresis = <1000>;
4773 type = "critical";
4774 };
4775 };
4776 };
4777
4778 cpu5-top-thermal {
4779 thermal-sensors = <&tsens0 9>;
4780
4781 trips {
4782 cpu5_top_alert0: trip-point0 {
4783 temperature = <90000>;
4784 hysteresis = <2000>;
4785 type = "passive";
4786 };
4787
4788 cpu5_top_alert1: trip-point1 {
4789 temperature = <95000>;
4790 hysteresis = <2000>;
4791 type = "passive";
4792 };
4793
4794 cpu5_top_crit: cpu-critical {
4795 temperature = <110000>;
4796 hysteresis = <1000>;
4797 type = "critical";
4798 };
4799 };
4800 };
4801
4802 cpu5-bottom-thermal {
4803 thermal-sensors = <&tsens0 10>;
4804
4805 trips {
4806 cpu5_bottom_alert0: trip-point0 {
4807 temperature = <90000>;
4808 hysteresis = <2000>;
4809 type = "passive";
4810 };
4811
4812 cpu5_bottom_alert1: trip-point1 {
4813 temperature = <95000>;
4814 hysteresis = <2000>;
4815 type = "passive";
4816 };
4817
4818 cpu5_bottom_crit: cpu-critical {
4819 temperature = <110000>;
4820 hysteresis = <1000>;
4821 type = "critical";
4822 };
4823 };
4824 };
4825
4826 cpu6-top-thermal {
4827 thermal-sensors = <&tsens0 11>;
4828
4829 trips {
4830 cpu6_top_alert0: trip-point0 {
4831 temperature = <90000>;
4832 hysteresis = <2000>;
4833 type = "passive";
4834 };
4835
4836 cpu6_top_alert1: trip-point1 {
4837 temperature = <95000>;
4838 hysteresis = <2000>;
4839 type = "passive";
4840 };
4841
4842 cpu6_top_crit: cpu-critical {
4843 temperature = <110000>;
4844 hysteresis = <1000>;
4845 type = "critical";
4846 };
4847 };
4848 };
4849
4850 cpu6-bottom-thermal {
4851 thermal-sensors = <&tsens0 12>;
4852
4853 trips {
4854 cpu6_bottom_alert0: trip-point0 {
4855 temperature = <90000>;
4856 hysteresis = <2000>;
4857 type = "passive";
4858 };
4859
4860 cpu6_bottom_alert1: trip-point1 {
4861 temperature = <95000>;
4862 hysteresis = <2000>;
4863 type = "passive";
4864 };
4865
4866 cpu6_bottom_crit: cpu-critical {
4867 temperature = <110000>;
4868 hysteresis = <1000>;
4869 type = "critical";
4870 };
4871 };
4872 };
4873
4874 cpu7-top-thermal {
4875 thermal-sensors = <&tsens0 13>;
4876
4877 trips {
4878 cpu7_top_alert0: trip-point0 {
4879 temperature = <90000>;
4880 hysteresis = <2000>;
4881 type = "passive";
4882 };
4883
4884 cpu7_top_alert1: trip-point1 {
4885 temperature = <95000>;
4886 hysteresis = <2000>;
4887 type = "passive";
4888 };
4889
4890 cpu7_top_crit: cpu-critical {
4891 temperature = <110000>;
4892 hysteresis = <1000>;
4893 type = "critical";
4894 };
4895 };
4896 };
4897
4898 cpu7-middle-thermal {
4899 thermal-sensors = <&tsens0 14>;
4900
4901 trips {
4902 cpu7_middle_alert0: trip-point0 {
4903 temperature = <90000>;
4904 hysteresis = <2000>;
4905 type = "passive";
4906 };
4907
4908 cpu7_middle_alert1: trip-point1 {
4909 temperature = <95000>;
4910 hysteresis = <2000>;
4911 type = "passive";
4912 };
4913
4914 cpu7_middle_crit: cpu-critical {
4915 temperature = <110000>;
4916 hysteresis = <1000>;
4917 type = "critical";
4918 };
4919 };
4920 };
4921
4922 cpu7-bottom-thermal {
4923 thermal-sensors = <&tsens0 15>;
4924
4925 trips {
4926 cpu7_bottom_alert0: trip-point0 {
4927 temperature = <90000>;
4928 hysteresis = <2000>;
4929 type = "passive";
4930 };
4931
4932 cpu7_bottom_alert1: trip-point1 {
4933 temperature = <95000>;
4934 hysteresis = <2000>;
4935 type = "passive";
4936 };
4937
4938 cpu7_bottom_crit: cpu-critical {
4939 temperature = <110000>;
4940 hysteresis = <1000>;
4941 type = "critical";
4942 };
4943 };
4944 };
4945
4946 aoss1-thermal {
4947 thermal-sensors = <&tsens1 0>;
4948
4949 trips {
4950 thermal-engine-config {
4951 temperature = <125000>;
4952 hysteresis = <1000>;
4953 type = "passive";
4954 };
4955
4956 reset-mon-config {
4957 temperature = <115000>;
4958 hysteresis = <5000>;
4959 type = "passive";
4960 };
4961 };
4962 };
4963
4964 cpu0-thermal {
4965 thermal-sensors = <&tsens1 1>;
4966
4967 trips {
4968 cpu0_alert0: trip-point0 {
4969 temperature = <90000>;
4970 hysteresis = <2000>;
4971 type = "passive";
4972 };
4973
4974 cpu0_alert1: trip-point1 {
4975 temperature = <95000>;
4976 hysteresis = <2000>;
4977 type = "passive";
4978 };
4979
4980 cpu0_crit: cpu-critical {
4981 temperature = <110000>;
4982 hysteresis = <1000>;
4983 type = "critical";
4984 };
4985 };
4986 };
4987
4988 cpu1-thermal {
4989 thermal-sensors = <&tsens1 2>;
4990
4991 trips {
4992 cpu1_alert0: trip-point0 {
4993 temperature = <90000>;
4994 hysteresis = <2000>;
4995 type = "passive";
4996 };
4997
4998 cpu1_alert1: trip-point1 {
4999 temperature = <95000>;
5000 hysteresis = <2000>;
5001 type = "passive";
5002 };
5003
5004 cpu1_crit: cpu-critical {
5005 temperature = <110000>;
5006 hysteresis = <1000>;
5007 type = "critical";
5008 };
5009 };
5010 };
5011
5012 cpu2-thermal {
5013 thermal-sensors = <&tsens1 3>;
5014
5015 trips {
5016 cpu2_alert0: trip-point0 {
5017 temperature = <90000>;
5018 hysteresis = <2000>;
5019 type = "passive";
5020 };
5021
5022 cpu2_alert1: trip-point1 {
5023 temperature = <95000>;
5024 hysteresis = <2000>;
5025 type = "passive";
5026 };
5027
5028 cpu2_crit: cpu-critical {
5029 temperature = <110000>;
5030 hysteresis = <1000>;
5031 type = "critical";
5032 };
5033 };
5034 };
5035
5036 cdsp0-thermal {
5037 polling-delay-passive = <10>;
5038
5039 thermal-sensors = <&tsens2 4>;
5040
5041 trips {
5042 thermal-engine-config {
5043 temperature = <125000>;
5044 hysteresis = <1000>;
5045 type = "passive";
5046 };
5047
5048 thermal-hal-config {
5049 temperature = <125000>;
5050 hysteresis = <1000>;
5051 type = "passive";
5052 };
5053
5054 reset-mon-config {
5055 temperature = <115000>;
5056 hysteresis = <5000>;
5057 type = "passive";
5058 };
5059
5060 cdsp0_junction_config: junction-config {
5061 temperature = <95000>;
5062 hysteresis = <5000>;
5063 type = "passive";
5064 };
5065 };
5066 };
5067
5068 cdsp1-thermal {
5069 polling-delay-passive = <10>;
5070
5071 thermal-sensors = <&tsens2 5>;
5072
5073 trips {
5074 thermal-engine-config {
5075 temperature = <125000>;
5076 hysteresis = <1000>;
5077 type = "passive";
5078 };
5079
5080 thermal-hal-config {
5081 temperature = <125000>;
5082 hysteresis = <1000>;
5083 type = "passive";
5084 };
5085
5086 reset-mon-config {
5087 temperature = <115000>;
5088 hysteresis = <5000>;
5089 type = "passive";
5090 };
5091
5092 cdsp1_junction_config: junction-config {
5093 temperature = <95000>;
5094 hysteresis = <5000>;
5095 type = "passive";
5096 };
5097 };
5098 };
5099
5100 cdsp2-thermal {
5101 polling-delay-passive = <10>;
5102
5103 thermal-sensors = <&tsens2 6>;
5104
5105 trips {
5106 thermal-engine-config {
5107 temperature = <125000>;
5108 hysteresis = <1000>;
5109 type = "passive";
5110 };
5111
5112 thermal-hal-config {
5113 temperature = <125000>;
5114 hysteresis = <1000>;
5115 type = "passive";
5116 };
5117
5118 reset-mon-config {
5119 temperature = <115000>;
5120 hysteresis = <5000>;
5121 type = "passive";
5122 };
5123
5124 cdsp2_junction_config: junction-config {
5125 temperature = <95000>;
5126 hysteresis = <5000>;
5127 type = "passive";
5128 };
5129 };
5130 };
5131
5132 cdsp3-thermal {
5133 polling-delay-passive = <10>;
5134
5135 thermal-sensors = <&tsens2 7>;
5136
5137 trips {
5138 thermal-engine-config {
5139 temperature = <125000>;
5140 hysteresis = <1000>;
5141 type = "passive";
5142 };
5143
5144 thermal-hal-config {
5145 temperature = <125000>;
5146 hysteresis = <1000>;
5147 type = "passive";
5148 };
5149
5150 reset-mon-config {
5151 temperature = <115000>;
5152 hysteresis = <5000>;
5153 type = "passive";
5154 };
5155
5156 cdsp3_junction_config: junction-config {
5157 temperature = <95000>;
5158 hysteresis = <5000>;
5159 type = "passive";
5160 };
5161 };
5162 };
5163
5164 video-thermal {
5165 thermal-sensors = <&tsens1 8>;
5166
5167 trips {
5168 thermal-engine-config {
5169 temperature = <125000>;
5170 hysteresis = <1000>;
5171 type = "passive";
5172 };
5173
5174 reset-mon-config {
5175 temperature = <115000>;
5176 hysteresis = <5000>;
5177 type = "passive";
5178 };
5179 };
5180 };
5181
5182 mem-thermal {
5183 polling-delay-passive = <10>;
5184
5185 thermal-sensors = <&tsens1 9>;
5186
5187 trips {
5188 thermal-engine-config {
5189 temperature = <125000>;
5190 hysteresis = <1000>;
5191 type = "passive";
5192 };
5193
5194 ddr_config0: ddr0-config {
5195 temperature = <90000>;
5196 hysteresis = <5000>;
5197 type = "passive";
5198 };
5199
5200 reset-mon-config {
5201 temperature = <115000>;
5202 hysteresis = <5000>;
5203 type = "passive";
5204 };
5205 };
5206 };
5207
5208 modem0-thermal {
5209 thermal-sensors = <&tsens1 10>;
5210
5211 trips {
5212 thermal-engine-config {
5213 temperature = <125000>;
5214 hysteresis = <1000>;
5215 type = "passive";
5216 };
5217
5218 mdmss0_config0: mdmss0-config0 {
5219 temperature = <102000>;
5220 hysteresis = <3000>;
5221 type = "passive";
5222 };
5223
5224 mdmss0_config1: mdmss0-config1 {
5225 temperature = <105000>;
5226 hysteresis = <3000>;
5227 type = "passive";
5228 };
5229
5230 reset-mon-config {
5231 temperature = <115000>;
5232 hysteresis = <5000>;
5233 type = "passive";
5234 };
5235 };
5236 };
5237
5238 modem1-thermal {
5239 thermal-sensors = <&tsens1 11>;
5240
5241 trips {
5242 thermal-engine-config {
5243 temperature = <125000>;
5244 hysteresis = <1000>;
5245 type = "passive";
5246 };
5247
5248 mdmss1_config0: mdmss1-config0 {
5249 temperature = <102000>;
5250 hysteresis = <3000>;
5251 type = "passive";
5252 };
5253
5254 mdmss1_config1: mdmss1-config1 {
5255 temperature = <105000>;
5256 hysteresis = <3000>;
5257 type = "passive";
5258 };
5259
5260 reset-mon-config {
5261 temperature = <115000>;
5262 hysteresis = <5000>;
5263 type = "passive";
5264 };
5265 };
5266 };
5267
5268 modem2-thermal {
5269 thermal-sensors = <&tsens1 12>;
5270
5271 trips {
5272 thermal-engine-config {
5273 temperature = <125000>;
5274 hysteresis = <1000>;
5275 type = "passive";
5276 };
5277
5278 mdmss2_config0: mdmss2-config0 {
5279 temperature = <102000>;
5280 hysteresis = <3000>;
5281 type = "passive";
5282 };
5283
5284 mdmss2_config1: mdmss2-config1 {
5285 temperature = <105000>;
5286 hysteresis = <3000>;
5287 type = "passive";
5288 };
5289
5290 reset-mon-config {
5291 temperature = <115000>;
5292 hysteresis = <5000>;
5293 type = "passive";
5294 };
5295 };
5296 };
5297
5298 modem3-thermal {
5299 thermal-sensors = <&tsens1 13>;
5300
5301 trips {
5302 thermal-engine-config {
5303 temperature = <125000>;
5304 hysteresis = <1000>;
5305 type = "passive";
5306 };
5307
5308 mdmss3_config0: mdmss3-config0 {
5309 temperature = <102000>;
5310 hysteresis = <3000>;
5311 type = "passive";
5312 };
5313
5314 mdmss3_config1: mdmss3-config1 {
5315 temperature = <105000>;
5316 hysteresis = <3000>;
5317 type = "passive";
5318 };
5319
5320 reset-mon-config {
5321 temperature = <115000>;
5322 hysteresis = <5000>;
5323 type = "passive";
5324 };
5325 };
5326 };
5327
5328 camera0-thermal {
5329 thermal-sensors = <&tsens1 14>;
5330
5331 trips {
5332 thermal-engine-config {
5333 temperature = <125000>;
5334 hysteresis = <1000>;
5335 type = "passive";
5336 };
5337
5338 reset-mon-config {
5339 temperature = <115000>;
5340 hysteresis = <5000>;
5341 type = "passive";
5342 };
5343 };
5344 };
5345
5346 camera1-thermal {
5347 thermal-sensors = <&tsens1 15>;
5348
5349 trips {
5350 thermal-engine-config {
5351 temperature = <125000>;
5352 hysteresis = <1000>;
5353 type = "passive";
5354 };
5355
5356 reset-mon-config {
5357 temperature = <115000>;
5358 hysteresis = <5000>;
5359 type = "passive";
5360 };
5361 };
5362 };
5363
5364 aoss2-thermal {
5365 thermal-sensors = <&tsens2 0>;
5366
5367 trips {
5368 thermal-engine-config {
5369 temperature = <125000>;
5370 hysteresis = <1000>;
5371 type = "passive";
5372 };
5373
5374 reset-mon-config {
5375 temperature = <115000>;
5376 hysteresis = <5000>;
5377 type = "passive";
5378 };
5379 };
5380 };
5381
5382 gpuss-0-thermal {
5383 polling-delay-passive = <10>;
5384
5385 thermal-sensors = <&tsens2 1>;
5386
5387 cooling-maps {
5388 map0 {
5389 trip = <&gpu0_alert0>;
5390 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5391 };
5392 };
5393
5394 trips {
5395 gpu0_alert0: trip-point0 {
5396 temperature = <85000>;
5397 hysteresis = <1000>;
5398 type = "passive";
5399 };
5400
5401 trip-point1 {
5402 temperature = <90000>;
5403 hysteresis = <1000>;
5404 type = "hot";
5405 };
5406
5407 trip-point2 {
5408 temperature = <110000>;
5409 hysteresis = <1000>;
5410 type = "critical";
5411 };
5412 };
5413 };
5414
5415 gpuss-1-thermal {
5416 polling-delay-passive = <10>;
5417
5418 thermal-sensors = <&tsens2 2>;
5419
5420 cooling-maps {
5421 map0 {
5422 trip = <&gpu1_alert0>;
5423 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5424 };
5425 };
5426
5427 trips {
5428 gpu1_alert0: trip-point0 {
5429 temperature = <85000>;
5430 hysteresis = <1000>;
5431 type = "passive";
5432 };
5433
5434 trip-point1 {
5435 temperature = <90000>;
5436 hysteresis = <1000>;
5437 type = "hot";
5438 };
5439
5440 trip-point2 {
5441 temperature = <110000>;
5442 hysteresis = <1000>;
5443 type = "critical";
5444 };
5445 };
5446 };
5447
5448 gpuss-2-thermal {
5449 polling-delay-passive = <10>;
5450
5451 thermal-sensors = <&tsens2 3>;
5452
5453 cooling-maps {
5454 map0 {
5455 trip = <&gpu2_alert0>;
5456 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5457 };
5458 };
5459
5460 trips {
5461 gpu2_alert0: trip-point0 {
5462 temperature = <85000>;
5463 hysteresis = <1000>;
5464 type = "passive";
5465 };
5466
5467 trip-point1 {
5468 temperature = <90000>;
5469 hysteresis = <1000>;
5470 type = "hot";
5471 };
5472
5473 trip-point2 {
5474 temperature = <110000>;
5475 hysteresis = <1000>;
5476 type = "critical";
5477 };
5478 };
5479 };
5480
5481 gpuss-3-thermal {
5482 polling-delay-passive = <10>;
5483
5484 thermal-sensors = <&tsens2 4>;
5485
5486 cooling-maps {
5487 map0 {
5488 trip = <&gpu3_alert0>;
5489 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5490 };
5491 };
5492
5493 trips {
5494 gpu3_alert0: trip-point0 {
5495 temperature = <85000>;
5496 hysteresis = <1000>;
5497 type = "passive";
5498 };
5499
5500 trip-point1 {
5501 temperature = <90000>;
5502 hysteresis = <1000>;
5503 type = "hot";
5504 };
5505
5506 trip-point2 {
5507 temperature = <110000>;
5508 hysteresis = <1000>;
5509 type = "critical";
5510 };
5511 };
5512 };
5513
5514 gpuss-4-thermal {
5515 polling-delay-passive = <10>;
5516
5517 thermal-sensors = <&tsens2 5>;
5518
5519 cooling-maps {
5520 map0 {
5521 trip = <&gpu4_alert0>;
5522 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5523 };
5524 };
5525
5526 trips {
5527 gpu4_alert0: trip-point0 {
5528 temperature = <85000>;
5529 hysteresis = <1000>;
5530 type = "passive";
5531 };
5532
5533 trip-point1 {
5534 temperature = <90000>;
5535 hysteresis = <1000>;
5536 type = "hot";
5537 };
5538
5539 trip-point2 {
5540 temperature = <110000>;
5541 hysteresis = <1000>;
5542 type = "critical";
5543 };
5544 };
5545 };
5546
5547 gpuss-5-thermal {
5548 polling-delay-passive = <10>;
5549
5550 thermal-sensors = <&tsens2 6>;
5551
5552 cooling-maps {
5553 map0 {
5554 trip = <&gpu5_alert0>;
5555 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5556 };
5557 };
5558
5559 trips {
5560 gpu5_alert0: trip-point0 {
5561 temperature = <85000>;
5562 hysteresis = <1000>;
5563 type = "passive";
5564 };
5565
5566 trip-point1 {
5567 temperature = <90000>;
5568 hysteresis = <1000>;
5569 type = "hot";
5570 };
5571
5572 trip-point2 {
5573 temperature = <110000>;
5574 hysteresis = <1000>;
5575 type = "critical";
5576 };
5577 };
5578 };
5579
5580 gpuss-6-thermal {
5581 polling-delay-passive = <10>;
5582
5583 thermal-sensors = <&tsens2 7>;
5584
5585 cooling-maps {
5586 map0 {
5587 trip = <&gpu6_alert0>;
5588 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5589 };
5590 };
5591
5592 trips {
5593 gpu6_alert0: trip-point0 {
5594 temperature = <85000>;
5595 hysteresis = <1000>;
5596 type = "passive";
5597 };
5598
5599 trip-point1 {
5600 temperature = <90000>;
5601 hysteresis = <1000>;
5602 type = "hot";
5603 };
5604
5605 trip-point2 {
5606 temperature = <110000>;
5607 hysteresis = <1000>;
5608 type = "critical";
5609 };
5610 };
5611 };
5612
5613 gpuss-7-thermal {
5614 polling-delay-passive = <10>;
5615
5616 thermal-sensors = <&tsens2 8>;
5617
5618 cooling-maps {
5619 map0 {
5620 trip = <&gpu7_alert0>;
5621 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5622 };
5623 };
5624
5625 trips {
5626 gpu7_alert0: trip-point0 {
5627 temperature = <85000>;
5628 hysteresis = <1000>;
5629 type = "passive";
5630 };
5631
5632 trip-point1 {
5633 temperature = <90000>;
5634 hysteresis = <1000>;
5635 type = "hot";
5636 };
5637
5638 trip-point2 {
5639 temperature = <110000>;
5640 hysteresis = <1000>;
5641 type = "critical";
5642 };
5643 };
5644 };
5645 };
5646
5647 timer {
5648 compatible = "arm,armv8-timer";
5649 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5650 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5651 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5652 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5653 };
5654 };
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