1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2023, Linaro Limited
4 */
5
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8650-camcc.h>
8 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8650-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interconnect/qcom,icc.h>
17 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/mailbox/qcom-ipcc.h>
20 #include <dt-bindings/phy/phy-qcom-qmp.h>
21 #include <dt-bindings/power/qcom,rpmhpd.h>
22 #include <dt-bindings/power/qcom-rpmpd.h>
23 #include <dt-bindings/reset/qcom,sm8650-gpucc.h>
24 #include <dt-bindings/soc/qcom,gpr.h>
25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
26 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
27 #include <dt-bindings/thermal/thermal.h>
28
29 / {
30 interrupt-parent = <&intc>;
31
32 #address-cells = <2>;
33 #size-cells = <2>;
34
35 chosen { };
36
37 clocks {
38 xo_board: xo-board {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 };
42
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 };
47
48 bi_tcxo_div2: bi-tcxo-div2-clk {
49 compatible = "fixed-factor-clock";
50 #clock-cells = <0>;
51
52 clocks = <&rpmhcc RPMH_CXO_CLK>;
53 clock-mult = <1>;
54 clock-div = <2>;
55 };
56
57 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
58 compatible = "fixed-factor-clock";
59 #clock-cells = <0>;
60
61 clocks = <&rpmhcc RPMH_CXO_CLK_A>;
62 clock-mult = <1>;
63 clock-div = <2>;
64 };
65 };
66
67 cpus {
68 #address-cells = <2>;
69 #size-cells = <0>;
70
71 CPU0: cpu@0 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a520";
74 reg = <0 0>;
75
76 clocks = <&cpufreq_hw 0>;
77
78 power-domains = <&CPU_PD0>;
79 power-domain-names = "psci";
80
81 enable-method = "psci";
82 next-level-cache = <&L2_0>;
83 capacity-dmips-mhz = <1024>;
84 dynamic-power-coefficient = <100>;
85
86 qcom,freq-domain = <&cpufreq_hw 0>;
87
88 #cooling-cells = <2>;
89
90 L2_0: l2-cache {
91 compatible = "cache";
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&L3_0>;
95
96 L3_0: l3-cache {
97 compatible = "cache";
98 cache-level = <3>;
99 cache-unified;
100 };
101 };
102 };
103
104 CPU1: cpu@100 {
105 device_type = "cpu";
106 compatible = "arm,cortex-a520";
107 reg = <0 0x100>;
108
109 clocks = <&cpufreq_hw 0>;
110
111 power-domains = <&CPU_PD1>;
112 power-domain-names = "psci";
113
114 enable-method = "psci";
115 next-level-cache = <&L2_0>;
116 capacity-dmips-mhz = <1024>;
117 dynamic-power-coefficient = <100>;
118
119 qcom,freq-domain = <&cpufreq_hw 0>;
120
121 #cooling-cells = <2>;
122 };
123
124 CPU2: cpu@200 {
125 device_type = "cpu";
126 compatible = "arm,cortex-a720";
127 reg = <0 0x200>;
128
129 clocks = <&cpufreq_hw 3>;
130
131 power-domains = <&CPU_PD2>;
132 power-domain-names = "psci";
133
134 enable-method = "psci";
135 next-level-cache = <&L2_200>;
136 capacity-dmips-mhz = <1792>;
137 dynamic-power-coefficient = <238>;
138
139 qcom,freq-domain = <&cpufreq_hw 3>;
140
141 #cooling-cells = <2>;
142
143 L2_200: l2-cache {
144 compatible = "cache";
145 cache-level = <2>;
146 cache-unified;
147 next-level-cache = <&L3_0>;
148 };
149 };
150
151 CPU3: cpu@300 {
152 device_type = "cpu";
153 compatible = "arm,cortex-a720";
154 reg = <0 0x300>;
155
156 clocks = <&cpufreq_hw 3>;
157
158 power-domains = <&CPU_PD3>;
159 power-domain-names = "psci";
160
161 enable-method = "psci";
162 next-level-cache = <&L2_200>;
163 capacity-dmips-mhz = <1792>;
164 dynamic-power-coefficient = <238>;
165
166 qcom,freq-domain = <&cpufreq_hw 3>;
167
168 #cooling-cells = <2>;
169 };
170
171 CPU4: cpu@400 {
172 device_type = "cpu";
173 compatible = "arm,cortex-a720";
174 reg = <0 0x400>;
175
176 clocks = <&cpufreq_hw 3>;
177
178 power-domains = <&CPU_PD4>;
179 power-domain-names = "psci";
180
181 enable-method = "psci";
182 next-level-cache = <&L2_400>;
183 capacity-dmips-mhz = <1792>;
184 dynamic-power-coefficient = <238>;
185
186 qcom,freq-domain = <&cpufreq_hw 3>;
187
188 #cooling-cells = <2>;
189
190 L2_400: l2-cache {
191 compatible = "cache";
192 cache-level = <2>;
193 cache-unified;
194 next-level-cache = <&L3_0>;
195 };
196 };
197
198 CPU5: cpu@500 {
199 device_type = "cpu";
200 compatible = "arm,cortex-a720";
201 reg = <0 0x500>;
202
203 clocks = <&cpufreq_hw 1>;
204
205 power-domains = <&CPU_PD5>;
206 power-domain-names = "psci";
207
208 enable-method = "psci";
209 next-level-cache = <&L2_500>;
210 capacity-dmips-mhz = <1792>;
211 dynamic-power-coefficient = <238>;
212
213 qcom,freq-domain = <&cpufreq_hw 1>;
214
215 #cooling-cells = <2>;
216
217 L2_500: l2-cache {
218 compatible = "cache";
219 cache-level = <2>;
220 cache-unified;
221 next-level-cache = <&L3_0>;
222 };
223 };
224
225 CPU6: cpu@600 {
226 device_type = "cpu";
227 compatible = "arm,cortex-a720";
228 reg = <0 0x600>;
229
230 clocks = <&cpufreq_hw 1>;
231
232 power-domains = <&CPU_PD6>;
233 power-domain-names = "psci";
234
235 enable-method = "psci";
236 next-level-cache = <&L2_600>;
237 capacity-dmips-mhz = <1792>;
238 dynamic-power-coefficient = <238>;
239
240 qcom,freq-domain = <&cpufreq_hw 1>;
241
242 #cooling-cells = <2>;
243
244 L2_600: l2-cache {
245 compatible = "cache";
246 cache-level = <2>;
247 cache-unified;
248 next-level-cache = <&L3_0>;
249 };
250 };
251
252 CPU7: cpu@700 {
253 device_type = "cpu";
254 compatible = "arm,cortex-x4";
255 reg = <0 0x700>;
256
257 clocks = <&cpufreq_hw 2>;
258
259 power-domains = <&CPU_PD7>;
260 power-domain-names = "psci";
261
262 enable-method = "psci";
263 next-level-cache = <&L2_700>;
264 capacity-dmips-mhz = <1894>;
265 dynamic-power-coefficient = <588>;
266
267 qcom,freq-domain = <&cpufreq_hw 2>;
268
269 #cooling-cells = <2>;
270
271 L2_700: l2-cache {
272 compatible = "cache";
273 cache-level = <2>;
274 cache-unified;
275 next-level-cache = <&L3_0>;
276 };
277 };
278
279 cpu-map {
280 cluster0 {
281 core0 {
282 cpu = <&CPU0>;
283 };
284
285 core1 {
286 cpu = <&CPU1>;
287 };
288
289 core2 {
290 cpu = <&CPU2>;
291 };
292
293 core3 {
294 cpu = <&CPU3>;
295 };
296
297 core4 {
298 cpu = <&CPU4>;
299 };
300
301 core5 {
302 cpu = <&CPU5>;
303 };
304
305 core6 {
306 cpu = <&CPU6>;
307 };
308
309 core7 {
310 cpu = <&CPU7>;
311 };
312 };
313 };
314
315 idle-states {
316 entry-method = "psci";
317
318 SILVER_CPU_SLEEP_0: cpu-sleep-0-0 {
319 compatible = "arm,idle-state";
320 idle-state-name = "silver-rail-power-collapse";
321 arm,psci-suspend-param = <0x40000004>;
322 entry-latency-us = <550>;
323 exit-latency-us = <750>;
324 min-residency-us = <6700>;
325 local-timer-stop;
326 };
327
328 GOLD_CPU_SLEEP_0: cpu-sleep-1-0 {
329 compatible = "arm,idle-state";
330 idle-state-name = "gold-rail-power-collapse";
331 arm,psci-suspend-param = <0x40000004>;
332 entry-latency-us = <600>;
333 exit-latency-us = <1300>;
334 min-residency-us = <8136>;
335 local-timer-stop;
336 };
337
338 GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 {
339 compatible = "arm,idle-state";
340 idle-state-name = "gold-plus-rail-power-collapse";
341 arm,psci-suspend-param = <0x40000004>;
342 entry-latency-us = <500>;
343 exit-latency-us = <1350>;
344 min-residency-us = <7480>;
345 local-timer-stop;
346 };
347 };
348
349 domain-idle-states {
350 CLUSTER_SLEEP_0: cluster-sleep-0 {
351 compatible = "domain-idle-state";
352 arm,psci-suspend-param = <0x41000044>;
353 entry-latency-us = <750>;
354 exit-latency-us = <2350>;
355 min-residency-us = <9144>;
356 };
357
358 CLUSTER_SLEEP_1: cluster-sleep-1 {
359 compatible = "domain-idle-state";
360 arm,psci-suspend-param = <0x4100c344>;
361 entry-latency-us = <2800>;
362 exit-latency-us = <4400>;
363 min-residency-us = <10150>;
364 };
365 };
366 };
367
368 firmware {
369 scm: scm {
370 compatible = "qcom,scm-sm8650", "qcom,scm";
371 qcom,dload-mode = <&tcsr 0x19000>;
372 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
373 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
374 };
375 };
376
377 clk_virt: interconnect-0 {
378 compatible = "qcom,sm8650-clk-virt";
379 #interconnect-cells = <2>;
380 qcom,bcm-voters = <&apps_bcm_voter>;
381 };
382
383 mc_virt: interconnect-1 {
384 compatible = "qcom,sm8650-mc-virt";
385 #interconnect-cells = <2>;
386 qcom,bcm-voters = <&apps_bcm_voter>;
387 };
388
389 memory@a0000000 {
390 device_type = "memory";
391 /* We expect the bootloader to fill in the size */
392 reg = <0 0xa0000000 0 0>;
393 };
394
395 pmu-a520 {
396 compatible = "arm,cortex-a520-pmu";
397 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
398 };
399
400 pmu-a720 {
401 compatible = "arm,cortex-a720-pmu";
402 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
403 };
404
405 pmu-x4 {
406 compatible = "arm,cortex-x4-pmu";
407 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
408 };
409
410 psci {
411 compatible = "arm,psci-1.0";
412 method = "smc";
413
414 CPU_PD0: power-domain-cpu0 {
415 #power-domain-cells = <0>;
416 power-domains = <&CLUSTER_PD>;
417 domain-idle-states = <&SILVER_CPU_SLEEP_0>;
418 };
419
420 CPU_PD1: power-domain-cpu1 {
421 #power-domain-cells = <0>;
422 power-domains = <&CLUSTER_PD>;
423 domain-idle-states = <&SILVER_CPU_SLEEP_0>;
424 };
425
426 CPU_PD2: power-domain-cpu2 {
427 #power-domain-cells = <0>;
428 power-domains = <&CLUSTER_PD>;
429 domain-idle-states = <&SILVER_CPU_SLEEP_0>;
430 };
431
432 CPU_PD3: power-domain-cpu3 {
433 #power-domain-cells = <0>;
434 power-domains = <&CLUSTER_PD>;
435 domain-idle-states = <&GOLD_CPU_SLEEP_0>;
436 };
437
438 CPU_PD4: power-domain-cpu4 {
439 #power-domain-cells = <0>;
440 power-domains = <&CLUSTER_PD>;
441 domain-idle-states = <&GOLD_CPU_SLEEP_0>;
442 };
443
444 CPU_PD5: power-domain-cpu5 {
445 #power-domain-cells = <0>;
446 power-domains = <&CLUSTER_PD>;
447 domain-idle-states = <&GOLD_CPU_SLEEP_0>;
448 };
449
450 CPU_PD6: power-domain-cpu6 {
451 #power-domain-cells = <0>;
452 power-domains = <&CLUSTER_PD>;
453 domain-idle-states = <&GOLD_CPU_SLEEP_0>;
454 };
455
456 CPU_PD7: power-domain-cpu7 {
457 #power-domain-cells = <0>;
458 power-domains = <&CLUSTER_PD>;
459 domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>;
460 };
461
462 CLUSTER_PD: power-domain-cluster {
463 #power-domain-cells = <0>;
464 domain-idle-states = <&CLUSTER_SLEEP_0>,
465 <&CLUSTER_SLEEP_1>;
466 };
467 };
468
469 reserved_memory: reserved-memory {
470 #address-cells = <2>;
471 #size-cells = <2>;
472 ranges;
473
474 hyp_mem: hyp@80000000 {
475 reg = <0 0x80000000 0 0xe00000>;
476 no-map;
477 };
478
479 cpusys_vm_mem: cpusys-vm@80e00000 {
480 reg = <0 0x80e00000 0 0x400000>;
481 no-map;
482 };
483
484 /* Merged xbl_dtlog, xbl_ramdump and aop_image regions */
485 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 {
486 reg = <0 0x81a00000 0 0x260000>;
487 no-map;
488 };
489
490 aop_cmd_db_mem: aop-cmd-db@81c60000 {
491 compatible = "qcom,cmd-db";
492 reg = <0 0x81c60000 0 0x20000>;
493 no-map;
494 };
495
496 /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */
497 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
498 reg = <0 0x81c80000 0 0x75000>;
499 no-map;
500 };
501
502 /* Secdata region can be reused by apps */
503
504 smem: smem@81d00000 {
505 compatible = "qcom,smem";
506 reg = <0 0x81d00000 0 0x200000>;
507 hwlocks = <&tcsr_mutex 3>;
508 no-map;
509 };
510
511 adsp_mhi_mem: adsp-mhi@81f00000 {
512 reg = <0 0x81f00000 0 0x20000>;
513 no-map;
514 };
515
516 pvmfw_mem: pvmfw@824a0000 {
517 reg = <0 0x824a0000 0 0x100000>;
518 no-map;
519 };
520
521 global_sync_mem: global-sync@82600000 {
522 reg = <0 0x82600000 0 0x100000>;
523 no-map;
524 };
525
526 tz_stat_mem: tz-stat@82700000 {
527 reg = <0 0x82700000 0 0x100000>;
528 no-map;
529 };
530
531 qdss_mem: qdss@82800000 {
532 reg = <0 0x82800000 0 0x2000000>;
533 no-map;
534 };
535
536 qlink_logging_mem: qlink-logging@84800000 {
537 reg = <0 0x84800000 0 0x200000>;
538 no-map;
539 };
540
541 mpss_dsm_mem: mpss-dsm@86b00000 {
542 reg = <0 0x86b00000 0 0x4900000>;
543 no-map;
544 };
545
546 mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
547 reg = <0 0x8b400000 0 0x800000>;
548 no-map;
549 };
550
551 mpss_mem: mpss@8bc00000 {
552 reg = <0 0x8bc00000 0 0xf400000>;
553 no-map;
554 };
555
556 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
557 reg = <0 0x9b000000 0 0x80000>;
558 no-map;
559 };
560
561 ipa_fw_mem: ipa-fw@9b080000 {
562 reg = <0 0x9b080000 0 0x10000>;
563 no-map;
564 };
565
566 ipa_gsi_mem: ipa-gsi@9b090000 {
567 reg = <0 0x9b090000 0 0xa000>;
568 no-map;
569 };
570
571 gpu_micro_code_mem: gpu-micro-code@9b09a000 {
572 reg = <0 0x9b09a000 0 0x2000>;
573 no-map;
574 };
575
576 spss_region_mem: spss@9b0a0000 {
577 reg = <0 0x9b0a0000 0 0x1e0000>;
578 no-map;
579 };
580
581 /* First part of the "SPU secure shared memory" region */
582 spu_tz_shared_mem: spu-tz-shared@9b280000 {
583 reg = <0 0x9b280000 0 0x60000>;
584 no-map;
585 };
586
587 /* Second part of the "SPU secure shared memory" region */
588 spu_modem_shared_mem: spu-modem-shared@9b2e0000 {
589 reg = <0 0x9b2e0000 0 0x20000>;
590 no-map;
591 };
592
593 camera_mem: camera@9b300000 {
594 reg = <0 0x9b300000 0 0x800000>;
595 no-map;
596 };
597
598 video_mem: video@9bb00000 {
599 reg = <0 0x9bb00000 0 0x800000>;
600 no-map;
601 };
602
603 cvp_mem: cvp@9c300000 {
604 reg = <0 0x9c300000 0 0x700000>;
605 no-map;
606 };
607
608 cdsp_mem: cdsp@9ca00000 {
609 reg = <0 0x9ca00000 0 0x1400000>;
610 no-map;
611 };
612
613 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 {
614 reg = <0 0x9de00000 0 0x80000>;
615 no-map;
616 };
617
618 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 {
619 reg = <0 0x9de80000 0 0x80000>;
620 no-map;
621 };
622
623 adspslpi_mem: adspslpi@9df00000 {
624 reg = <0 0x9df00000 0 0x4080000>;
625 no-map;
626 };
627
628 rmtfs_mem: rmtfs@d7c00000 {
629 compatible = "qcom,rmtfs-mem";
630 reg = <0 0xd7c00000 0 0x400000>;
631 no-map;
632
633 qcom,client-id = <1>;
634 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
635 };
636
637 /* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */
638 tz_merged_mem: tz-merged@d8000000 {
639 reg = <0 0xd8000000 0 0x800000>;
640 no-map;
641 };
642
643 hwfence_shbuf: hwfence-shbuf@e6440000 {
644 reg = <0 0xe6440000 0 0x2dd000>;
645 no-map;
646 };
647
648 trust_ui_vm_mem: trust-ui-vm@f3800000 {
649 reg = <0 0xf3800000 0 0x4400000>;
650 no-map;
651 };
652
653 oem_vm_mem: oem-vm@f7c00000 {
654 reg = <0 0xf7c00000 0 0x4c00000>;
655 no-map;
656 };
657
658 llcc_lpi_mem: llcc-lpi@ff800000 {
659 reg = <0 0xff800000 0 0x600000>;
660 no-map;
661 };
662 };
663
664 smp2p-adsp {
665 compatible = "qcom,smp2p";
666
667 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
668 IPCC_MPROC_SIGNAL_SMP2P
669 IRQ_TYPE_EDGE_RISING>;
670
671 mboxes = <&ipcc IPCC_CLIENT_LPASS
672 IPCC_MPROC_SIGNAL_SMP2P>;
673
674 qcom,smem = <443>, <429>;
675 qcom,local-pid = <0>;
676 qcom,remote-pid = <2>;
677
678 smp2p_adsp_out: master-kernel {
679 qcom,entry-name = "master-kernel";
680 #qcom,smem-state-cells = <1>;
681 };
682
683 smp2p_adsp_in: slave-kernel {
684 qcom,entry-name = "slave-kernel";
685 interrupt-controller;
686 #interrupt-cells = <2>;
687 };
688 };
689
690 smp2p-cdsp {
691 compatible = "qcom,smp2p";
692
693 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
694 IPCC_MPROC_SIGNAL_SMP2P
695 IRQ_TYPE_EDGE_RISING>;
696
697 mboxes = <&ipcc IPCC_CLIENT_CDSP
698 IPCC_MPROC_SIGNAL_SMP2P>;
699
700 qcom,smem = <94>, <432>;
701 qcom,local-pid = <0>;
702 qcom,remote-pid = <5>;
703
704 smp2p_cdsp_out: master-kernel {
705 qcom,entry-name = "master-kernel";
706 #qcom,smem-state-cells = <1>;
707 };
708
709 smp2p_cdsp_in: slave-kernel {
710 qcom,entry-name = "slave-kernel";
711 interrupt-controller;
712 #interrupt-cells = <2>;
713 };
714 };
715
716 smp2p-modem {
717 compatible = "qcom,smp2p";
718
719 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
720 IPCC_MPROC_SIGNAL_SMP2P
721 IRQ_TYPE_EDGE_RISING>;
722
723 mboxes = <&ipcc IPCC_CLIENT_MPSS
724 IPCC_MPROC_SIGNAL_SMP2P>;
725
726 qcom,smem = <435>, <428>;
727 qcom,local-pid = <0>;
728 qcom,remote-pid = <1>;
729
730 smp2p_modem_out: master-kernel {
731 qcom,entry-name = "master-kernel";
732 #qcom,smem-state-cells = <1>;
733 };
734
735 smp2p_modem_in: slave-kernel {
736 qcom,entry-name = "slave-kernel";
737 interrupt-controller;
738 #interrupt-cells = <2>;
739 };
740
741 ipa_smp2p_out: ipa-ap-to-modem {
742 qcom,entry-name = "ipa";
743 #qcom,smem-state-cells = <1>;
744 };
745
746 ipa_smp2p_in: ipa-modem-to-ap {
747 qcom,entry-name = "ipa";
748 interrupt-controller;
749 #interrupt-cells = <2>;
750 };
751 };
752
753 soc: soc@0 {
754 compatible = "simple-bus";
755
756 #address-cells = <2>;
757 #size-cells = <2>;
758 dma-ranges = <0 0 0 0 0x10 0>;
759 ranges = <0 0 0 0 0x10 0>;
760
761 gcc: clock-controller@100000 {
762 compatible = "qcom,sm8650-gcc";
763 reg = <0 0x00100000 0 0x1f4200>;
764
765 clocks = <&bi_tcxo_div2>,
766 <&bi_tcxo_ao_div2>,
767 <&sleep_clk>,
768 <&pcie0_phy>,
769 <&pcie1_phy QMP_PCIE_PIPE_CLK>,
770 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
771 <&ufs_mem_phy 0>,
772 <&ufs_mem_phy 1>,
773 <&ufs_mem_phy 2>,
774 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
775
776 #clock-cells = <1>;
777 #reset-cells = <1>;
778 #power-domain-cells = <1>;
779 };
780
781 ipcc: mailbox@406000 {
782 compatible = "qcom,sm8650-ipcc", "qcom,ipcc";
783 reg = <0 0x00406000 0 0x1000>;
784
785 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
786 interrupt-controller;
787 #interrupt-cells = <3>;
788
789 #mbox-cells = <2>;
790 };
791
792 gpi_dma2: dma-controller@800000 {
793 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
794 reg = <0 0x00800000 0 0x60000>;
795
796 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
797 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
798 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
799 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
800 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
801 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
808
809 dma-channels = <12>;
810 dma-channel-mask = <0x3f>;
811 #dma-cells = <3>;
812
813 iommus = <&apps_smmu 0x436 0>;
814
815 dma-coherent;
816
817 status = "disabled";
818 };
819
820 qupv3_id_1: geniqup@8c0000 {
821 compatible = "qcom,geni-se-qup";
822 reg = <0 0x008c0000 0 0x2000>;
823
824 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
825 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
826 clock-names = "m-ahb",
827 "s-ahb";
828
829 iommus = <&apps_smmu 0x423 0>;
830
831 dma-coherent;
832
833 #address-cells = <2>;
834 #size-cells = <2>;
835 ranges;
836
837 status = "disabled";
838
839 i2c8: i2c@880000 {
840 compatible = "qcom,geni-i2c";
841 reg = <0 0x00880000 0 0x4000>;
842
843 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
844
845 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
846 clock-names = "se";
847
848 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
849 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
850 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
851 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
852 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
853 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
854 interconnect-names = "qup-core",
855 "qup-config",
856 "qup-memory";
857
858 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
859 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
860 dma-names = "tx",
861 "rx";
862
863 pinctrl-0 = <&qup_i2c8_data_clk>;
864 pinctrl-names = "default";
865
866 #address-cells = <1>;
867 #size-cells = <0>;
868
869 status = "disabled";
870 };
871
872 spi8: spi@880000 {
873 compatible = "qcom,geni-spi";
874 reg = <0 0x00880000 0 0x4000>;
875
876 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
877
878 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
879 clock-names = "se";
880
881 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
882 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
883 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
884 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
885 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
886 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
887 interconnect-names = "qup-core",
888 "qup-config",
889 "qup-memory";
890
891 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
892 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
893 dma-names = "tx",
894 "rx";
895
896 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
897 pinctrl-names = "default";
898
899 #address-cells = <1>;
900 #size-cells = <0>;
901
902 status = "disabled";
903 };
904
905 i2c9: i2c@884000 {
906 compatible = "qcom,geni-i2c";
907 reg = <0 0x00884000 0 0x4000>;
908
909 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
910
911 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
912 clock-names = "se";
913
914 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
915 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
916 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
917 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
918 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
919 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
920 interconnect-names = "qup-core",
921 "qup-config",
922 "qup-memory";
923
924 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
925 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
926 dma-names = "tx",
927 "rx";
928
929 pinctrl-0 = <&qup_i2c9_data_clk>;
930 pinctrl-names = "default";
931
932 #address-cells = <1>;
933 #size-cells = <0>;
934
935 status = "disabled";
936 };
937
938 spi9: spi@884000 {
939 compatible = "qcom,geni-spi";
940 reg = <0 0x00884000 0 0x4000>;
941
942 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
943
944 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
945 clock-names = "se";
946
947 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
948 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
949 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
950 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
951 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
953 interconnect-names = "qup-core",
954 "qup-config",
955 "qup-memory";
956
957 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
958 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
959 dma-names = "tx",
960 "rx";
961
962 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
963 pinctrl-names = "default";
964
965 #address-cells = <1>;
966 #size-cells = <0>;
967
968 status = "disabled";
969 };
970
971 i2c10: i2c@888000 {
972 compatible = "qcom,geni-i2c";
973 reg = <0 0x00888000 0 0x4000>;
974
975 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
976
977 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
978 clock-names = "se";
979
980 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
981 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
982 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
983 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
984 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
985 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
986 interconnect-names = "qup-core",
987 "qup-config",
988 "qup-memory";
989
990 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
991 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
992 dma-names = "tx",
993 "rx";
994
995 pinctrl-0 = <&qup_i2c10_data_clk>;
996 pinctrl-names = "default";
997
998 #address-cells = <1>;
999 #size-cells = <0>;
1000
1001 status = "disabled";
1002 };
1003
1004 spi10: spi@888000 {
1005 compatible = "qcom,geni-spi";
1006 reg = <0 0x00888000 0 0x4000>;
1007
1008 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1009
1010 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1011 clock-names = "se";
1012
1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1014 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1015 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1016 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1017 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1018 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1019 interconnect-names = "qup-core",
1020 "qup-config",
1021 "qup-memory";
1022
1023 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1024 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1025 dma-names = "tx",
1026 "rx";
1027
1028 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1029 pinctrl-names = "default";
1030
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1033
1034 status = "disabled";
1035 };
1036
1037 i2c11: i2c@88c000 {
1038 compatible = "qcom,geni-i2c";
1039 reg = <0 0x0088c000 0 0x4000>;
1040
1041 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1042
1043 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1044 clock-names = "se";
1045
1046 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1047 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1048 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1049 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1050 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1051 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1052 interconnect-names = "qup-core",
1053 "qup-config",
1054 "qup-memory";
1055
1056 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1057 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1058 dma-names = "tx",
1059 "rx";
1060
1061 pinctrl-0 = <&qup_i2c11_data_clk>;
1062 pinctrl-names = "default";
1063
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1066
1067 status = "disabled";
1068 };
1069
1070 spi11: spi@88c000 {
1071 compatible = "qcom,geni-spi";
1072 reg = <0 0x0088c000 0 0x4000>;
1073
1074 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1075
1076 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1077 clock-names = "se";
1078
1079 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1080 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1081 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1082 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1083 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1084 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1085 interconnect-names = "qup-core",
1086 "qup-config",
1087 "qup-memory";
1088
1089 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1090 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1091 dma-names = "tx",
1092 "rx";
1093
1094 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1095 pinctrl-names = "default";
1096
1097 #address-cells = <1>;
1098 #size-cells = <0>;
1099
1100 status = "disabled";
1101 };
1102
1103 i2c12: i2c@890000 {
1104 compatible = "qcom,geni-i2c";
1105 reg = <0 0x00890000 0 0x4000>;
1106
1107 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1108
1109 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1110 clock-names = "se";
1111
1112 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1113 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1114 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1115 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1116 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1117 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1118 interconnect-names = "qup-core",
1119 "qup-config",
1120 "qup-memory";
1121
1122 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1123 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1124 dma-names = "tx",
1125 "rx";
1126
1127 pinctrl-0 = <&qup_i2c12_data_clk>;
1128 pinctrl-names = "default";
1129
1130 #address-cells = <1>;
1131 #size-cells = <0>;
1132
1133 status = "disabled";
1134 };
1135
1136 spi12: spi@890000 {
1137 compatible = "qcom,geni-spi";
1138 reg = <0 0x00890000 0 0x4000>;
1139
1140 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1141
1142 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1143 clock-names = "se";
1144
1145 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1146 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1147 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1148 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1149 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1150 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1151 interconnect-names = "qup-core",
1152 "qup-config",
1153 "qup-memory";
1154
1155 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1156 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1157 dma-names = "tx",
1158 "rx";
1159
1160 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1161 pinctrl-names = "default";
1162
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1165
1166 status = "disabled";
1167 };
1168
1169 i2c13: i2c@894000 {
1170 compatible = "qcom,geni-i2c";
1171 reg = <0 0x00894000 0 0x4000>;
1172
1173 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1174
1175 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1176 clock-names = "se";
1177
1178 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1179 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1180 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1181 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1182 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1183 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1184 interconnect-names = "qup-core",
1185 "qup-config",
1186 "qup-memory";
1187
1188 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1189 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1190 dma-names = "tx",
1191 "rx";
1192
1193 pinctrl-0 = <&qup_i2c13_data_clk>;
1194 pinctrl-names = "default";
1195
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1198
1199 status = "disabled";
1200 };
1201
1202 spi13: spi@894000 {
1203 compatible = "qcom,geni-spi";
1204 reg = <0 0x00894000 0 0x4000>;
1205
1206 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1207
1208 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1209 clock-names = "se";
1210
1211 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1212 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1213 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1214 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1215 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1216 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1217 interconnect-names = "qup-core",
1218 "qup-config",
1219 "qup-memory";
1220
1221 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1222 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1223 dma-names = "tx",
1224 "rx";
1225
1226 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1227 pinctrl-names = "default";
1228
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1231
1232 status = "disabled";
1233 };
1234
1235 uart14: serial@898000 {
1236 compatible = "qcom,geni-uart";
1237 reg = <0 0x00898000 0 0x4000>;
1238
1239 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1240
1241 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1242 clock-names = "se";
1243
1244 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1245 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1246 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1247 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1248 interconnect-names = "qup-core",
1249 "qup-config";
1250
1251 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1252 pinctrl-names = "default";
1253
1254 status = "disabled";
1255 };
1256
1257 uart15: serial@89c000 {
1258 compatible = "qcom,geni-debug-uart";
1259 reg = <0 0x0089c000 0 0x4000>;
1260
1261 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1262
1263 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1264 clock-names = "se";
1265
1266 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1267 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1268 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1269 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1270 interconnect-names = "qup-core",
1271 "qup-config";
1272
1273 pinctrl-0 = <&qup_uart15_default>;
1274 pinctrl-names = "default";
1275
1276 status = "disabled";
1277 };
1278 };
1279
1280 i2c_master_hub_0: geniqup@9c0000 {
1281 compatible = "qcom,geni-se-i2c-master-hub";
1282 reg = <0 0x009c0000 0 0x2000>;
1283
1284 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
1285 clock-names = "s-ahb";
1286
1287 #address-cells = <2>;
1288 #size-cells = <2>;
1289 ranges;
1290
1291 status = "disabled";
1292
1293 i2c_hub_0: i2c@980000 {
1294 compatible = "qcom,geni-i2c-master-hub";
1295 reg = <0 0x00980000 0 0x4000>;
1296
1297 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
1298
1299 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
1300 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1301 clock-names = "se",
1302 "core";
1303
1304 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1305 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1306 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1307 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
1308 interconnect-names = "qup-core",
1309 "qup-config";
1310
1311 pinctrl-0 = <&hub_i2c0_data_clk>;
1312 pinctrl-names = "default";
1313
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1316
1317 status = "disabled";
1318 };
1319
1320 i2c_hub_1: i2c@984000 {
1321 compatible = "qcom,geni-i2c-master-hub";
1322 reg = <0 0x00984000 0 0x4000>;
1323
1324 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
1325
1326 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
1327 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1328 clock-names = "se",
1329 "core";
1330
1331 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1332 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1333 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1334 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
1335 interconnect-names = "qup-core",
1336 "qup-config";
1337
1338 pinctrl-0 = <&hub_i2c1_data_clk>;
1339 pinctrl-names = "default";
1340
1341 #address-cells = <1>;
1342 #size-cells = <0>;
1343
1344 status = "disabled";
1345 };
1346
1347 i2c_hub_2: i2c@988000 {
1348 compatible = "qcom,geni-i2c-master-hub";
1349 reg = <0 0x00988000 0 0x4000>;
1350
1351 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1352
1353 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
1354 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1355 clock-names = "se",
1356 "core";
1357
1358 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1359 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1360 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1361 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
1362 interconnect-names = "qup-core",
1363 "qup-config";
1364
1365 pinctrl-0 = <&hub_i2c2_data_clk>;
1366 pinctrl-names = "default";
1367
1368 #address-cells = <1>;
1369 #size-cells = <0>;
1370
1371 status = "disabled";
1372 };
1373
1374 i2c_hub_3: i2c@98c000 {
1375 compatible = "qcom,geni-i2c-master-hub";
1376 reg = <0 0x0098c000 0 0x4000>;
1377
1378 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1379
1380 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
1381 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1382 clock-names = "se",
1383 "core";
1384
1385 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1386 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1388 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
1389 interconnect-names = "qup-core",
1390 "qup-config";
1391
1392 pinctrl-0 = <&hub_i2c3_data_clk>;
1393 pinctrl-names = "default";
1394
1395 #address-cells = <1>;
1396 #size-cells = <0>;
1397
1398 status = "disabled";
1399 };
1400
1401 i2c_hub_4: i2c@990000 {
1402 compatible = "qcom,geni-i2c-master-hub";
1403 reg = <0 0x00990000 0 0x4000>;
1404
1405 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
1406
1407 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
1408 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1409 clock-names = "se",
1410 "core";
1411
1412 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1413 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1414 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1415 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
1416 interconnect-names = "qup-core",
1417 "qup-config";
1418
1419 pinctrl-0 = <&hub_i2c4_data_clk>;
1420 pinctrl-names = "default";
1421
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1424
1425 status = "disabled";
1426 };
1427
1428 i2c_hub_5: i2c@994000 {
1429 compatible = "qcom,geni-i2c-master-hub";
1430 reg = <0 0x00994000 0 0x4000>;
1431
1432 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
1433
1434 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
1435 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1436 clock-names = "se",
1437 "core";
1438
1439 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1440 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1441 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1442 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
1443 interconnect-names = "qup-core",
1444 "qup-config";
1445
1446 pinctrl-0 = <&hub_i2c5_data_clk>;
1447 pinctrl-names = "default";
1448
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1451
1452 status = "disabled";
1453 };
1454
1455 i2c_hub_6: i2c@998000 {
1456 compatible = "qcom,geni-i2c-master-hub";
1457 reg = <0 0x00998000 0 0x4000>;
1458
1459 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
1460
1461 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
1462 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1463 clock-names = "se",
1464 "core";
1465
1466 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1467 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1468 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1469 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
1470 interconnect-names = "qup-core",
1471 "qup-config";
1472
1473 pinctrl-0 = <&hub_i2c6_data_clk>;
1474 pinctrl-names = "default";
1475
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1478
1479 status = "disabled";
1480 };
1481
1482 i2c_hub_7: i2c@99c000 {
1483 compatible = "qcom,geni-i2c-master-hub";
1484 reg = <0 0x0099c000 0 0x4000>;
1485
1486 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
1487
1488 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
1489 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1490 clock-names = "se",
1491 "core";
1492
1493 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1494 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1495 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1496 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
1497 interconnect-names = "qup-core",
1498 "qup-config";
1499
1500 pinctrl-0 = <&hub_i2c7_data_clk>;
1501 pinctrl-names = "default";
1502
1503 #address-cells = <1>;
1504 #size-cells = <0>;
1505
1506 status = "disabled";
1507 };
1508
1509 i2c_hub_8: i2c@9a0000 {
1510 compatible = "qcom,geni-i2c-master-hub";
1511 reg = <0 0x009a0000 0 0x4000>;
1512
1513 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
1514
1515 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
1516 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1517 clock-names = "se",
1518 "core";
1519
1520 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1521 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1522 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1523 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
1524 interconnect-names = "qup-core",
1525 "qup-config";
1526
1527 pinctrl-0 = <&hub_i2c8_data_clk>;
1528 pinctrl-names = "default";
1529
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1532
1533 status = "disabled";
1534 };
1535
1536 i2c_hub_9: i2c@9a4000 {
1537 compatible = "qcom,geni-i2c-master-hub";
1538 reg = <0 0x009a4000 0 0x4000>;
1539
1540 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
1541
1542 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
1543 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1544 clock-names = "se",
1545 "core";
1546
1547 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1548 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1549 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1550 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
1551 interconnect-names = "qup-core",
1552 "qup-config";
1553
1554 pinctrl-0 = <&hub_i2c9_data_clk>;
1555 pinctrl-names = "default";
1556
1557 #address-cells = <1>;
1558 #size-cells = <0>;
1559
1560 status = "disabled";
1561 };
1562 };
1563
1564 gpi_dma1: dma-controller@a00000 {
1565 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
1566 reg = <0 0x00a00000 0 0x60000>;
1567
1568 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1569 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1570 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1571 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1572 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1573 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1574 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1575 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1576 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1577 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1578 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1579 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1580
1581 dma-channels = <12>;
1582 dma-channel-mask = <0xc>;
1583 #dma-cells = <3>;
1584
1585 iommus = <&apps_smmu 0xb6 0>;
1586 dma-coherent;
1587
1588 status = "disabled";
1589 };
1590
1591 qupv3_id_0: geniqup@ac0000 {
1592 compatible = "qcom,geni-se-qup";
1593 reg = <0 0x00ac0000 0 0x2000>;
1594
1595 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1596 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1597 clock-names = "m-ahb",
1598 "s-ahb";
1599
1600 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1601 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>;
1602 interconnect-names = "qup-core";
1603
1604 iommus = <&apps_smmu 0xa3 0>;
1605
1606 dma-coherent;
1607
1608 #address-cells = <2>;
1609 #size-cells = <2>;
1610 ranges;
1611
1612 status = "disabled";
1613
1614 i2c0: i2c@a80000 {
1615 compatible = "qcom,geni-i2c";
1616 reg = <0 0x00a80000 0 0x4000>;
1617
1618 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1619
1620 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1621 clock-names = "se";
1622
1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1624 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1625 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1626 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1627 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1628 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1629 interconnect-names = "qup-core",
1630 "qup-config",
1631 "qup-memory";
1632
1633 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1634 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1635 dma-names = "tx",
1636 "rx";
1637
1638 pinctrl-0 = <&qup_i2c0_data_clk>;
1639 pinctrl-names = "default";
1640
1641 #address-cells = <1>;
1642 #size-cells = <0>;
1643
1644 status = "disabled";
1645 };
1646
1647 spi0: spi@a80000 {
1648 compatible = "qcom,geni-spi";
1649 reg = <0 0x00a80000 0 0x4000>;
1650
1651 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1652
1653 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1654 clock-names = "se";
1655
1656 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1657 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1658 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1659 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1660 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1661 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1662 interconnect-names = "qup-core",
1663 "qup-config",
1664 "qup-memory";
1665
1666 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1667 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1668 dma-names = "tx",
1669 "rx";
1670
1671 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1672 pinctrl-names = "default";
1673
1674 #address-cells = <1>;
1675 #size-cells = <0>;
1676
1677 status = "disabled";
1678 };
1679
1680 i2c1: i2c@a84000 {
1681 compatible = "qcom,geni-i2c";
1682 reg = <0 0x00a84000 0 0x4000>;
1683
1684 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1685
1686 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1687 clock-names = "se";
1688
1689 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1690 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1691 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1692 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1693 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1694 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1695 interconnect-names = "qup-core",
1696 "qup-config",
1697 "qup-memory";
1698
1699 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1700 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1701 dma-names = "tx",
1702 "rx";
1703
1704 pinctrl-0 = <&qup_i2c1_data_clk>;
1705 pinctrl-names = "default";
1706
1707 #address-cells = <1>;
1708 #size-cells = <0>;
1709
1710 status = "disabled";
1711 };
1712
1713 spi1: spi@a84000 {
1714 compatible = "qcom,geni-spi";
1715 reg = <0 0x00a84000 0 0x4000>;
1716
1717 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1718
1719 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1720 clock-names = "se";
1721
1722 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1723 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1724 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1725 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1726 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1727 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1728 interconnect-names = "qup-core",
1729 "qup-config",
1730 "qup-memory";
1731
1732 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1733 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1734 dma-names = "tx",
1735 "rx";
1736
1737 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1738 pinctrl-names = "default";
1739
1740 #address-cells = <1>;
1741 #size-cells = <0>;
1742
1743 status = "disabled";
1744 };
1745
1746 i2c2: i2c@a88000 {
1747 compatible = "qcom,geni-i2c";
1748 reg = <0 0x00a88000 0 0x4000>;
1749
1750 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1751
1752 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1753 clock-names = "se";
1754
1755 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1756 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1757 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1758 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1759 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1760 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1761 interconnect-names = "qup-core",
1762 "qup-config",
1763 "qup-memory";
1764
1765 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1766 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1767 dma-names = "tx",
1768 "rx";
1769
1770 pinctrl-0 = <&qup_i2c2_data_clk>;
1771 pinctrl-names = "default";
1772
1773 #address-cells = <1>;
1774 #size-cells = <0>;
1775
1776 status = "disabled";
1777 };
1778
1779 spi2: spi@a88000 {
1780 compatible = "qcom,geni-spi";
1781 reg = <0 0x00a88000 0 0x4000>;
1782
1783 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1784
1785 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1786 clock-names = "se";
1787
1788 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1789 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1790 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1791 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1792 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1793 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1794 interconnect-names = "qup-core",
1795 "qup-config",
1796 "qup-memory";
1797
1798 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1799 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1800 dma-names = "tx",
1801 "rx";
1802
1803 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1804 pinctrl-names = "default";
1805
1806 #address-cells = <1>;
1807 #size-cells = <0>;
1808
1809 status = "disabled";
1810 };
1811
1812 i2c3: i2c@a8c000 {
1813 compatible = "qcom,geni-i2c";
1814 reg = <0 0x00a8c000 0 0x4000>;
1815
1816 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1817
1818 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1819 clock-names = "se";
1820
1821 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1822 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1823 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1824 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1825 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1826 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1827 interconnect-names = "qup-core",
1828 "qup-config",
1829 "qup-memory";
1830
1831 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1832 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1833 dma-names = "tx",
1834 "rx";
1835
1836 pinctrl-0 = <&qup_i2c3_data_clk>;
1837 pinctrl-names = "default";
1838
1839 #address-cells = <1>;
1840 #size-cells = <0>;
1841
1842 status = "disabled";
1843 };
1844
1845 spi3: spi@a8c000 {
1846 compatible = "qcom,geni-spi";
1847 reg = <0 0x00a8c000 0 0x4000>;
1848
1849 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1850
1851 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1852 clock-names = "se";
1853
1854 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1855 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1856 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1857 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1858 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1859 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1860 interconnect-names = "qup-core",
1861 "qup-config",
1862 "qup-memory";
1863
1864 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1865 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1866 dma-names = "tx",
1867 "rx";
1868
1869 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1870 pinctrl-names = "default";
1871
1872 #address-cells = <1>;
1873 #size-cells = <0>;
1874
1875 status = "disabled";
1876 };
1877
1878 i2c4: i2c@a90000 {
1879 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00a90000 0 0x4000>;
1881
1882 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1883
1884 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1885 clock-names = "se";
1886
1887 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1888 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1889 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1890 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1891 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1892 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1893 interconnect-names = "qup-core",
1894 "qup-config",
1895 "qup-memory";
1896
1897 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1898 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1899 dma-names = "tx",
1900 "rx";
1901
1902 pinctrl-0 = <&qup_i2c4_data_clk>;
1903 pinctrl-names = "default";
1904
1905 #address-cells = <1>;
1906 #size-cells = <0>;
1907
1908 status = "disabled";
1909 };
1910
1911 spi4: spi@a90000 {
1912 compatible = "qcom,geni-spi";
1913 reg = <0 0x00a90000 0 0x4000>;
1914
1915 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1916
1917 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1918 clock-names = "se";
1919
1920 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1921 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1922 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1923 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1924 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1926 interconnect-names = "qup-core",
1927 "qup-config",
1928 "qup-memory";
1929
1930 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1931 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1932 dma-names = "tx",
1933 "rx";
1934
1935 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1936 pinctrl-names = "default";
1937
1938 #address-cells = <1>;
1939 #size-cells = <0>;
1940
1941 status = "disabled";
1942 };
1943
1944 i2c5: i2c@a94000 {
1945 compatible = "qcom,geni-i2c";
1946 reg = <0 0x00a94000 0 0x4000>;
1947
1948 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1949
1950 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1951 clock-names = "se";
1952
1953 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1954 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1955 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1956 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1957 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1958 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1959 interconnect-names = "qup-core",
1960 "qup-config",
1961 "qup-memory";
1962
1963 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1964 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1965 dma-names = "tx",
1966 "rx";
1967
1968 pinctrl-0 = <&qup_i2c5_data_clk>;
1969 pinctrl-names = "default";
1970
1971 #address-cells = <1>;
1972 #size-cells = <0>;
1973
1974 status = "disabled";
1975 };
1976
1977 spi5: spi@a94000 {
1978 compatible = "qcom,geni-spi";
1979 reg = <0 0x00a94000 0 0x4000>;
1980
1981 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1982
1983 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1984 clock-names = "se";
1985
1986 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1987 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1988 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1989 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1990 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1991 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1992 interconnect-names = "qup-core",
1993 "qup-config",
1994 "qup-memory";
1995
1996 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1997 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1998 dma-names = "tx",
1999 "rx";
2000
2001 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2002 pinctrl-names = "default";
2003
2004 #address-cells = <1>;
2005 #size-cells = <0>;
2006
2007 status = "disabled";
2008 };
2009
2010 i2c6: i2c@a98000 {
2011 compatible = "qcom,geni-i2c";
2012 reg = <0 0x00a98000 0 0x4000>;
2013
2014 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
2015
2016 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2017 clock-names = "se";
2018
2019 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
2020 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
2021 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2022 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
2023 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
2024 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2025 interconnect-names = "qup-core",
2026 "qup-config",
2027 "qup-memory";
2028
2029 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2030 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2031 dma-names = "tx",
2032 "rx";
2033
2034 pinctrl-0 = <&qup_i2c6_data_clk>;
2035 pinctrl-names = "default";
2036
2037 #address-cells = <1>;
2038 #size-cells = <0>;
2039
2040 status = "disabled";
2041 };
2042
2043 spi6: spi@a98000 {
2044 compatible = "qcom,geni-spi";
2045 reg = <0 0x00a98000 0 0x4000>;
2046
2047 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
2048
2049 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2050 clock-names = "se";
2051
2052 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
2053 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
2054 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2055 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
2056 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
2057 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2058 interconnect-names = "qup-core",
2059 "qup-config",
2060 "qup-memory";
2061
2062 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2063 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2064 dma-names = "tx",
2065 "rx";
2066
2067 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2068 pinctrl-names = "default";
2069
2070 #address-cells = <1>;
2071 #size-cells = <0>;
2072
2073 status = "disabled";
2074 };
2075
2076 i2c7: i2c@a9c000 {
2077 compatible = "qcom,geni-i2c";
2078 reg = <0 0x00a9c000 0 0x4000>;
2079
2080 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
2081
2082 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2083 clock-names = "se";
2084
2085 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
2086 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
2087 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2088 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
2089 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
2090 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2091 interconnect-names = "qup-core",
2092 "qup-config",
2093 "qup-memory";
2094
2095 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2096 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2097 dma-names = "tx",
2098 "rx";
2099
2100 pinctrl-0 = <&qup_i2c7_data_clk>;
2101 pinctrl-names = "default";
2102
2103 #address-cells = <1>;
2104 #size-cells = <0>;
2105
2106 status = "disabled";
2107 };
2108
2109 spi7: spi@a9c000 {
2110 compatible = "qcom,geni-spi";
2111 reg = <0 0x00a9c000 0 0x4000>;
2112
2113 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
2114
2115 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2116 clock-names = "se";
2117
2118 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
2119 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
2120 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2121 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
2122 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
2123 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2124 interconnect-names = "qup-core",
2125 "qup-config",
2126 "qup-memory";
2127
2128 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2129 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2130 dma-names = "tx",
2131 "rx";
2132
2133 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2134 pinctrl-names = "default";
2135
2136 #address-cells = <1>;
2137 #size-cells = <0>;
2138
2139 status = "disabled";
2140 };
2141 };
2142
2143 cnoc_main: interconnect@1500000 {
2144 compatible = "qcom,sm8650-cnoc-main";
2145 reg = <0 0x01500000 0 0x14080>;
2146
2147 qcom,bcm-voters = <&apps_bcm_voter>;
2148
2149 #interconnect-cells = <2>;
2150 };
2151
2152 config_noc: interconnect@1600000 {
2153 compatible = "qcom,sm8650-config-noc";
2154 reg = <0 0x01600000 0 0x6200>;
2155
2156 qcom,bcm-voters = <&apps_bcm_voter>;
2157
2158 #interconnect-cells = <2>;
2159 };
2160
2161 system_noc: interconnect@1680000 {
2162 compatible = "qcom,sm8650-system-noc";
2163 reg = <0 0x01680000 0 0x1d080>;
2164
2165 qcom,bcm-voters = <&apps_bcm_voter>;
2166
2167 #interconnect-cells = <2>;
2168 };
2169
2170 pcie_noc: interconnect@16c0000 {
2171 compatible = "qcom,sm8650-pcie-anoc";
2172 reg = <0 0x016c0000 0 0x12200>;
2173
2174 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
2175 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
2176
2177 qcom,bcm-voters = <&apps_bcm_voter>;
2178
2179 #interconnect-cells = <2>;
2180 };
2181
2182 aggre1_noc: interconnect@16e0000 {
2183 compatible = "qcom,sm8650-aggre1-noc";
2184 reg = <0 0x016e0000 0 0x16400>;
2185
2186 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2187 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2188
2189 qcom,bcm-voters = <&apps_bcm_voter>;
2190
2191 #interconnect-cells = <2>;
2192 };
2193
2194 aggre2_noc: interconnect@1700000 {
2195 compatible = "qcom,sm8650-aggre2-noc";
2196 reg = <0 0x01700000 0 0x1e400>;
2197
2198 clocks = <&rpmhcc RPMH_IPA_CLK>;
2199
2200 qcom,bcm-voters = <&apps_bcm_voter>;
2201
2202 #interconnect-cells = <2>;
2203 };
2204
2205 mmss_noc: interconnect@1780000 {
2206 compatible = "qcom,sm8650-mmss-noc";
2207 reg = <0 0x01780000 0 0x5b800>;
2208
2209 qcom,bcm-voters = <&apps_bcm_voter>;
2210
2211 #interconnect-cells = <2>;
2212 };
2213
2214 rng: rng@10c3000 {
2215 compatible = "qcom,sm8650-trng", "qcom,trng";
2216 reg = <0 0x010c3000 0 0x1000>;
2217 };
2218
2219 pcie0: pcie@1c00000 {
2220 device_type = "pci";
2221 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
2222 reg = <0 0x01c00000 0 0x3000>,
2223 <0 0x60000000 0 0xf1d>,
2224 <0 0x60000f20 0 0xa8>,
2225 <0 0x60001000 0 0x1000>,
2226 <0 0x60100000 0 0x100000>;
2227 reg-names = "parf", "dbi", "elbi", "atu", "config";
2228
2229 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2230 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2231 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2232 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2233 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2234 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2235 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2236 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2237 interrupt-names = "msi0",
2238 "msi1",
2239 "msi2",
2240 "msi3",
2241 "msi4",
2242 "msi5",
2243 "msi6",
2244 "msi7";
2245
2246 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
2247 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2248 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2249 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2250 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2251 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
2252 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
2253 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
2254 clock-names = "aux",
2255 "cfg",
2256 "bus_master",
2257 "bus_slave",
2258 "slave_q2a",
2259 "ddrss_sf_tbu",
2260 "noc_aggr",
2261 "cnoc_sf_axi";
2262
2263 resets = <&gcc GCC_PCIE_0_BCR>;
2264 reset-names = "pci";
2265
2266 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
2267 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
2268 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2269 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
2270 interconnect-names = "pcie-mem",
2271 "cpu-pcie";
2272
2273 power-domains = <&gcc PCIE_0_GDSC>;
2274
2275 iommu-map = <0 &apps_smmu 0x1400 0x1>,
2276 <0x100 &apps_smmu 0x1401 0x1>;
2277
2278 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
2279 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
2280 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
2281 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
2282 interrupt-map-mask = <0 0 0 0x7>;
2283 #interrupt-cells = <1>;
2284
2285 msi-map = <0x0 &gic_its 0x1400 0x1>,
2286 <0x100 &gic_its 0x1401 0x1>;
2287 msi-map-mask = <0xff00>;
2288
2289 linux,pci-domain = <0>;
2290 num-lanes = <2>;
2291 bus-range = <0 0xff>;
2292
2293 phys = <&pcie0_phy>;
2294 phy-names = "pciephy";
2295
2296 #address-cells = <3>;
2297 #size-cells = <2>;
2298 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>,
2299 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>;
2300
2301 dma-coherent;
2302
2303 status = "disabled";
2304
2305 pcieport0: pcie@0 {
2306 device_type = "pci";
2307 reg = <0x0 0x0 0x0 0x0 0x0>;
2308 bus-range = <0x01 0xff>;
2309
2310 #address-cells = <3>;
2311 #size-cells = <2>;
2312 ranges;
2313 };
2314 };
2315
2316 pcie0_phy: phy@1c06000 {
2317 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy";
2318 reg = <0 0x01c06000 0 0x2000>;
2319
2320 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
2321 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2322 <&tcsr TCSR_PCIE_0_CLKREF_EN>,
2323 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
2324 <&gcc GCC_PCIE_0_PIPE_CLK>;
2325 clock-names = "aux",
2326 "cfg_ahb",
2327 "ref",
2328 "rchng",
2329 "pipe";
2330
2331 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
2332 assigned-clock-rates = <100000000>;
2333
2334 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2335 reset-names = "phy";
2336
2337 power-domains = <&gcc PCIE_0_PHY_GDSC>;
2338
2339 #clock-cells = <0>;
2340 clock-output-names = "pcie0_pipe_clk";
2341
2342 #phy-cells = <0>;
2343
2344 status = "disabled";
2345 };
2346
2347 pcie1: pcie@1c08000 {
2348 device_type = "pci";
2349 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
2350 reg = <0 0x01c08000 0 0x3000>,
2351 <0 0x40000000 0 0xf1d>,
2352 <0 0x40000f20 0 0xa8>,
2353 <0 0x40001000 0 0x1000>,
2354 <0 0x40100000 0 0x100000>;
2355 reg-names = "parf",
2356 "dbi",
2357 "elbi",
2358 "atu",
2359 "config";
2360
2361 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2362 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2363 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
2364 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
2365 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2369 interrupt-names = "msi0",
2370 "msi1",
2371 "msi2",
2372 "msi3",
2373 "msi4",
2374 "msi5",
2375 "msi6",
2376 "msi7";
2377
2378 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2379 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2380 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2381 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2382 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2383 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
2384 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
2385 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
2386 clock-names = "aux",
2387 "cfg",
2388 "bus_master",
2389 "bus_slave",
2390 "slave_q2a",
2391 "ddrss_sf_tbu",
2392 "noc_aggr",
2393 "cnoc_sf_axi";
2394
2395 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2396 assigned-clock-rates = <19200000>;
2397
2398 resets = <&gcc GCC_PCIE_1_BCR>,
2399 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
2400 reset-names = "pci",
2401 "link_down";
2402
2403 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
2404 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
2405 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2406 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>;
2407 interconnect-names = "pcie-mem",
2408 "cpu-pcie";
2409
2410 power-domains = <&gcc PCIE_1_GDSC>;
2411
2412 iommu-map = <0 &apps_smmu 0x1480 0x1>,
2413 <0x100 &apps_smmu 0x1481 0x1>;
2414
2415 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2416 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2417 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2418 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2419 interrupt-map-mask = <0 0 0 0x7>;
2420 #interrupt-cells = <1>;
2421
2422 msi-map = <0x0 &gic_its 0x1480 0x1>,
2423 <0x100 &gic_its 0x1481 0x1>;
2424 msi-map-mask = <0xff00>;
2425
2426 linux,pci-domain = <1>;
2427 num-lanes = <2>;
2428 bus-range = <0 0xff>;
2429
2430 phys = <&pcie1_phy>;
2431 phy-names = "pciephy";
2432
2433 dma-coherent;
2434
2435 #address-cells = <3>;
2436 #size-cells = <2>;
2437 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>,
2438 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>;
2439
2440 status = "disabled";
2441
2442 pcie@0 {
2443 device_type = "pci";
2444 reg = <0x0 0x0 0x0 0x0 0x0>;
2445 bus-range = <0x01 0xff>;
2446
2447 #address-cells = <3>;
2448 #size-cells = <2>;
2449 ranges;
2450 };
2451 };
2452
2453 pcie1_phy: phy@1c0e000 {
2454 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy";
2455 reg = <0 0x01c0e000 0 0x2000>;
2456
2457 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
2458 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2459 <&tcsr TCSR_PCIE_1_CLKREF_EN>,
2460 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
2461 <&gcc GCC_PCIE_1_PIPE_CLK>;
2462 clock-names = "aux",
2463 "cfg_ahb",
2464 "ref",
2465 "rchng",
2466 "pipe";
2467
2468 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2469 assigned-clock-rates = <100000000>;
2470
2471 resets = <&gcc GCC_PCIE_1_PHY_BCR>,
2472 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
2473 reset-names = "phy",
2474 "phy_nocsr";
2475
2476 power-domains = <&gcc PCIE_1_PHY_GDSC>;
2477
2478 #clock-cells = <1>;
2479 clock-output-names = "pcie1_pipe_clk";
2480
2481 #phy-cells = <0>;
2482
2483 status = "disabled";
2484 };
2485
2486 cryptobam: dma-controller@1dc4000 {
2487 compatible = "qcom,bam-v1.7.0";
2488 reg = <0 0x01dc4000 0 0x28000>;
2489
2490 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2491
2492 #dma-cells = <1>;
2493
2494 iommus = <&apps_smmu 0x480 0>,
2495 <&apps_smmu 0x481 0>;
2496
2497 qcom,ee = <0>;
2498 qcom,controlled-remotely;
2499 };
2500
2501 crypto: crypto@1dfa000 {
2502 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
2503 reg = <0 0x01dfa000 0 0x6000>;
2504
2505 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
2506 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2507 interconnect-names = "memory";
2508
2509 dmas = <&cryptobam 4>, <&cryptobam 5>;
2510 dma-names = "rx", "tx";
2511
2512 iommus = <&apps_smmu 0x480 0>,
2513 <&apps_smmu 0x481 0>;
2514 };
2515
2516 ufs_mem_phy: phy@1d80000 {
2517 compatible = "qcom,sm8650-qmp-ufs-phy";
2518 reg = <0 0x01d80000 0 0x2000>;
2519
2520 clocks = <&rpmhcc RPMH_CXO_CLK>,
2521 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2522 <&tcsr TCSR_UFS_CLKREF_EN>;
2523 clock-names = "ref",
2524 "ref_aux",
2525 "qref";
2526
2527 resets = <&ufs_mem_hc 0>;
2528 reset-names = "ufsphy";
2529
2530 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
2531
2532 #clock-cells = <1>;
2533 #phy-cells = <0>;
2534
2535 status = "disabled";
2536 };
2537
2538 ufs_mem_hc: ufs@1d84000 {
2539 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
2540 reg = <0 0x01d84000 0 0x3000>;
2541
2542 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2543
2544 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2545 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2546 <&gcc GCC_UFS_PHY_AHB_CLK>,
2547 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2548 <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
2549 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2550 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2551 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2552 clock-names = "core_clk",
2553 "bus_aggr_clk",
2554 "iface_clk",
2555 "core_clk_unipro",
2556 "ref_clk",
2557 "tx_lane0_sync_clk",
2558 "rx_lane0_sync_clk",
2559 "rx_lane1_sync_clk";
2560 freq-table-hz = <100000000 403000000>,
2561 <0 0>,
2562 <0 0>,
2563 <100000000 403000000>,
2564 <100000000 403000000>,
2565 <0 0>,
2566 <0 0>,
2567 <0 0>;
2568
2569 resets = <&gcc GCC_UFS_PHY_BCR>;
2570 reset-names = "rst";
2571
2572 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
2573 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
2574 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2575 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
2576 interconnect-names = "ufs-ddr",
2577 "cpu-ufs";
2578
2579 power-domains = <&gcc UFS_PHY_GDSC>;
2580 required-opps = <&rpmhpd_opp_nom>;
2581
2582 iommus = <&apps_smmu 0x60 0>;
2583
2584 lanes-per-direction = <2>;
2585 qcom,ice = <&ice>;
2586
2587 phys = <&ufs_mem_phy>;
2588 phy-names = "ufsphy";
2589
2590 #reset-cells = <1>;
2591
2592 status = "disabled";
2593 };
2594
2595 ice: crypto@1d88000 {
2596 compatible = "qcom,sm8650-inline-crypto-engine",
2597 "qcom,inline-crypto-engine";
2598 reg = <0 0x01d88000 0 0x8000>;
2599
2600 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2601 };
2602
2603 tcsr_mutex: hwlock@1f40000 {
2604 compatible = "qcom,tcsr-mutex";
2605 reg = <0 0x01f40000 0 0x20000>;
2606
2607 #hwlock-cells = <1>;
2608 };
2609
2610 tcsr: clock-controller@1fc0000 {
2611 compatible = "qcom,sm8650-tcsr", "syscon";
2612 reg = <0 0x01fc0000 0 0xa0000>;
2613
2614 clocks = <&rpmhcc RPMH_CXO_CLK>;
2615
2616 #clock-cells = <1>;
2617 #reset-cells = <1>;
2618 };
2619
2620 gpu: gpu@3d00000 {
2621 compatible = "qcom,adreno-43051401", "qcom,adreno";
2622 reg = <0x0 0x03d00000 0x0 0x40000>,
2623 <0x0 0x03d9e000 0x0 0x2000>,
2624 <0x0 0x03d61000 0x0 0x800>;
2625 reg-names = "kgsl_3d0_reg_memory",
2626 "cx_mem",
2627 "cx_dbgc";
2628
2629 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2630
2631 iommus = <&adreno_smmu 0 0x0>,
2632 <&adreno_smmu 1 0x0>;
2633
2634 operating-points-v2 = <&gpu_opp_table>;
2635
2636 qcom,gmu = <&gmu>;
2637 #cooling-cells = <2>;
2638
2639 status = "disabled";
2640
2641 zap-shader {
2642 memory-region = <&gpu_micro_code_mem>;
2643 };
2644
2645 /* Speedbin needs more work on A740+, keep only lower freqs */
2646 gpu_opp_table: opp-table {
2647 compatible = "operating-points-v2";
2648
2649 opp-231000000 {
2650 opp-hz = /bits/ 64 <231000000>;
2651 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2652 };
2653
2654 opp-310000000 {
2655 opp-hz = /bits/ 64 <310000000>;
2656 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2657 };
2658
2659 opp-366000000 {
2660 opp-hz = /bits/ 64 <366000000>;
2661 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2662 };
2663
2664 opp-422000000 {
2665 opp-hz = /bits/ 64 <422000000>;
2666 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2667 };
2668
2669 opp-500000000 {
2670 opp-hz = /bits/ 64 <500000000>;
2671 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2672 };
2673
2674 opp-578000000 {
2675 opp-hz = /bits/ 64 <578000000>;
2676 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2677 };
2678
2679 opp-629000000 {
2680 opp-hz = /bits/ 64 <629000000>;
2681 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2682 };
2683
2684 opp-680000000 {
2685 opp-hz = /bits/ 64 <680000000>;
2686 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2687 };
2688
2689 opp-720000000 {
2690 opp-hz = /bits/ 64 <720000000>;
2691 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2692 };
2693
2694 opp-770000000 {
2695 opp-hz = /bits/ 64 <770000000>;
2696 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2697 };
2698
2699 opp-834000000 {
2700 opp-hz = /bits/ 64 <834000000>;
2701 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2702 };
2703 };
2704 };
2705
2706 gmu: gmu@3d6a000 {
2707 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu";
2708 reg = <0x0 0x03d6a000 0x0 0x35000>,
2709 <0x0 0x03d50000 0x0 0x10000>,
2710 <0x0 0x0b280000 0x0 0x10000>;
2711 reg-names = "gmu", "rscc", "gmu_pdc";
2712
2713 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2714 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2715 interrupt-names = "hfi", "gmu";
2716
2717 clocks = <&gpucc GPU_CC_AHB_CLK>,
2718 <&gpucc GPU_CC_CX_GMU_CLK>,
2719 <&gpucc GPU_CC_CXO_CLK>,
2720 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2721 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2722 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2723 <&gpucc GPU_CC_DEMET_CLK>;
2724 clock-names = "ahb",
2725 "gmu",
2726 "cxo",
2727 "axi",
2728 "memnoc",
2729 "hub",
2730 "demet";
2731
2732 power-domains = <&gpucc GPU_CX_GDSC>,
2733 <&gpucc GPU_GX_GDSC>;
2734 power-domain-names = "cx",
2735 "gx";
2736
2737 iommus = <&adreno_smmu 5 0x0>;
2738
2739 qcom,qmp = <&aoss_qmp>;
2740
2741 operating-points-v2 = <&gmu_opp_table>;
2742
2743 gmu_opp_table: opp-table {
2744 compatible = "operating-points-v2";
2745
2746 opp-260000000 {
2747 opp-hz = /bits/ 64 <260000000>;
2748 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2749 };
2750
2751 opp-625000000 {
2752 opp-hz = /bits/ 64 <625000000>;
2753 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2754 };
2755 };
2756 };
2757
2758 gpucc: clock-controller@3d90000 {
2759 compatible = "qcom,sm8650-gpucc";
2760 reg = <0 0x03d90000 0 0xa000>;
2761
2762 clocks = <&bi_tcxo_div2>,
2763 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2764 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2765
2766 #clock-cells = <1>;
2767 #reset-cells = <1>;
2768 #power-domain-cells = <1>;
2769 };
2770
2771 adreno_smmu: iommu@3da0000 {
2772 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu",
2773 "qcom,smmu-500", "arm,mmu-500";
2774 reg = <0x0 0x03da0000 0x0 0x40000>;
2775 #iommu-cells = <2>;
2776 #global-interrupts = <1>;
2777 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2778 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>,
2779 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2780 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2781 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2782 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2783 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2784 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2785 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2786 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2787 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2788 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2789 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2790 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
2791 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
2792 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
2793 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2794 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
2795 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
2796 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
2797 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
2798 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
2799 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
2800 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
2801 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
2802 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
2803 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2804 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2805 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2806 <&gpucc GPU_CC_AHB_CLK>;
2807 clock-names = "hlos",
2808 "bus",
2809 "iface",
2810 "ahb";
2811 power-domains = <&gpucc GPU_CX_GDSC>;
2812 dma-coherent;
2813 };
2814
2815 ipa: ipa@3f40000 {
2816 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa";
2817
2818 iommus = <&apps_smmu 0x4a0 0x0>,
2819 <&apps_smmu 0x4a2 0x0>;
2820 reg = <0 0x3f40000 0 0x10000>,
2821 <0 0x3f50000 0 0x5000>,
2822 <0 0x3e04000 0 0xfc000>;
2823 reg-names = "ipa-reg",
2824 "ipa-shared",
2825 "gsi";
2826
2827 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2828 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2829 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2830 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2831 interrupt-names = "ipa",
2832 "gsi",
2833 "ipa-clock-query",
2834 "ipa-setup-ready";
2835
2836 clocks = <&rpmhcc RPMH_IPA_CLK>;
2837 clock-names = "core";
2838
2839 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2840 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2841 interconnect-names = "memory",
2842 "config";
2843
2844 qcom,qmp = <&aoss_qmp>;
2845
2846 qcom,smem-states = <&ipa_smp2p_out 0>,
2847 <&ipa_smp2p_out 1>;
2848 qcom,smem-state-names = "ipa-clock-enabled-valid",
2849 "ipa-clock-enabled";
2850
2851 status = "disabled";
2852 };
2853
2854 remoteproc_mpss: remoteproc@4080000 {
2855 compatible = "qcom,sm8650-mpss-pas";
2856 reg = <0 0x04080000 0 0x4040>;
2857
2858 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2859 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2860 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2861 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2862 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2863 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2864 interrupt-names = "wdog",
2865 "fatal",
2866 "ready",
2867 "handover",
2868 "stop-ack",
2869 "shutdown-ack";
2870
2871 clocks = <&rpmhcc RPMH_CXO_CLK>;
2872 clock-names = "xo";
2873
2874 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
2875 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2876
2877 power-domains = <&rpmhpd RPMHPD_CX>,
2878 <&rpmhpd RPMHPD_MSS>;
2879 power-domain-names = "cx",
2880 "mss";
2881
2882 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
2883 <&mpss_dsm_mem>, <&mpss_dsm_mem_2>,
2884 <&qlink_logging_mem>;
2885
2886 qcom,qmp = <&aoss_qmp>;
2887
2888 qcom,smem-states = <&smp2p_modem_out 0>;
2889 qcom,smem-state-names = "stop";
2890
2891 status = "disabled";
2892
2893 glink-edge {
2894 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2895 IPCC_MPROC_SIGNAL_GLINK_QMP
2896 IRQ_TYPE_EDGE_RISING>;
2897
2898 mboxes = <&ipcc IPCC_CLIENT_MPSS
2899 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2900
2901 qcom,remote-pid = <1>;
2902
2903 label = "mpss";
2904 };
2905 };
2906
2907 lpass_wsa2macro: codec@6aa0000 {
2908 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
2909 reg = <0 0x06aa0000 0 0x1000>;
2910 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2911 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2912 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2913 <&lpass_vamacro>;
2914 clock-names = "mclk",
2915 "macro",
2916 "dcodec",
2917 "fsgen";
2918
2919 #clock-cells = <0>;
2920 clock-output-names = "wsa2-mclk";
2921 #sound-dai-cells = <1>;
2922 };
2923
2924 swr3: soundwire@6ab0000 {
2925 compatible = "qcom,soundwire-v2.0.0";
2926 reg = <0 0x06ab0000 0 0x10000>;
2927 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2928 clocks = <&lpass_wsa2macro>;
2929 clock-names = "iface";
2930 label = "WSA2";
2931
2932 pinctrl-0 = <&wsa2_swr_active>;
2933 pinctrl-names = "default";
2934
2935 qcom,din-ports = <4>;
2936 qcom,dout-ports = <9>;
2937
2938 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2939 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2940 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2941 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2942 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2943 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2944 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2945 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2946 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2947
2948 #address-cells = <2>;
2949 #size-cells = <0>;
2950 #sound-dai-cells = <1>;
2951 status = "disabled";
2952 };
2953
2954 lpass_rxmacro: codec@6ac0000 {
2955 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
2956 reg = <0 0x06ac0000 0 0x1000>;
2957 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2958 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2959 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2960 <&lpass_vamacro>;
2961 clock-names = "mclk",
2962 "macro",
2963 "dcodec",
2964 "fsgen";
2965
2966 #clock-cells = <0>;
2967 clock-output-names = "mclk";
2968 #sound-dai-cells = <1>;
2969 };
2970
2971 swr1: soundwire@6ad0000 {
2972 compatible = "qcom,soundwire-v2.0.0";
2973 reg = <0 0x06ad0000 0 0x10000>;
2974 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2975 clocks = <&lpass_rxmacro>;
2976 clock-names = "iface";
2977 label = "RX";
2978
2979 pinctrl-0 = <&rx_swr_active>;
2980 pinctrl-names = "default";
2981
2982 qcom,din-ports = <0>;
2983 qcom,dout-ports = <11>;
2984
2985 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>;
2986 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>;
2987 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
2988 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>;
2989 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>;
2990 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>;
2991 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>;
2992 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>;
2993 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
2994
2995 #address-cells = <2>;
2996 #size-cells = <0>;
2997 #sound-dai-cells = <1>;
2998 status = "disabled";
2999 };
3000
3001 lpass_txmacro: codec@6ae0000 {
3002 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
3003 reg = <0 0x06ae0000 0 0x1000>;
3004 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3005 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3006 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3007 <&lpass_vamacro>;
3008 clock-names = "mclk",
3009 "macro",
3010 "dcodec",
3011 "fsgen";
3012
3013 #clock-cells = <0>;
3014 clock-output-names = "mclk";
3015 #sound-dai-cells = <1>;
3016 };
3017
3018 lpass_wsamacro: codec@6b00000 {
3019 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3020 reg = <0 0x06b00000 0 0x1000>;
3021 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3022 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3023 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3024 <&lpass_vamacro>;
3025 clock-names = "mclk",
3026 "macro",
3027 "dcodec",
3028 "fsgen";
3029
3030 #clock-cells = <0>;
3031 clock-output-names = "mclk";
3032 #sound-dai-cells = <1>;
3033 };
3034
3035 swr0: soundwire@6b10000 {
3036 compatible = "qcom,soundwire-v2.0.0";
3037 reg = <0 0x06b10000 0 0x10000>;
3038 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
3039 clocks = <&lpass_wsamacro>;
3040 clock-names = "iface";
3041 label = "WSA";
3042
3043 pinctrl-0 = <&wsa_swr_active>;
3044 pinctrl-names = "default";
3045
3046 qcom,din-ports = <4>;
3047 qcom,dout-ports = <9>;
3048
3049 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
3050 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3051 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3052 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3053 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3054 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
3055 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
3056 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3057 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3058
3059 #address-cells = <2>;
3060 #size-cells = <0>;
3061 #sound-dai-cells = <1>;
3062 status = "disabled";
3063 };
3064
3065 swr2: soundwire@6d30000 {
3066 compatible = "qcom,soundwire-v2.0.0";
3067 reg = <0 0x06d30000 0 0x10000>;
3068 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
3070 interrupt-names = "core", "wakeup";
3071 clocks = <&lpass_txmacro>;
3072 clock-names = "iface";
3073 label = "TX";
3074
3075 pinctrl-0 = <&tx_swr_active>;
3076 pinctrl-names = "default";
3077
3078 qcom,din-ports = <4>;
3079 qcom,dout-ports = <0>;
3080
3081 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
3082 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
3083 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
3084 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
3085 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
3086 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
3087 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
3088 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
3089 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
3090
3091 #address-cells = <2>;
3092 #size-cells = <0>;
3093 #sound-dai-cells = <1>;
3094 status = "disabled";
3095 };
3096
3097 lpass_vamacro: codec@6d44000 {
3098 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
3099 reg = <0 0x06d44000 0 0x1000>;
3100 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3101 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3102 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3103 clock-names = "mclk",
3104 "macro",
3105 "dcodec";
3106
3107 #clock-cells = <0>;
3108 clock-output-names = "fsgen";
3109 #sound-dai-cells = <1>;
3110 };
3111
3112 lpass_tlmm: pinctrl@6e80000 {
3113 compatible = "qcom,sm8650-lpass-lpi-pinctrl";
3114 reg = <0 0x06e80000 0 0x20000>;
3115
3116 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3117 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3118 clock-names = "core", "audio";
3119
3120 gpio-controller;
3121 #gpio-cells = <2>;
3122 gpio-ranges = <&lpass_tlmm 0 0 23>;
3123
3124 tx_swr_active: tx-swr-active-state {
3125 clk-pins {
3126 pins = "gpio0";
3127 function = "swr_tx_clk";
3128 drive-strength = <2>;
3129 slew-rate = <1>;
3130 bias-disable;
3131 };
3132
3133 data-pins {
3134 pins = "gpio1", "gpio2", "gpio14";
3135 function = "swr_tx_data";
3136 drive-strength = <2>;
3137 slew-rate = <1>;
3138 bias-bus-hold;
3139 };
3140 };
3141
3142 rx_swr_active: rx-swr-active-state {
3143 clk-pins {
3144 pins = "gpio3";
3145 function = "swr_rx_clk";
3146 drive-strength = <2>;
3147 slew-rate = <1>;
3148 bias-disable;
3149 };
3150
3151 data-pins {
3152 pins = "gpio4", "gpio5";
3153 function = "swr_rx_data";
3154 drive-strength = <2>;
3155 slew-rate = <1>;
3156 bias-bus-hold;
3157 };
3158 };
3159
3160 dmic01_default: dmic01-default-state {
3161 clk-pins {
3162 pins = "gpio6";
3163 function = "dmic1_clk";
3164 drive-strength = <8>;
3165 output-high;
3166 };
3167
3168 data-pins {
3169 pins = "gpio7";
3170 function = "dmic1_data";
3171 drive-strength = <8>;
3172 input-enable;
3173 };
3174 };
3175
3176 dmic23_default: dmic23-default-state {
3177 clk-pins {
3178 pins = "gpio8";
3179 function = "dmic2_clk";
3180 drive-strength = <8>;
3181 output-high;
3182 };
3183
3184 data-pins {
3185 pins = "gpio9";
3186 function = "dmic2_data";
3187 drive-strength = <8>;
3188 input-enable;
3189 };
3190 };
3191
3192 wsa_swr_active: wsa-swr-active-state {
3193 clk-pins {
3194 pins = "gpio10";
3195 function = "wsa_swr_clk";
3196 drive-strength = <2>;
3197 slew-rate = <1>;
3198 bias-disable;
3199 };
3200
3201 data-pins {
3202 pins = "gpio11";
3203 function = "wsa_swr_data";
3204 drive-strength = <2>;
3205 slew-rate = <1>;
3206 bias-bus-hold;
3207 };
3208 };
3209
3210 wsa2_swr_active: wsa2-swr-active-state {
3211 clk-pins {
3212 pins = "gpio15";
3213 function = "wsa2_swr_clk";
3214 drive-strength = <2>;
3215 slew-rate = <1>;
3216 bias-disable;
3217 };
3218
3219 data-pins {
3220 pins = "gpio16";
3221 function = "wsa2_swr_data";
3222 drive-strength = <2>;
3223 slew-rate = <1>;
3224 bias-bus-hold;
3225 };
3226 };
3227 };
3228
3229 lpass_lpiaon_noc: interconnect@7400000 {
3230 compatible = "qcom,sm8650-lpass-lpiaon-noc";
3231 reg = <0 0x07400000 0 0x19080>;
3232
3233 #interconnect-cells = <2>;
3234
3235 qcom,bcm-voters = <&apps_bcm_voter>;
3236 };
3237
3238 lpass_lpicx_noc: interconnect@7430000 {
3239 compatible = "qcom,sm8650-lpass-lpicx-noc";
3240 reg = <0 0x07430000 0 0x3a200>;
3241
3242 #interconnect-cells = <2>;
3243
3244 qcom,bcm-voters = <&apps_bcm_voter>;
3245 };
3246
3247 lpass_ag_noc: interconnect@7e40000 {
3248 compatible = "qcom,sm8650-lpass-ag-noc";
3249 reg = <0 0x07e40000 0 0xe080>;
3250
3251 #interconnect-cells = <2>;
3252
3253 qcom,bcm-voters = <&apps_bcm_voter>;
3254 };
3255
3256 sdhc_2: mmc@8804000 {
3257 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5";
3258 reg = <0 0x08804000 0 0x1000>;
3259
3260 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3261 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3262 interrupt-names = "hc_irq",
3263 "pwr_irq";
3264
3265 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3266 <&gcc GCC_SDCC2_APPS_CLK>,
3267 <&rpmhcc RPMH_CXO_CLK>;
3268 clock-names = "iface",
3269 "core",
3270 "xo";
3271
3272 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
3273 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3274 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
3275 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
3276 interconnect-names = "sdhc-ddr",
3277 "cpu-sdhc";
3278
3279 power-domains = <&rpmhpd RPMHPD_CX>;
3280 operating-points-v2 = <&sdhc2_opp_table>;
3281
3282 iommus = <&apps_smmu 0x540 0>;
3283
3284 bus-width = <4>;
3285
3286 /* Forbid SDR104/SDR50 - broken hw! */
3287 sdhci-caps-mask = <0x3 0>;
3288
3289 qcom,dll-config = <0x0007642c>;
3290 qcom,ddr-config = <0x80040868>;
3291
3292 dma-coherent;
3293
3294 status = "disabled";
3295
3296 sdhc2_opp_table: opp-table {
3297 compatible = "operating-points-v2";
3298
3299 opp-19200000 {
3300 opp-hz = /bits/ 64 <19200000>;
3301 required-opps = <&rpmhpd_opp_min_svs>;
3302 };
3303
3304 opp-50000000 {
3305 opp-hz = /bits/ 64 <50000000>;
3306 required-opps = <&rpmhpd_opp_low_svs>;
3307 };
3308
3309 opp-100000000 {
3310 opp-hz = /bits/ 64 <100000000>;
3311 required-opps = <&rpmhpd_opp_svs>;
3312 };
3313
3314 opp-202000000 {
3315 opp-hz = /bits/ 64 <202000000>;
3316 required-opps = <&rpmhpd_opp_svs_l1>;
3317 };
3318 };
3319 };
3320
3321 videocc: clock-controller@aaf0000 {
3322 compatible = "qcom,sm8650-videocc";
3323 reg = <0 0x0aaf0000 0 0x10000>;
3324 clocks = <&bi_tcxo_div2>,
3325 <&gcc GCC_VIDEO_AHB_CLK>;
3326 power-domains = <&rpmhpd RPMHPD_MMCX>;
3327 #clock-cells = <1>;
3328 #reset-cells = <1>;
3329 #power-domain-cells = <1>;
3330 };
3331
3332 camcc: clock-controller@ade0000 {
3333 compatible = "qcom,sm8650-camcc";
3334 reg = <0 0x0ade0000 0 0x20000>;
3335 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3336 <&bi_tcxo_div2>,
3337 <&bi_tcxo_ao_div2>,
3338 <&sleep_clk>;
3339 power-domains = <&rpmhpd RPMHPD_MMCX>;
3340 #clock-cells = <1>;
3341 #reset-cells = <1>;
3342 #power-domain-cells = <1>;
3343 };
3344
3345 mdss: display-subsystem@ae00000 {
3346 compatible = "qcom,sm8650-mdss";
3347 reg = <0 0x0ae00000 0 0x1000>;
3348 reg-names = "mdss";
3349
3350 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3351
3352 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3353 <&gcc GCC_DISP_HF_AXI_CLK>,
3354 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3355
3356 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
3357
3358 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
3359 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
3360 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
3361 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
3362 interconnect-names = "mdp0-mem",
3363 "mdp1-mem";
3364
3365 power-domains = <&dispcc MDSS_GDSC>;
3366
3367 iommus = <&apps_smmu 0x1c00 0x2>;
3368
3369 interrupt-controller;
3370 #interrupt-cells = <1>;
3371
3372 #address-cells = <2>;
3373 #size-cells = <2>;
3374 ranges;
3375
3376 status = "disabled";
3377
3378 mdss_mdp: display-controller@ae01000 {
3379 compatible = "qcom,sm8650-dpu";
3380 reg = <0 0x0ae01000 0 0x8f000>,
3381 <0 0x0aeb0000 0 0x2008>;
3382 reg-names = "mdp",
3383 "vbif";
3384
3385 interrupts-extended = <&mdss 0>;
3386
3387 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3388 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3389 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3390 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3391 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3392 clock-names = "nrt_bus",
3393 "iface",
3394 "lut",
3395 "core",
3396 "vsync";
3397
3398 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3399 assigned-clock-rates = <19200000>;
3400
3401 operating-points-v2 = <&mdp_opp_table>;
3402
3403 power-domains = <&rpmhpd RPMHPD_MMCX>;
3404
3405 ports {
3406 #address-cells = <1>;
3407 #size-cells = <0>;
3408
3409 port@0 {
3410 reg = <0>;
3411
3412 dpu_intf1_out: endpoint {
3413 remote-endpoint = <&mdss_dsi0_in>;
3414 };
3415 };
3416
3417 port@1 {
3418 reg = <1>;
3419
3420 dpu_intf2_out: endpoint {
3421 remote-endpoint = <&mdss_dsi1_in>;
3422 };
3423 };
3424
3425 port@2 {
3426 reg = <2>;
3427
3428 dpu_intf0_out: endpoint {
3429 remote-endpoint = <&mdss_dp0_in>;
3430 };
3431 };
3432 };
3433
3434 mdp_opp_table: opp-table {
3435 compatible = "operating-points-v2";
3436
3437 opp-200000000 {
3438 opp-hz = /bits/ 64 <200000000>;
3439 required-opps = <&rpmhpd_opp_low_svs>;
3440 };
3441
3442 opp-325000000 {
3443 opp-hz = /bits/ 64 <325000000>;
3444 required-opps = <&rpmhpd_opp_svs>;
3445 };
3446
3447 opp-375000000 {
3448 opp-hz = /bits/ 64 <375000000>;
3449 required-opps = <&rpmhpd_opp_svs_l1>;
3450 };
3451
3452 opp-514000000 {
3453 opp-hz = /bits/ 64 <514000000>;
3454 required-opps = <&rpmhpd_opp_nom>;
3455 };
3456 };
3457 };
3458
3459 mdss_dsi0: dsi@ae94000 {
3460 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3461 reg = <0 0x0ae94000 0 0x400>;
3462 reg-names = "dsi_ctrl";
3463
3464 interrupts-extended = <&mdss 4>;
3465
3466 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3467 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3468 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3469 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3470 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3471 <&gcc GCC_DISP_HF_AXI_CLK>;
3472 clock-names = "byte",
3473 "byte_intf",
3474 "pixel",
3475 "core",
3476 "iface",
3477 "bus";
3478
3479 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3480 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3481 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3482 <&mdss_dsi0_phy 1>;
3483
3484 operating-points-v2 = <&mdss_dsi_opp_table>;
3485
3486 power-domains = <&rpmhpd RPMHPD_MMCX>;
3487
3488 phys = <&mdss_dsi0_phy>;
3489 phy-names = "dsi";
3490
3491 #address-cells = <1>;
3492 #size-cells = <0>;
3493
3494 status = "disabled";
3495
3496 ports {
3497 #address-cells = <1>;
3498 #size-cells = <0>;
3499
3500 port@0 {
3501 reg = <0>;
3502
3503 mdss_dsi0_in: endpoint {
3504 remote-endpoint = <&dpu_intf1_out>;
3505 };
3506 };
3507
3508 port@1 {
3509 reg = <1>;
3510
3511 mdss_dsi0_out: endpoint {
3512 };
3513 };
3514 };
3515
3516 mdss_dsi_opp_table: opp-table {
3517 compatible = "operating-points-v2";
3518
3519 opp-187500000 {
3520 opp-hz = /bits/ 64 <187500000>;
3521 required-opps = <&rpmhpd_opp_low_svs>;
3522 };
3523
3524 opp-300000000 {
3525 opp-hz = /bits/ 64 <300000000>;
3526 required-opps = <&rpmhpd_opp_svs>;
3527 };
3528
3529 opp-358000000 {
3530 opp-hz = /bits/ 64 <358000000>;
3531 required-opps = <&rpmhpd_opp_svs_l1>;
3532 };
3533 };
3534 };
3535
3536 mdss_dsi0_phy: phy@ae95000 {
3537 compatible = "qcom,sm8650-dsi-phy-4nm";
3538 reg = <0 0x0ae95000 0 0x200>,
3539 <0 0x0ae95200 0 0x280>,
3540 <0 0x0ae95500 0 0x400>;
3541 reg-names = "dsi_phy",
3542 "dsi_phy_lane",
3543 "dsi_pll";
3544
3545 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3546 <&rpmhcc RPMH_CXO_CLK>;
3547 clock-names = "iface",
3548 "ref";
3549
3550 #clock-cells = <1>;
3551 #phy-cells = <0>;
3552
3553 status = "disabled";
3554 };
3555
3556 mdss_dsi1: dsi@ae96000 {
3557 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3558 reg = <0 0x0ae96000 0 0x400>;
3559 reg-names = "dsi_ctrl";
3560
3561 interrupts-extended = <&mdss 5>;
3562
3563 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3564 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3565 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3566 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3567 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3568 <&gcc GCC_DISP_HF_AXI_CLK>;
3569 clock-names = "byte",
3570 "byte_intf",
3571 "pixel",
3572 "core",
3573 "iface",
3574 "bus";
3575
3576 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3577 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3578 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3579 <&mdss_dsi1_phy 1>;
3580
3581 operating-points-v2 = <&mdss_dsi_opp_table>;
3582
3583 power-domains = <&rpmhpd RPMHPD_MMCX>;
3584
3585 phys = <&mdss_dsi1_phy>;
3586 phy-names = "dsi";
3587
3588 #address-cells = <1>;
3589 #size-cells = <0>;
3590
3591 status = "disabled";
3592
3593 ports {
3594 #address-cells = <1>;
3595 #size-cells = <0>;
3596
3597 port@0 {
3598 reg = <0>;
3599
3600 mdss_dsi1_in: endpoint {
3601 remote-endpoint = <&dpu_intf2_out>;
3602 };
3603 };
3604
3605 port@1 {
3606 reg = <1>;
3607
3608 mdss_dsi1_out: endpoint {
3609 };
3610 };
3611 };
3612 };
3613
3614 mdss_dsi1_phy: phy@ae97000 {
3615 compatible = "qcom,sm8650-dsi-phy-4nm";
3616 reg = <0 0x0ae97000 0 0x200>,
3617 <0 0x0ae97200 0 0x280>,
3618 <0 0x0ae97500 0 0x400>;
3619 reg-names = "dsi_phy",
3620 "dsi_phy_lane",
3621 "dsi_pll";
3622
3623 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3624 <&rpmhcc RPMH_CXO_CLK>;
3625 clock-names = "iface",
3626 "ref";
3627
3628 #clock-cells = <1>;
3629 #phy-cells = <0>;
3630
3631 status = "disabled";
3632 };
3633
3634 mdss_dp0: displayport-controller@af54000 {
3635 compatible = "qcom,sm8650-dp";
3636 reg = <0 0xaf54000 0 0x104>,
3637 <0 0xaf54200 0 0xc0>,
3638 <0 0xaf55000 0 0x770>,
3639 <0 0xaf56000 0 0x9c>,
3640 <0 0xaf57000 0 0x9c>;
3641
3642 interrupts-extended = <&mdss 12>;
3643
3644 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3645 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
3646 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
3647 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3648 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3649 clock-names = "core_iface",
3650 "core_aux",
3651 "ctrl_link",
3652 "ctrl_link_iface",
3653 "stream_pixel";
3654
3655 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3656 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3657 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3658 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3659
3660 operating-points-v2 = <&dp_opp_table>;
3661
3662 power-domains = <&rpmhpd RPMHPD_MMCX>;
3663
3664 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
3665 phy-names = "dp";
3666
3667 #sound-dai-cells = <0>;
3668
3669 status = "disabled";
3670
3671 dp_opp_table: opp-table {
3672 compatible = "operating-points-v2";
3673
3674 opp-162000000 {
3675 opp-hz = /bits/ 64 <162000000>;
3676 required-opps = <&rpmhpd_opp_low_svs_d1>;
3677 };
3678
3679 opp-270000000 {
3680 opp-hz = /bits/ 64 <270000000>;
3681 required-opps = <&rpmhpd_opp_low_svs>;
3682 };
3683
3684 opp-540000000 {
3685 opp-hz = /bits/ 64 <540000000>;
3686 required-opps = <&rpmhpd_opp_svs_l1>;
3687 };
3688
3689 opp-810000000 {
3690 opp-hz = /bits/ 64 <810000000>;
3691 required-opps = <&rpmhpd_opp_nom>;
3692 };
3693 };
3694
3695 ports {
3696 #address-cells = <1>;
3697 #size-cells = <0>;
3698
3699 port@0 {
3700 reg = <0>;
3701
3702 mdss_dp0_in: endpoint {
3703 remote-endpoint = <&dpu_intf0_out>;
3704 };
3705 };
3706
3707 port@1 {
3708 reg = <1>;
3709
3710 mdss_dp0_out: endpoint {
3711 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
3712 };
3713 };
3714 };
3715 };
3716 };
3717
3718 dispcc: clock-controller@af00000 {
3719 compatible = "qcom,sm8650-dispcc";
3720 reg = <0 0x0af00000 0 0x20000>;
3721
3722 clocks = <&bi_tcxo_div2>,
3723 <&bi_tcxo_ao_div2>,
3724 <&gcc GCC_DISP_AHB_CLK>,
3725 <&sleep_clk>,
3726 <&mdss_dsi0_phy 0>,
3727 <&mdss_dsi0_phy 1>,
3728 <&mdss_dsi1_phy 0>,
3729 <&mdss_dsi1_phy 1>,
3730 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3731 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3732 <0>, /* dp1 */
3733 <0>,
3734 <0>, /* dp2 */
3735 <0>,
3736 <0>, /* dp3 */
3737 <0>;
3738
3739 power-domains = <&rpmhpd RPMHPD_MMCX>;
3740 required-opps = <&rpmhpd_opp_low_svs>;
3741
3742 #clock-cells = <1>;
3743 #reset-cells = <1>;
3744 #power-domain-cells = <1>;
3745
3746 status = "disabled";
3747 };
3748
3749 usb_1_hsphy: phy@88e3000 {
3750 compatible = "qcom,sm8650-snps-eusb2-phy",
3751 "qcom,sm8550-snps-eusb2-phy";
3752 reg = <0 0x088e3000 0 0x154>;
3753
3754 clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
3755 clock-names = "ref";
3756
3757 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3758
3759 #phy-cells = <0>;
3760
3761 status = "disabled";
3762 };
3763
3764 usb_dp_qmpphy: phy@88e8000 {
3765 compatible = "qcom,sm8650-qmp-usb3-dp-phy";
3766 reg = <0 0x088e8000 0 0x3000>;
3767
3768 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3769 <&rpmhcc RPMH_CXO_CLK>,
3770 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3771 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3772 clock-names = "aux",
3773 "ref",
3774 "com_aux",
3775 "usb3_pipe";
3776
3777 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3778 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
3779 reset-names = "phy",
3780 "common";
3781
3782 power-domains = <&gcc USB3_PHY_GDSC>;
3783
3784 #clock-cells = <1>;
3785 #phy-cells = <1>;
3786
3787 orientation-switch;
3788
3789 status = "disabled";
3790
3791 ports {
3792 #address-cells = <1>;
3793 #size-cells = <0>;
3794
3795 port@0 {
3796 reg = <0>;
3797
3798 usb_dp_qmpphy_out: endpoint {
3799 };
3800 };
3801
3802 port@1 {
3803 reg = <1>;
3804
3805 usb_dp_qmpphy_usb_ss_in: endpoint {
3806 remote-endpoint = <&usb_1_dwc3_ss>;
3807 };
3808 };
3809
3810 port@2 {
3811 reg = <2>;
3812
3813 usb_dp_qmpphy_dp_in: endpoint {
3814 remote-endpoint = <&mdss_dp0_out>;
3815 };
3816 };
3817 };
3818 };
3819
3820 usb_1: usb@a6f8800 {
3821 compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
3822 reg = <0 0x0a6f8800 0 0x400>;
3823
3824 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3825 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3826 <&pdc 14 IRQ_TYPE_EDGE_RISING>,
3827 <&pdc 15 IRQ_TYPE_EDGE_RISING>,
3828 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
3829 interrupt-names = "pwr_event",
3830 "hs_phy_irq",
3831 "dp_hs_phy_irq",
3832 "dm_hs_phy_irq",
3833 "ss_phy_irq";
3834
3835 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3836 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3837 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3838 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3839 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3840 <&tcsr TCSR_USB3_CLKREF_EN>;
3841 clock-names = "cfg_noc",
3842 "core",
3843 "iface",
3844 "sleep",
3845 "mock_utmi",
3846 "xo";
3847
3848 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3849 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3850 assigned-clock-rates = <19200000>, <200000000>;
3851
3852 resets = <&gcc GCC_USB30_PRIM_BCR>;
3853
3854 power-domains = <&gcc USB30_PRIM_GDSC>;
3855 required-opps = <&rpmhpd_opp_nom>;
3856
3857 #address-cells = <2>;
3858 #size-cells = <2>;
3859 ranges;
3860
3861 status = "disabled";
3862
3863 usb_1_dwc3: usb@a600000 {
3864 compatible = "snps,dwc3";
3865 reg = <0 0x0a600000 0 0xcd00>;
3866
3867 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3868
3869 iommus = <&apps_smmu 0x40 0>;
3870
3871 phys = <&usb_1_hsphy>,
3872 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
3873 phy-names = "usb2-phy",
3874 "usb3-phy";
3875
3876 snps,hird-threshold = /bits/ 8 <0x0>;
3877 snps,usb2-gadget-lpm-disable;
3878 snps,dis_u2_susphy_quirk;
3879 snps,dis_enblslpm_quirk;
3880 snps,dis-u1-entry-quirk;
3881 snps,dis-u2-entry-quirk;
3882 snps,is-utmi-l1-suspend;
3883 snps,usb3_lpm_capable;
3884 snps,usb2-lpm-disable;
3885 snps,has-lpm-erratum;
3886 tx-fifo-resize;
3887
3888 dma-coherent;
3889
3890 ports {
3891 #address-cells = <1>;
3892 #size-cells = <0>;
3893
3894 port@0 {
3895 reg = <0>;
3896
3897 usb_1_dwc3_hs: endpoint {
3898 };
3899 };
3900
3901 port@1 {
3902 reg = <1>;
3903
3904 usb_1_dwc3_ss: endpoint {
3905 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
3906 };
3907 };
3908 };
3909 };
3910 };
3911
3912 pdc: interrupt-controller@b220000 {
3913 compatible = "qcom,sm8650-pdc", "qcom,pdc";
3914 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3915
3916 interrupt-parent = <&intc>;
3917
3918 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3919 <125 63 1>, <126 716 12>,
3920 <138 251 5>, <143 244 4>;
3921
3922 #interrupt-cells = <2>;
3923 interrupt-controller;
3924 };
3925
3926 tsens0: thermal-sensor@c228000 {
3927 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
3928 reg = <0 0x0c228000 0 0x1000>, /* TM */
3929 <0 0x0c222000 0 0x1000>; /* SROT */
3930
3931 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3932 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
3933 interrupt-names = "uplow",
3934 "critical";
3935
3936 #qcom,sensors = <15>;
3937
3938 #thermal-sensor-cells = <1>;
3939 };
3940
3941 tsens1: thermal-sensor@c229000 {
3942 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
3943 reg = <0 0x0c229000 0 0x1000>, /* TM */
3944 <0 0x0c223000 0 0x1000>; /* SROT */
3945
3946 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3947 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
3948 interrupt-names = "uplow",
3949 "critical";
3950
3951 #qcom,sensors = <16>;
3952
3953 #thermal-sensor-cells = <1>;
3954 };
3955
3956 tsens2: thermal-sensor@c22a000 {
3957 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
3958 reg = <0 0x0c22a000 0 0x1000>, /* TM */
3959 <0 0x0c224000 0 0x1000>; /* SROT */
3960
3961 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
3962 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
3963 interrupt-names = "uplow",
3964 "critical";
3965
3966 #qcom,sensors = <13>;
3967
3968 #thermal-sensor-cells = <1>;
3969 };
3970
3971 aoss_qmp: power-management@c300000 {
3972 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp";
3973 reg = <0 0x0c300000 0 0x400>;
3974
3975 interrupt-parent = <&ipcc>;
3976 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3977 IRQ_TYPE_EDGE_RISING>;
3978
3979 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3980
3981 #clock-cells = <0>;
3982 };
3983
3984 sram@c3f0000 {
3985 compatible = "qcom,rpmh-stats";
3986 reg = <0 0x0c3f0000 0 0x400>;
3987 };
3988
3989 spmi_bus: spmi@c400000 {
3990 compatible = "qcom,spmi-pmic-arb";
3991 reg = <0 0x0c400000 0 0x3000>,
3992 <0 0x0c500000 0 0x400000>,
3993 <0 0x0c440000 0 0x80000>,
3994 <0 0x0c4c0000 0 0x20000>,
3995 <0 0x0c42d000 0 0x4000>;
3996 reg-names = "core",
3997 "chnls",
3998 "obsrvr",
3999 "intr",
4000 "cnfg";
4001
4002 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4003 interrupt-names = "periph_irq";
4004
4005 qcom,ee = <0>;
4006 qcom,channel = <0>;
4007 qcom,bus-id = <0>;
4008
4009 interrupt-controller;
4010 #interrupt-cells = <4>;
4011
4012 #address-cells = <2>;
4013 #size-cells = <0>;
4014 };
4015
4016 tlmm: pinctrl@f100000 {
4017 compatible = "qcom,sm8650-tlmm";
4018 reg = <0 0x0f100000 0 0x300000>;
4019
4020 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4021
4022 gpio-controller;
4023 #gpio-cells = <2>;
4024
4025 interrupt-controller;
4026 #interrupt-cells = <2>;
4027
4028 gpio-ranges = <&tlmm 0 0 211>;
4029
4030 wakeup-parent = <&pdc>;
4031
4032 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
4033 /* SDA, SCL */
4034 pins = "gpio64", "gpio65";
4035 function = "i2chub0_se0";
4036 drive-strength = <2>;
4037 bias-pull-up;
4038 };
4039
4040 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
4041 /* SDA, SCL */
4042 pins = "gpio66", "gpio67";
4043 function = "i2chub0_se1";
4044 drive-strength = <2>;
4045 bias-pull-up;
4046 };
4047
4048 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
4049 /* SDA, SCL */
4050 pins = "gpio68", "gpio69";
4051 function = "i2chub0_se2";
4052 drive-strength = <2>;
4053 bias-pull-up;
4054 };
4055
4056 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
4057 /* SDA, SCL */
4058 pins = "gpio70", "gpio71";
4059 function = "i2chub0_se3";
4060 drive-strength = <2>;
4061 bias-pull-up;
4062 };
4063
4064 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
4065 /* SDA, SCL */
4066 pins = "gpio72", "gpio73";
4067 function = "i2chub0_se4";
4068 drive-strength = <2>;
4069 bias-pull-up;
4070 };
4071
4072 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
4073 /* SDA, SCL */
4074 pins = "gpio74", "gpio75";
4075 function = "i2chub0_se5";
4076 drive-strength = <2>;
4077 bias-pull-up;
4078 };
4079
4080 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
4081 /* SDA, SCL */
4082 pins = "gpio76", "gpio77";
4083 function = "i2chub0_se6";
4084 drive-strength = <2>;
4085 bias-pull-up;
4086 };
4087
4088 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
4089 /* SDA, SCL */
4090 pins = "gpio78", "gpio79";
4091 function = "i2chub0_se7";
4092 drive-strength = <2>;
4093 bias-pull-up;
4094 };
4095
4096 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
4097 /* SDA, SCL */
4098 pins = "gpio206", "gpio207";
4099 function = "i2chub0_se8";
4100 drive-strength = <2>;
4101 bias-pull-up;
4102 };
4103
4104 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
4105 /* SDA, SCL */
4106 pins = "gpio80", "gpio81";
4107 function = "i2chub0_se9";
4108 drive-strength = <2>;
4109 bias-pull-up;
4110 };
4111
4112 pcie0_default_state: pcie0-default-state {
4113 perst-pins {
4114 pins = "gpio94";
4115 function = "gpio";
4116 drive-strength = <2>;
4117 bias-pull-down;
4118 };
4119
4120 clkreq-pins {
4121 pins = "gpio95";
4122 function = "pcie0_clk_req_n";
4123 drive-strength = <2>;
4124 bias-pull-up;
4125 };
4126
4127 wake-pins {
4128 pins = "gpio96";
4129 function = "gpio";
4130 drive-strength = <2>;
4131 bias-pull-up;
4132 };
4133 };
4134
4135 pcie1_default_state: pcie1-default-state {
4136 perst-pins {
4137 pins = "gpio97";
4138 function = "gpio";
4139 drive-strength = <2>;
4140 bias-pull-down;
4141 };
4142
4143 clkreq-pins {
4144 pins = "gpio98";
4145 function = "pcie1_clk_req_n";
4146 drive-strength = <2>;
4147 bias-pull-up;
4148 };
4149
4150 wake-pins {
4151 pins = "gpio99";
4152 function = "gpio";
4153 drive-strength = <2>;
4154 bias-pull-up;
4155 };
4156 };
4157
4158 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4159 /* SDA, SCL */
4160 pins = "gpio32", "gpio33";
4161 function = "qup1_se0";
4162 drive-strength = <2>;
4163 bias-pull-up;
4164 };
4165
4166 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4167 /* SDA, SCL */
4168 pins = "gpio36", "gpio37";
4169 function = "qup1_se1";
4170 drive-strength = <2>;
4171 bias-pull-up;
4172 };
4173
4174 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4175 /* SDA, SCL */
4176 pins = "gpio40", "gpio41";
4177 function = "qup1_se2";
4178 drive-strength = <2>;
4179 bias-pull-up;
4180 };
4181
4182 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4183 /* SDA, SCL */
4184 pins = "gpio44", "gpio45";
4185 function = "qup1_se3";
4186 drive-strength = <2>;
4187 bias-pull-up;
4188 };
4189
4190 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4191 /* SDA, SCL */
4192 pins = "gpio48", "gpio49";
4193 function = "qup1_se4";
4194 drive-strength = <2>;
4195 bias-pull-up;
4196 };
4197
4198 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4199 /* SDA, SCL */
4200 pins = "gpio52", "gpio53";
4201 function = "qup1_se5";
4202 drive-strength = <2>;
4203 bias-pull-up;
4204 };
4205
4206 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4207 /* SDA, SCL */
4208 pins = "gpio56", "gpio57";
4209 function = "qup1_se6";
4210 drive-strength = <2>;
4211 bias-pull-up;
4212 };
4213
4214 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
4215 /* SDA, SCL */
4216 pins = "gpio60", "gpio61";
4217 function = "qup1_se7";
4218 drive-strength = <2>;
4219 bias-pull-up;
4220 };
4221
4222 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4223 /* SDA, SCL */
4224 pins = "gpio0", "gpio1";
4225 function = "qup2_se0";
4226 drive-strength = <2>;
4227 bias-pull-up;
4228 };
4229
4230 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4231 /* SDA, SCL */
4232 pins = "gpio4", "gpio5";
4233 function = "qup2_se1";
4234 drive-strength = <2>;
4235 bias-pull-up;
4236 };
4237
4238 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4239 /* SDA, SCL */
4240 pins = "gpio8", "gpio9";
4241 function = "qup2_se2";
4242 drive-strength = <2>;
4243 bias-pull-up;
4244 };
4245
4246 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4247 /* SDA, SCL */
4248 pins = "gpio12", "gpio13";
4249 function = "qup2_se3";
4250 drive-strength = <2>;
4251 bias-pull-up;
4252 };
4253
4254 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4255 /* SDA, SCL */
4256 pins = "gpio16", "gpio17";
4257 function = "qup2_se4";
4258 drive-strength = <2>;
4259 bias-pull-up;
4260 };
4261
4262 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4263 /* SDA, SCL */
4264 pins = "gpio20", "gpio21";
4265 function = "qup2_se5";
4266 drive-strength = <2>;
4267 bias-pull-up;
4268 };
4269
4270 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
4271 /* SDA, SCL */
4272 pins = "gpio24", "gpio25";
4273 function = "qup2_se6";
4274 drive-strength = <2>;
4275 bias-pull-up;
4276 };
4277
4278 qup_spi0_cs: qup-spi0-cs-state {
4279 pins = "gpio35";
4280 function = "qup1_se0";
4281 drive-strength = <6>;
4282 bias-disable;
4283 };
4284
4285 qup_spi0_data_clk: qup-spi0-data-clk-state {
4286 /* MISO, MOSI, CLK */
4287 pins = "gpio32", "gpio33", "gpio34";
4288 function = "qup1_se0";
4289 drive-strength = <6>;
4290 bias-disable;
4291 };
4292
4293 qup_spi1_cs: qup-spi1-cs-state {
4294 pins = "gpio39";
4295 function = "qup1_se1";
4296 drive-strength = <6>;
4297 bias-disable;
4298 };
4299
4300 qup_spi1_data_clk: qup-spi1-data-clk-state {
4301 /* MISO, MOSI, CLK */
4302 pins = "gpio36", "gpio37", "gpio38";
4303 function = "qup1_se1";
4304 drive-strength = <6>;
4305 bias-disable;
4306 };
4307
4308 qup_spi2_cs: qup-spi2-cs-state {
4309 pins = "gpio43";
4310 function = "qup1_se2";
4311 drive-strength = <6>;
4312 bias-disable;
4313 };
4314
4315 qup_spi2_data_clk: qup-spi2-data-clk-state {
4316 /* MISO, MOSI, CLK */
4317 pins = "gpio40", "gpio41", "gpio42";
4318 function = "qup1_se2";
4319 drive-strength = <6>;
4320 bias-disable;
4321 };
4322
4323 qup_spi3_cs: qup-spi3-cs-state {
4324 pins = "gpio47";
4325 function = "qup1_se3";
4326 drive-strength = <6>;
4327 bias-disable;
4328 };
4329
4330 qup_spi3_data_clk: qup-spi3-data-clk-state {
4331 /* MISO, MOSI, CLK */
4332 pins = "gpio44", "gpio45", "gpio46";
4333 function = "qup1_se3";
4334 drive-strength = <6>;
4335 bias-disable;
4336 };
4337
4338 qup_spi4_cs: qup-spi4-cs-state {
4339 pins = "gpio51";
4340 function = "qup1_se4";
4341 drive-strength = <6>;
4342 bias-disable;
4343 };
4344
4345 qup_spi4_data_clk: qup-spi4-data-clk-state {
4346 /* MISO, MOSI, CLK */
4347 pins = "gpio48", "gpio49", "gpio50";
4348 function = "qup1_se4";
4349 drive-strength = <6>;
4350 bias-disable;
4351 };
4352
4353 qup_spi5_cs: qup-spi5-cs-state {
4354 pins = "gpio55";
4355 function = "qup1_se5";
4356 drive-strength = <6>;
4357 bias-disable;
4358 };
4359
4360 qup_spi5_data_clk: qup-spi5-data-clk-state {
4361 /* MISO, MOSI, CLK */
4362 pins = "gpio52", "gpio53", "gpio54";
4363 function = "qup1_se5";
4364 drive-strength = <6>;
4365 bias-disable;
4366 };
4367
4368 qup_spi6_cs: qup-spi6-cs-state {
4369 pins = "gpio59";
4370 function = "qup1_se6";
4371 drive-strength = <6>;
4372 bias-disable;
4373 };
4374
4375 qup_spi6_data_clk: qup-spi6-data-clk-state {
4376 /* MISO, MOSI, CLK */
4377 pins = "gpio56", "gpio57", "gpio58";
4378 function = "qup1_se6";
4379 drive-strength = <6>;
4380 bias-disable;
4381 };
4382
4383 qup_spi7_cs: qup-spi7-cs-state {
4384 pins = "gpio63";
4385 function = "qup1_se7";
4386 drive-strength = <6>;
4387 bias-disable;
4388 };
4389
4390 qup_spi7_data_clk: qup-spi7-data-clk-state {
4391 /* MISO, MOSI, CLK */
4392 pins = "gpio60", "gpio61", "gpio62";
4393 function = "qup1_se7";
4394 drive-strength = <6>;
4395 bias-disable;
4396 };
4397
4398 qup_spi8_cs: qup-spi8-cs-state {
4399 pins = "gpio3";
4400 function = "qup2_se0";
4401 drive-strength = <6>;
4402 bias-disable;
4403 };
4404
4405 qup_spi8_data_clk: qup-spi8-data-clk-state {
4406 /* MISO, MOSI, CLK */
4407 pins = "gpio0", "gpio1", "gpio2";
4408 function = "qup2_se0";
4409 drive-strength = <6>;
4410 bias-disable;
4411 };
4412
4413 qup_spi9_cs: qup-spi9-cs-state {
4414 pins = "gpio7";
4415 function = "qup2_se1";
4416 drive-strength = <6>;
4417 bias-disable;
4418 };
4419
4420 qup_spi9_data_clk: qup-spi9-data-clk-state {
4421 /* MISO, MOSI, CLK */
4422 pins = "gpio4", "gpio5", "gpio6";
4423 function = "qup2_se1";
4424 drive-strength = <6>;
4425 bias-disable;
4426 };
4427
4428 qup_spi10_cs: qup-spi10-cs-state {
4429 pins = "gpio11";
4430 function = "qup2_se2";
4431 drive-strength = <6>;
4432 bias-disable;
4433 };
4434
4435 qup_spi10_data_clk: qup-spi10-data-clk-state {
4436 /* MISO, MOSI, CLK */
4437 pins = "gpio8", "gpio9", "gpio10";
4438 function = "qup2_se2";
4439 drive-strength = <6>;
4440 bias-disable;
4441 };
4442
4443 qup_spi11_cs: qup-spi11-cs-state {
4444 pins = "gpio15";
4445 function = "qup2_se3";
4446 drive-strength = <6>;
4447 bias-disable;
4448 };
4449
4450 qup_spi11_data_clk: qup-spi11-data-clk-state {
4451 /* MISO, MOSI, CLK */
4452 pins = "gpio12", "gpio13", "gpio14";
4453 function = "qup2_se3";
4454 drive-strength = <6>;
4455 bias-disable;
4456 };
4457
4458 qup_spi12_cs: qup-spi12-cs-state {
4459 pins = "gpio19";
4460 function = "qup2_se4";
4461 drive-strength = <6>;
4462 bias-disable;
4463 };
4464
4465 qup_spi12_data_clk: qup-spi12-data-clk-state {
4466 /* MISO, MOSI, CLK */
4467 pins = "gpio16", "gpio17", "gpio18";
4468 function = "qup2_se4";
4469 drive-strength = <6>;
4470 bias-disable;
4471 };
4472
4473 qup_spi13_cs: qup-spi13-cs-state {
4474 pins = "gpio23";
4475 function = "qup2_se5";
4476 drive-strength = <6>;
4477 bias-disable;
4478 };
4479
4480 qup_spi13_data_clk: qup-spi13-data-clk-state {
4481 /* MISO, MOSI, CLK */
4482 pins = "gpio20", "gpio21", "gpio22";
4483 function = "qup2_se5";
4484 drive-strength = <6>;
4485 bias-disable;
4486 };
4487
4488 qup_spi14_cs: qup-spi14-cs-state {
4489 pins = "gpio27";
4490 function = "qup2_se6";
4491 drive-strength = <6>;
4492 bias-disable;
4493 };
4494
4495 qup_spi14_data_clk: qup-spi14-data-clk-state {
4496 /* MISO, MOSI, CLK */
4497 pins = "gpio24", "gpio25", "gpio26";
4498 function = "qup2_se6";
4499 drive-strength = <6>;
4500 bias-disable;
4501 };
4502
4503 qup_uart14_default: qup-uart14-default-state {
4504 /* TX, RX */
4505 pins = "gpio26", "gpio27";
4506 function = "qup2_se6";
4507 drive-strength = <2>;
4508 bias-pull-up;
4509 };
4510
4511 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
4512 /* CTS, RTS */
4513 pins = "gpio24", "gpio25";
4514 function = "qup2_se6";
4515 drive-strength = <2>;
4516 bias-pull-down;
4517 };
4518
4519 qup_uart15_default: qup-uart15-default-state {
4520 /* TX, RX */
4521 pins = "gpio30", "gpio31";
4522 function = "qup2_se7";
4523 drive-strength = <2>;
4524 bias-disable;
4525 };
4526
4527 sdc2_sleep: sdc2-sleep-state {
4528 clk-pins {
4529 pins = "sdc2_clk";
4530 drive-strength = <2>;
4531 bias-disable;
4532 };
4533
4534 cmd-pins {
4535 pins = "sdc2_cmd";
4536 drive-strength = <2>;
4537 bias-pull-up;
4538 };
4539
4540 data-pins {
4541 pins = "sdc2_data";
4542 drive-strength = <2>;
4543 bias-pull-up;
4544 };
4545 };
4546
4547 sdc2_default: sdc2-default-state {
4548 clk-pins {
4549 pins = "sdc2_clk";
4550 drive-strength = <16>;
4551 bias-disable;
4552 };
4553
4554 cmd-pins {
4555 pins = "sdc2_cmd";
4556 drive-strength = <10>;
4557 bias-pull-up;
4558 };
4559
4560 data-pins {
4561 pins = "sdc2_data";
4562 drive-strength = <10>;
4563 bias-pull-up;
4564 };
4565 };
4566 };
4567
4568 apps_smmu: iommu@15000000 {
4569 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4570 reg = <0 0x15000000 0 0x100000>;
4571
4572 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4573 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4574 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4575 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4576 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4577 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4578 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4579 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4580 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4581 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4582 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4583 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4595 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4596 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4597 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4598 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4599 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4600 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4601 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4602 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4603 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4604 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4605 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4606 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4607 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4608 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4609 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4610 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4611 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4612 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4613 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4614 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4615 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4616 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4617 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4618 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4619 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4620 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4621 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4622 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4623 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4624 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4625 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4626 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4627 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4628 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4629 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4630 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4631 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4632 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4633 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4634 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4635 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4636 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4637 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4638 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4639 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4640 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4641 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4642 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4643 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4644 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4645 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4646 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4647 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4648 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4649 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4650 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4651 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4652 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4653 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4654 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4655 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4656 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4657 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
4658 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4659 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4660 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4661 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
4662 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4663 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4664 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4665 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4666 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4667 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4668 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
4669
4670 #iommu-cells = <2>;
4671 #global-interrupts = <1>;
4672
4673 dma-coherent;
4674 };
4675
4676 intc: interrupt-controller@17100000 {
4677 compatible = "arm,gic-v3";
4678 reg = <0 0x17100000 0 0x10000>, /* GICD */
4679 <0 0x17180000 0 0x200000>; /* GICR * 8 */
4680
4681 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
4682
4683 #interrupt-cells = <3>;
4684 interrupt-controller;
4685
4686 #redistributor-regions = <1>;
4687 redistributor-stride = <0 0x40000>;
4688
4689 #address-cells = <2>;
4690 #size-cells = <2>;
4691 ranges;
4692
4693 gic_its: msi-controller@17140000 {
4694 compatible = "arm,gic-v3-its";
4695 reg = <0 0x17140000 0 0x20000>;
4696
4697 msi-controller;
4698 #msi-cells = <1>;
4699 };
4700 };
4701
4702 timer@17420000 {
4703 compatible = "arm,armv7-timer-mem";
4704 reg = <0 0x17420000 0 0x1000>;
4705
4706 ranges = <0 0 0 0x20000000>;
4707 #address-cells = <1>;
4708 #size-cells = <1>;
4709
4710 frame@17421000 {
4711 reg = <0x17421000 0x1000>,
4712 <0x17422000 0x1000>;
4713
4714 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4715 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4716
4717 frame-number = <0>;
4718 };
4719
4720 frame@17423000 {
4721 reg = <0x17423000 0x1000>;
4722
4723 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4724
4725 frame-number = <1>;
4726
4727 status = "disabled";
4728 };
4729
4730 frame@17425000 {
4731 reg = <0x17425000 0x1000>;
4732
4733 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4734
4735 frame-number = <2>;
4736
4737 status = "disabled";
4738 };
4739
4740 frame@17427000 {
4741 reg = <0x17427000 0x1000>;
4742
4743 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4744
4745 frame-number = <3>;
4746
4747 status = "disabled";
4748 };
4749
4750 frame@17429000 {
4751 reg = <0x17429000 0x1000>;
4752
4753 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4754
4755 frame-number = <4>;
4756
4757 status = "disabled";
4758 };
4759
4760 frame@1742b000 {
4761 reg = <0x1742b000 0x1000>;
4762
4763 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4764
4765 frame-number = <5>;
4766
4767 status = "disabled";
4768 };
4769
4770 frame@1742d000 {
4771 reg = <0x1742d000 0x1000>;
4772
4773 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4774
4775 frame-number = <6>;
4776
4777 status = "disabled";
4778 };
4779 };
4780
4781 apps_rsc: rsc@17a00000 {
4782 compatible = "qcom,rpmh-rsc";
4783 reg = <0 0x17a00000 0 0x10000>,
4784 <0 0x17a10000 0 0x10000>,
4785 <0 0x17a20000 0 0x10000>,
4786 <0 0x17a30000 0 0x10000>;
4787 reg-names = "drv-0",
4788 "drv-1",
4789 "drv-2";
4790
4791 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4792 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4793 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4794
4795 power-domains = <&CLUSTER_PD>;
4796
4797 qcom,tcs-offset = <0xd00>;
4798 qcom,drv-id = <2>;
4799 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4800 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4801
4802 label = "apps_rsc";
4803
4804 apps_bcm_voter: bcm-voter {
4805 compatible = "qcom,bcm-voter";
4806 };
4807
4808 rpmhcc: clock-controller {
4809 compatible = "qcom,sm8650-rpmh-clk";
4810
4811 clocks = <&xo_board>;
4812 clock-names = "xo";
4813
4814 #clock-cells = <1>;
4815 };
4816
4817 rpmhpd: power-controller {
4818 compatible = "qcom,sm8650-rpmhpd";
4819
4820 operating-points-v2 = <&rpmhpd_opp_table>;
4821
4822 #power-domain-cells = <1>;
4823
4824 rpmhpd_opp_table: opp-table {
4825 compatible = "operating-points-v2";
4826
4827 rpmhpd_opp_ret: opp-16 {
4828 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4829 };
4830
4831 rpmhpd_opp_min_svs: opp-48 {
4832 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4833 };
4834
4835 rpmhpd_opp_low_svs_d2: opp-52 {
4836 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
4837 };
4838
4839 rpmhpd_opp_low_svs_d1: opp-56 {
4840 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4841 };
4842
4843 rpmhpd_opp_low_svs_d0: opp-60 {
4844 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
4845 };
4846
4847 rpmhpd_opp_low_svs: opp-64 {
4848 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4849 };
4850
4851 rpmhpd_opp_low_svs_l1: opp-80 {
4852 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4853 };
4854
4855 rpmhpd_opp_svs: opp-128 {
4856 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4857 };
4858
4859 rpmhpd_opp_svs_l0: opp-144 {
4860 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4861 };
4862
4863 rpmhpd_opp_svs_l1: opp-192 {
4864 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4865 };
4866
4867 rpmhpd_opp_nom: opp-256 {
4868 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4869 };
4870
4871 rpmhpd_opp_nom_l1: opp-320 {
4872 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4873 };
4874
4875 rpmhpd_opp_nom_l2: opp-336 {
4876 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4877 };
4878
4879 rpmhpd_opp_turbo: opp-384 {
4880 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4881 };
4882
4883 rpmhpd_opp_turbo_l1: opp-416 {
4884 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4885 };
4886 };
4887 };
4888 };
4889
4890 cpufreq_hw: cpufreq@17d91000 {
4891 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss";
4892 reg = <0 0x17d91000 0 0x1000>,
4893 <0 0x17d92000 0 0x1000>,
4894 <0 0x17d93000 0 0x1000>,
4895 <0 0x17d94000 0 0x1000>;
4896 reg-names = "freq-domain0",
4897 "freq-domain1",
4898 "freq-domain2",
4899 "freq-domain3";
4900
4901 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4902 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4903 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
4904 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
4905 interrupt-names = "dcvsh-irq-0",
4906 "dcvsh-irq-1",
4907 "dcvsh-irq-2",
4908 "dcvsh-irq-3";
4909
4910 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
4911 clock-names = "xo", "alternate";
4912
4913 #freq-domain-cells = <1>;
4914 #clock-cells = <1>;
4915 };
4916
4917 pmu@24091000 {
4918 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4919 reg = <0 0x24091000 0 0x1000>;
4920
4921 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
4922
4923 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
4924 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
4925
4926 operating-points-v2 = <&llcc_bwmon_opp_table>;
4927
4928 llcc_bwmon_opp_table: opp-table {
4929 compatible = "operating-points-v2";
4930
4931 opp-0 {
4932 opp-peak-kBps = <2086000>;
4933 };
4934
4935 opp-1 {
4936 opp-peak-kBps = <2929000>;
4937 };
4938
4939 opp-2 {
4940 opp-peak-kBps = <5931000>;
4941 };
4942
4943 opp-3 {
4944 opp-peak-kBps = <6515000>;
4945 };
4946
4947 opp-4 {
4948 opp-peak-kBps = <7980000>;
4949 };
4950
4951 opp-5 {
4952 opp-peak-kBps = <10437000>;
4953 };
4954
4955 opp-6 {
4956 opp-peak-kBps = <12157000>;
4957 };
4958
4959 opp-7 {
4960 opp-peak-kBps = <14060000>;
4961 };
4962
4963 opp-8 {
4964 opp-peak-kBps = <16113000>;
4965 };
4966 };
4967 };
4968
4969 pmu@240b7400 {
4970 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon";
4971 reg = <0 0x240b7400 0 0x600>;
4972
4973 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
4974
4975 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
4976 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
4977
4978 operating-points-v2 = <&cpu_bwmon_opp_table>;
4979
4980 cpu_bwmon_opp_table: opp-table {
4981 compatible = "operating-points-v2";
4982
4983 opp-0 {
4984 opp-peak-kBps = <4577000>;
4985 };
4986
4987 opp-1 {
4988 opp-peak-kBps = <7110000>;
4989 };
4990
4991 opp-2 {
4992 opp-peak-kBps = <9155000>;
4993 };
4994
4995 opp-3 {
4996 opp-peak-kBps = <12298000>;
4997 };
4998
4999 opp-4 {
5000 opp-peak-kBps = <14236000>;
5001 };
5002
5003 opp-5 {
5004 opp-peak-kBps = <16265000>;
5005 };
5006 };
5007 };
5008
5009 gem_noc: interconnect@24100000 {
5010 compatible = "qcom,sm8650-gem-noc";
5011 reg = <0 0x24100000 0 0xc5080>;
5012
5013 qcom,bcm-voters = <&apps_bcm_voter>;
5014
5015 #interconnect-cells = <2>;
5016 };
5017
5018 system-cache-controller@25000000 {
5019 compatible = "qcom,sm8650-llcc";
5020 reg = <0 0x25000000 0 0x200000>,
5021 <0 0x25400000 0 0x200000>,
5022 <0 0x25200000 0 0x200000>,
5023 <0 0x25600000 0 0x200000>,
5024 <0 0x25800000 0 0x200000>,
5025 <0 0x25a00000 0 0x200000>;
5026 reg-names = "llcc0_base",
5027 "llcc1_base",
5028 "llcc2_base",
5029 "llcc3_base",
5030 "llcc_broadcast_base",
5031 "llcc_broadcast_and_base";
5032
5033 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
5034 };
5035
5036 remoteproc_adsp: remoteproc@30000000 {
5037 compatible = "qcom,sm8650-adsp-pas";
5038 reg = <0 0x30000000 0 0x100>;
5039
5040 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
5041 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5042 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5043 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5044 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5045 interrupt-names = "wdog",
5046 "fatal",
5047 "ready",
5048 "handover",
5049 "stop-ack";
5050
5051 clocks = <&rpmhcc RPMH_CXO_CLK>;
5052 clock-names = "xo";
5053
5054 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
5055 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
5056
5057 power-domains = <&rpmhpd RPMHPD_LCX>,
5058 <&rpmhpd RPMHPD_LMX>;
5059 power-domain-names = "lcx",
5060 "lmx";
5061
5062 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
5063
5064 qcom,qmp = <&aoss_qmp>;
5065
5066 qcom,smem-states = <&smp2p_adsp_out 0>;
5067 qcom,smem-state-names = "stop";
5068
5069 status = "disabled";
5070
5071 remoteproc_adsp_glink: glink-edge {
5072 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5073 IPCC_MPROC_SIGNAL_GLINK_QMP
5074 IRQ_TYPE_EDGE_RISING>;
5075
5076 mboxes = <&ipcc IPCC_CLIENT_LPASS
5077 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5078
5079 qcom,remote-pid = <2>;
5080
5081 label = "lpass";
5082
5083 fastrpc {
5084 compatible = "qcom,fastrpc";
5085
5086 qcom,glink-channels = "fastrpcglink-apps-dsp";
5087
5088 label = "adsp";
5089
5090 qcom,non-secure-domain;
5091
5092 #address-cells = <1>;
5093 #size-cells = <0>;
5094
5095 compute-cb@3 {
5096 compatible = "qcom,fastrpc-compute-cb";
5097 reg = <3>;
5098
5099 iommus = <&apps_smmu 0x1003 0x80>,
5100 <&apps_smmu 0x1043 0x20>;
5101 dma-coherent;
5102 };
5103
5104 compute-cb@4 {
5105 compatible = "qcom,fastrpc-compute-cb";
5106 reg = <4>;
5107
5108 iommus = <&apps_smmu 0x1004 0x80>,
5109 <&apps_smmu 0x1044 0x20>;
5110 dma-coherent;
5111 };
5112
5113 compute-cb@5 {
5114 compatible = "qcom,fastrpc-compute-cb";
5115 reg = <5>;
5116
5117 iommus = <&apps_smmu 0x1005 0x80>,
5118 <&apps_smmu 0x1045 0x20>;
5119 dma-coherent;
5120 };
5121
5122 compute-cb@6 {
5123 compatible = "qcom,fastrpc-compute-cb";
5124 reg = <6>;
5125
5126 iommus = <&apps_smmu 0x1006 0x80>,
5127 <&apps_smmu 0x1046 0x20>;
5128 dma-coherent;
5129 };
5130
5131 compute-cb@7 {
5132 compatible = "qcom,fastrpc-compute-cb";
5133 reg = <7>;
5134
5135 iommus = <&apps_smmu 0x1007 0x40>,
5136 <&apps_smmu 0x1067 0x0>,
5137 <&apps_smmu 0x1087 0x0>;
5138 dma-coherent;
5139 };
5140 };
5141
5142 gpr {
5143 compatible = "qcom,gpr";
5144 qcom,glink-channels = "adsp_apps";
5145 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
5146 qcom,intents = <512 20>;
5147 #address-cells = <1>;
5148 #size-cells = <0>;
5149
5150 q6apm: service@1 {
5151 compatible = "qcom,q6apm";
5152 reg = <GPR_APM_MODULE_IID>;
5153 #sound-dai-cells = <0>;
5154 qcom,protection-domain = "avs/audio",
5155 "msm/adsp/audio_pd";
5156
5157 q6apmbedai: bedais {
5158 compatible = "qcom,q6apm-lpass-dais";
5159 #sound-dai-cells = <1>;
5160 };
5161
5162 q6apmdai: dais {
5163 compatible = "qcom,q6apm-dais";
5164 iommus = <&apps_smmu 0x1001 0x80>,
5165 <&apps_smmu 0x1061 0x0>;
5166 };
5167 };
5168
5169 q6prm: service@2 {
5170 compatible = "qcom,q6prm";
5171 reg = <GPR_PRM_MODULE_IID>;
5172 qcom,protection-domain = "avs/audio",
5173 "msm/adsp/audio_pd";
5174
5175 q6prmcc: clock-controller {
5176 compatible = "qcom,q6prm-lpass-clocks";
5177 #clock-cells = <2>;
5178 };
5179 };
5180 };
5181 };
5182 };
5183
5184 nsp_noc: interconnect@320c0000 {
5185 compatible = "qcom,sm8650-nsp-noc";
5186 reg = <0 0x320c0000 0 0xf080>;
5187
5188 qcom,bcm-voters = <&apps_bcm_voter>;
5189
5190 #interconnect-cells = <2>;
5191 };
5192
5193 remoteproc_cdsp: remoteproc@32300000 {
5194 compatible = "qcom,sm8650-cdsp-pas";
5195 reg = <0 0x32300000 0 0x1400000>;
5196
5197 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
5198 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
5199 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
5200 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
5201 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
5202 interrupt-names = "wdog",
5203 "fatal",
5204 "ready",
5205 "handover",
5206 "stop-ack";
5207
5208 clocks = <&rpmhcc RPMH_CXO_CLK>;
5209 clock-names = "xo";
5210
5211 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
5212 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
5213
5214 power-domains = <&rpmhpd RPMHPD_CX>,
5215 <&rpmhpd RPMHPD_MXC>,
5216 <&rpmhpd RPMHPD_NSP>;
5217 power-domain-names = "cx",
5218 "mxc",
5219 "nsp";
5220
5221 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>;
5222
5223 qcom,qmp = <&aoss_qmp>;
5224
5225 qcom,smem-states = <&smp2p_cdsp_out 0>;
5226 qcom,smem-state-names = "stop";
5227
5228 status = "disabled";
5229
5230 glink-edge {
5231 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5232 IPCC_MPROC_SIGNAL_GLINK_QMP
5233 IRQ_TYPE_EDGE_RISING>;
5234
5235 mboxes = <&ipcc IPCC_CLIENT_CDSP
5236 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5237
5238 qcom,remote-pid = <5>;
5239
5240 label = "cdsp";
5241
5242 fastrpc {
5243 compatible = "qcom,fastrpc";
5244
5245 qcom,glink-channels = "fastrpcglink-apps-dsp";
5246
5247 label = "cdsp";
5248
5249 qcom,non-secure-domain;
5250
5251 #address-cells = <1>;
5252 #size-cells = <0>;
5253
5254 compute-cb@1 {
5255 compatible = "qcom,fastrpc-compute-cb";
5256 reg = <1>;
5257
5258 iommus = <&apps_smmu 0x1961 0x0>,
5259 <&apps_smmu 0x0c01 0x20>,
5260 <&apps_smmu 0x19c1 0x0>;
5261 dma-coherent;
5262 };
5263
5264 compute-cb@2 {
5265 compatible = "qcom,fastrpc-compute-cb";
5266 reg = <2>;
5267
5268 iommus = <&apps_smmu 0x1962 0x0>,
5269 <&apps_smmu 0x0c02 0x20>,
5270 <&apps_smmu 0x19c2 0x0>;
5271 dma-coherent;
5272 };
5273
5274 compute-cb@3 {
5275 compatible = "qcom,fastrpc-compute-cb";
5276 reg = <3>;
5277
5278 iommus = <&apps_smmu 0x1963 0x0>,
5279 <&apps_smmu 0x0c03 0x20>,
5280 <&apps_smmu 0x19c3 0x0>;
5281 dma-coherent;
5282 };
5283
5284 compute-cb@4 {
5285 compatible = "qcom,fastrpc-compute-cb";
5286 reg = <4>;
5287
5288 iommus = <&apps_smmu 0x1964 0x0>,
5289 <&apps_smmu 0x0c04 0x20>,
5290 <&apps_smmu 0x19c4 0x0>;
5291 dma-coherent;
5292 };
5293
5294 compute-cb@5 {
5295 compatible = "qcom,fastrpc-compute-cb";
5296 reg = <5>;
5297
5298 iommus = <&apps_smmu 0x1965 0x0>,
5299 <&apps_smmu 0x0c05 0x20>,
5300 <&apps_smmu 0x19c5 0x0>;
5301 dma-coherent;
5302 };
5303
5304 compute-cb@6 {
5305 compatible = "qcom,fastrpc-compute-cb";
5306 reg = <6>;
5307
5308 iommus = <&apps_smmu 0x1966 0x0>,
5309 <&apps_smmu 0x0c06 0x20>,
5310 <&apps_smmu 0x19c6 0x0>;
5311 dma-coherent;
5312 };
5313
5314 compute-cb@7 {
5315 compatible = "qcom,fastrpc-compute-cb";
5316 reg = <7>;
5317
5318 iommus = <&apps_smmu 0x1967 0x0>,
5319 <&apps_smmu 0x0c07 0x20>,
5320 <&apps_smmu 0x19c7 0x0>;
5321 dma-coherent;
5322 };
5323
5324 compute-cb@8 {
5325 compatible = "qcom,fastrpc-compute-cb";
5326 reg = <8>;
5327
5328 iommus = <&apps_smmu 0x1968 0x0>,
5329 <&apps_smmu 0x0c08 0x20>,
5330 <&apps_smmu 0x19c8 0x0>;
5331 dma-coherent;
5332 };
5333
5334 /* note: secure cb9 in downstream */
5335
5336 compute-cb@10 {
5337 compatible = "qcom,fastrpc-compute-cb";
5338 reg = <12>;
5339
5340 iommus = <&apps_smmu 0x196c 0x0>,
5341 <&apps_smmu 0x0c0c 0x20>,
5342 <&apps_smmu 0x19cc 0x0>;
5343 dma-coherent;
5344 };
5345
5346 compute-cb@11 {
5347 compatible = "qcom,fastrpc-compute-cb";
5348 reg = <13>;
5349
5350 iommus = <&apps_smmu 0x196d 0x0>,
5351 <&apps_smmu 0x0c0d 0x20>,
5352 <&apps_smmu 0x19cd 0x0>;
5353 dma-coherent;
5354 };
5355
5356 compute-cb@12 {
5357 compatible = "qcom,fastrpc-compute-cb";
5358 reg = <14>;
5359
5360 iommus = <&apps_smmu 0x196e 0x0>,
5361 <&apps_smmu 0x0c0e 0x20>,
5362 <&apps_smmu 0x19ce 0x0>;
5363 dma-coherent;
5364 };
5365 };
5366 };
5367 };
5368 };
5369
5370 thermal-zones {
5371 aoss0-thermal {
5372 thermal-sensors = <&tsens0 0>;
5373
5374 trips {
5375 trip-point0 {
5376 temperature = <90000>;
5377 hysteresis = <2000>;
5378 type = "hot";
5379 };
5380
5381 aoss0-critical {
5382 temperature = <110000>;
5383 hysteresis = <0>;
5384 type = "critical";
5385 };
5386 };
5387 };
5388
5389 cpuss0-thermal {
5390 thermal-sensors = <&tsens0 1>;
5391
5392 trips {
5393 trip-point0 {
5394 temperature = <90000>;
5395 hysteresis = <2000>;
5396 type = "hot";
5397 };
5398
5399 cpuss0-critical {
5400 temperature = <110000>;
5401 hysteresis = <0>;
5402 type = "critical";
5403 };
5404 };
5405 };
5406
5407 cpuss1-thermal {
5408 thermal-sensors = <&tsens0 2>;
5409
5410 trips {
5411 trip-point0 {
5412 temperature = <90000>;
5413 hysteresis = <2000>;
5414 type = "hot";
5415 };
5416
5417 cpuss1-critical {
5418 temperature = <110000>;
5419 hysteresis = <0>;
5420 type = "critical";
5421 };
5422 };
5423 };
5424
5425 cpuss2-thermal {
5426 thermal-sensors = <&tsens0 3>;
5427
5428 trips {
5429 trip-point0 {
5430 temperature = <90000>;
5431 hysteresis = <2000>;
5432 type = "hot";
5433 };
5434
5435 cpuss2-critical {
5436 temperature = <110000>;
5437 hysteresis = <0>;
5438 type = "critical";
5439 };
5440 };
5441 };
5442
5443 cpuss3-thermal {
5444 thermal-sensors = <&tsens0 4>;
5445
5446 trips {
5447 trip-point0 {
5448 temperature = <90000>;
5449 hysteresis = <2000>;
5450 type = "hot";
5451 };
5452
5453 cpuss3-critical {
5454 temperature = <110000>;
5455 hysteresis = <0>;
5456 type = "critical";
5457 };
5458 };
5459 };
5460
5461 cpu2-top-thermal {
5462 thermal-sensors = <&tsens0 5>;
5463
5464 trips {
5465 trip-point0 {
5466 temperature = <90000>;
5467 hysteresis = <2000>;
5468 type = "passive";
5469 };
5470
5471 trip-point1 {
5472 temperature = <95000>;
5473 hysteresis = <2000>;
5474 type = "passive";
5475 };
5476
5477 cpu2-critical {
5478 temperature = <110000>;
5479 hysteresis = <1000>;
5480 type = "critical";
5481 };
5482 };
5483 };
5484
5485 cpu2-bottom-thermal {
5486 thermal-sensors = <&tsens0 6>;
5487
5488 trips {
5489 trip-point0 {
5490 temperature = <90000>;
5491 hysteresis = <2000>;
5492 type = "passive";
5493 };
5494
5495 trip-point1 {
5496 temperature = <95000>;
5497 hysteresis = <2000>;
5498 type = "passive";
5499 };
5500
5501 cpu2-critical {
5502 temperature = <110000>;
5503 hysteresis = <1000>;
5504 type = "critical";
5505 };
5506 };
5507 };
5508
5509 cpu3-top-thermal {
5510 thermal-sensors = <&tsens0 7>;
5511
5512 trips {
5513 trip-point0 {
5514 temperature = <90000>;
5515 hysteresis = <2000>;
5516 type = "passive";
5517 };
5518
5519 trip-point1 {
5520 temperature = <95000>;
5521 hysteresis = <2000>;
5522 type = "passive";
5523 };
5524
5525 cpu3-critical {
5526 temperature = <110000>;
5527 hysteresis = <1000>;
5528 type = "critical";
5529 };
5530 };
5531 };
5532
5533 cpu3-bottom-thermal {
5534 thermal-sensors = <&tsens0 8>;
5535
5536 trips {
5537 trip-point0 {
5538 temperature = <90000>;
5539 hysteresis = <2000>;
5540 type = "passive";
5541 };
5542
5543 trip-point1 {
5544 temperature = <95000>;
5545 hysteresis = <2000>;
5546 type = "passive";
5547 };
5548
5549 cpu3-critical {
5550 temperature = <110000>;
5551 hysteresis = <1000>;
5552 type = "critical";
5553 };
5554 };
5555 };
5556
5557 cpu4-top-thermal {
5558 thermal-sensors = <&tsens0 9>;
5559
5560 trips {
5561 trip-point0 {
5562 temperature = <90000>;
5563 hysteresis = <2000>;
5564 type = "passive";
5565 };
5566
5567 trip-point1 {
5568 temperature = <95000>;
5569 hysteresis = <2000>;
5570 type = "passive";
5571 };
5572
5573 cpu4-critical {
5574 temperature = <110000>;
5575 hysteresis = <1000>;
5576 type = "critical";
5577 };
5578 };
5579 };
5580
5581 cpu4-bottom-thermal {
5582 thermal-sensors = <&tsens0 10>;
5583
5584 trips {
5585 trip-point0 {
5586 temperature = <90000>;
5587 hysteresis = <2000>;
5588 type = "passive";
5589 };
5590
5591 trip-point1 {
5592 temperature = <95000>;
5593 hysteresis = <2000>;
5594 type = "passive";
5595 };
5596
5597 cpu4-critical {
5598 temperature = <110000>;
5599 hysteresis = <1000>;
5600 type = "critical";
5601 };
5602 };
5603 };
5604
5605 cpu5-top-thermal {
5606 thermal-sensors = <&tsens0 11>;
5607
5608 trips {
5609 trip-point0 {
5610 temperature = <90000>;
5611 hysteresis = <2000>;
5612 type = "passive";
5613 };
5614
5615 trip-point1 {
5616 temperature = <95000>;
5617 hysteresis = <2000>;
5618 type = "passive";
5619 };
5620
5621 cpu5-critical {
5622 temperature = <110000>;
5623 hysteresis = <1000>;
5624 type = "critical";
5625 };
5626 };
5627 };
5628
5629 cpu5-bottom-thermal {
5630 thermal-sensors = <&tsens0 12>;
5631
5632 trips {
5633 trip-point0 {
5634 temperature = <90000>;
5635 hysteresis = <2000>;
5636 type = "passive";
5637 };
5638
5639 trip-point1 {
5640 temperature = <95000>;
5641 hysteresis = <2000>;
5642 type = "passive";
5643 };
5644
5645 cpu5-critical {
5646 temperature = <110000>;
5647 hysteresis = <1000>;
5648 type = "critical";
5649 };
5650 };
5651 };
5652
5653 cpu6-top-thermal {
5654 thermal-sensors = <&tsens0 13>;
5655
5656 trips {
5657 trip-point0 {
5658 temperature = <90000>;
5659 hysteresis = <2000>;
5660 type = "passive";
5661 };
5662
5663 trip-point1 {
5664 temperature = <95000>;
5665 hysteresis = <2000>;
5666 type = "passive";
5667 };
5668
5669 cpu6-critical {
5670 temperature = <110000>;
5671 hysteresis = <1000>;
5672 type = "critical";
5673 };
5674 };
5675 };
5676
5677 cpu6-bottom-thermal {
5678 thermal-sensors = <&tsens0 14>;
5679
5680 trips {
5681 trip-point0 {
5682 temperature = <90000>;
5683 hysteresis = <2000>;
5684 type = "passive";
5685 };
5686
5687 trip-point1 {
5688 temperature = <95000>;
5689 hysteresis = <2000>;
5690 type = "passive";
5691 };
5692
5693 cpu6-critical {
5694 temperature = <110000>;
5695 hysteresis = <1000>;
5696 type = "critical";
5697 };
5698 };
5699 };
5700
5701 aoss1-thermal {
5702 thermal-sensors = <&tsens1 0>;
5703
5704 trips {
5705 trip-point0 {
5706 temperature = <90000>;
5707 hysteresis = <2000>;
5708 type = "hot";
5709 };
5710
5711 aoss1-critical {
5712 temperature = <110000>;
5713 hysteresis = <0>;
5714 type = "critical";
5715 };
5716 };
5717 };
5718
5719 cpu7-top-thermal {
5720 thermal-sensors = <&tsens1 1>;
5721
5722 trips {
5723 trip-point0 {
5724 temperature = <90000>;
5725 hysteresis = <2000>;
5726 type = "passive";
5727 };
5728
5729 trip-point1 {
5730 temperature = <95000>;
5731 hysteresis = <2000>;
5732 type = "passive";
5733 };
5734
5735 cpu7-critical {
5736 temperature = <110000>;
5737 hysteresis = <1000>;
5738 type = "critical";
5739 };
5740 };
5741 };
5742
5743 cpu7-middle-thermal {
5744 thermal-sensors = <&tsens1 2>;
5745
5746 trips {
5747 trip-point0 {
5748 temperature = <90000>;
5749 hysteresis = <2000>;
5750 type = "passive";
5751 };
5752
5753 trip-point1 {
5754 temperature = <95000>;
5755 hysteresis = <2000>;
5756 type = "passive";
5757 };
5758
5759 cpu7-critical {
5760 temperature = <110000>;
5761 hysteresis = <1000>;
5762 type = "critical";
5763 };
5764 };
5765 };
5766
5767 cpu7-bottom-thermal {
5768 thermal-sensors = <&tsens1 3>;
5769
5770 trips {
5771 trip-point0 {
5772 temperature = <90000>;
5773 hysteresis = <2000>;
5774 type = "passive";
5775 };
5776
5777 trip-point1 {
5778 temperature = <95000>;
5779 hysteresis = <2000>;
5780 type = "passive";
5781 };
5782
5783 cpu7-critical {
5784 temperature = <110000>;
5785 hysteresis = <1000>;
5786 type = "critical";
5787 };
5788 };
5789 };
5790
5791 cpu0-thermal {
5792 thermal-sensors = <&tsens1 4>;
5793
5794 trips {
5795 trip-point0 {
5796 temperature = <90000>;
5797 hysteresis = <2000>;
5798 type = "passive";
5799 };
5800
5801 trip-point1 {
5802 temperature = <95000>;
5803 hysteresis = <2000>;
5804 type = "passive";
5805 };
5806
5807 cpu0-critical {
5808 temperature = <110000>;
5809 hysteresis = <1000>;
5810 type = "critical";
5811 };
5812 };
5813 };
5814
5815 cpu1-thermal {
5816 thermal-sensors = <&tsens1 5>;
5817
5818 trips {
5819 trip-point0 {
5820 temperature = <90000>;
5821 hysteresis = <2000>;
5822 type = "passive";
5823 };
5824
5825 trip-point1 {
5826 temperature = <95000>;
5827 hysteresis = <2000>;
5828 type = "passive";
5829 };
5830
5831 cpu1-critical {
5832 temperature = <110000>;
5833 hysteresis = <1000>;
5834 type = "critical";
5835 };
5836 };
5837 };
5838
5839 nsphvx0-thermal {
5840 polling-delay-passive = <10>;
5841
5842 thermal-sensors = <&tsens2 6>;
5843
5844 trips {
5845 trip-point0 {
5846 temperature = <90000>;
5847 hysteresis = <2000>;
5848 type = "hot";
5849 };
5850
5851 nsphvx1-critical {
5852 temperature = <110000>;
5853 hysteresis = <0>;
5854 type = "critical";
5855 };
5856 };
5857 };
5858
5859 nsphvx1-thermal {
5860 polling-delay-passive = <10>;
5861
5862 thermal-sensors = <&tsens2 7>;
5863
5864 trips {
5865 trip-point0 {
5866 temperature = <90000>;
5867 hysteresis = <2000>;
5868 type = "hot";
5869 };
5870
5871 nsphvx1-critical {
5872 temperature = <110000>;
5873 hysteresis = <0>;
5874 type = "critical";
5875 };
5876 };
5877 };
5878
5879 nsphmx0-thermal {
5880 polling-delay-passive = <10>;
5881
5882 thermal-sensors = <&tsens2 8>;
5883
5884 trips {
5885 trip-point0 {
5886 temperature = <90000>;
5887 hysteresis = <2000>;
5888 type = "hot";
5889 };
5890
5891 nsphmx0-critical {
5892 temperature = <110000>;
5893 hysteresis = <0>;
5894 type = "critical";
5895 };
5896 };
5897 };
5898
5899 nsphmx1-thermal {
5900 polling-delay-passive = <10>;
5901
5902 thermal-sensors = <&tsens2 9>;
5903
5904 trips {
5905 trip-point0 {
5906 temperature = <90000>;
5907 hysteresis = <2000>;
5908 type = "hot";
5909 };
5910
5911 nsphmx1-critical {
5912 temperature = <110000>;
5913 hysteresis = <0>;
5914 type = "critical";
5915 };
5916 };
5917 };
5918
5919 nsphmx2-thermal {
5920 polling-delay-passive = <10>;
5921
5922 thermal-sensors = <&tsens2 10>;
5923
5924 trips {
5925 trip-point0 {
5926 temperature = <90000>;
5927 hysteresis = <2000>;
5928 type = "hot";
5929 };
5930
5931 nsphmx2-critical {
5932 temperature = <110000>;
5933 hysteresis = <0>;
5934 type = "critical";
5935 };
5936 };
5937 };
5938
5939 nsphmx3-thermal {
5940 polling-delay-passive = <10>;
5941
5942 thermal-sensors = <&tsens2 11>;
5943
5944 trips {
5945 trip-point0 {
5946 temperature = <90000>;
5947 hysteresis = <2000>;
5948 type = "hot";
5949 };
5950
5951 nsphmx3-critical {
5952 temperature = <110000>;
5953 hysteresis = <0>;
5954 type = "critical";
5955 };
5956 };
5957 };
5958
5959 video-thermal {
5960 polling-delay-passive = <10>;
5961
5962 thermal-sensors = <&tsens1 12>;
5963
5964 trips {
5965 trip-point0 {
5966 temperature = <90000>;
5967 hysteresis = <2000>;
5968 type = "hot";
5969 };
5970
5971 video-critical {
5972 temperature = <110000>;
5973 hysteresis = <0>;
5974 type = "critical";
5975 };
5976 };
5977 };
5978
5979 ddr-thermal {
5980 polling-delay-passive = <10>;
5981
5982 thermal-sensors = <&tsens1 13>;
5983
5984 trips {
5985 trip-point0 {
5986 temperature = <90000>;
5987 hysteresis = <2000>;
5988 type = "hot";
5989 };
5990
5991 ddr-critical {
5992 temperature = <110000>;
5993 hysteresis = <0>;
5994 type = "critical";
5995 };
5996 };
5997 };
5998
5999 camera0-thermal {
6000 thermal-sensors = <&tsens1 14>;
6001
6002 trips {
6003 trip-point0 {
6004 temperature = <90000>;
6005 hysteresis = <2000>;
6006 type = "hot";
6007 };
6008
6009 camera0-critical {
6010 temperature = <110000>;
6011 hysteresis = <0>;
6012 type = "critical";
6013 };
6014 };
6015 };
6016
6017 camera1-thermal {
6018 thermal-sensors = <&tsens1 15>;
6019
6020 trips {
6021 trip-point0 {
6022 temperature = <90000>;
6023 hysteresis = <2000>;
6024 type = "hot";
6025 };
6026
6027 camera1-critical {
6028 temperature = <110000>;
6029 hysteresis = <0>;
6030 type = "critical";
6031 };
6032 };
6033 };
6034
6035 aoss2-thermal {
6036 thermal-sensors = <&tsens2 0>;
6037
6038 trips {
6039 trip-point0 {
6040 temperature = <90000>;
6041 hysteresis = <2000>;
6042 type = "hot";
6043 };
6044
6045 aoss2-critical {
6046 temperature = <110000>;
6047 hysteresis = <0>;
6048 type = "critical";
6049 };
6050 };
6051 };
6052
6053 gpuss0-thermal {
6054 polling-delay-passive = <10>;
6055
6056 thermal-sensors = <&tsens2 1>;
6057
6058 cooling-maps {
6059 map0 {
6060 trip = <&gpu0_alert0>;
6061 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6062 };
6063 };
6064
6065 trips {
6066 gpu0_alert0: trip-point0 {
6067 temperature = <85000>;
6068 hysteresis = <1000>;
6069 type = "passive";
6070 };
6071
6072 trip-point1 {
6073 temperature = <90000>;
6074 hysteresis = <1000>;
6075 type = "hot";
6076 };
6077
6078 trip-point2 {
6079 temperature = <110000>;
6080 hysteresis = <1000>;
6081 type = "critical";
6082 };
6083 };
6084 };
6085
6086 gpuss1-thermal {
6087 polling-delay-passive = <10>;
6088
6089 thermal-sensors = <&tsens2 2>;
6090
6091 cooling-maps {
6092 map0 {
6093 trip = <&gpu1_alert0>;
6094 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6095 };
6096 };
6097
6098 trips {
6099 gpu1_alert0: trip-point0 {
6100 temperature = <85000>;
6101 hysteresis = <1000>;
6102 type = "passive";
6103 };
6104
6105 trip-point1 {
6106 temperature = <90000>;
6107 hysteresis = <1000>;
6108 type = "hot";
6109 };
6110
6111 trip-point2 {
6112 temperature = <110000>;
6113 hysteresis = <1000>;
6114 type = "critical";
6115 };
6116 };
6117 };
6118
6119 gpuss2-thermal {
6120 polling-delay-passive = <10>;
6121
6122 thermal-sensors = <&tsens2 3>;
6123
6124 cooling-maps {
6125 map0 {
6126 trip = <&gpu2_alert0>;
6127 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6128 };
6129 };
6130
6131 trips {
6132 gpu2_alert0: trip-point0 {
6133 temperature = <85000>;
6134 hysteresis = <1000>;
6135 type = "passive";
6136 };
6137
6138 trip-point1 {
6139 temperature = <90000>;
6140 hysteresis = <1000>;
6141 type = "hot";
6142 };
6143
6144 trip-point2 {
6145 temperature = <110000>;
6146 hysteresis = <1000>;
6147 type = "critical";
6148 };
6149 };
6150 };
6151
6152 gpuss3-thermal {
6153 polling-delay-passive = <10>;
6154
6155 thermal-sensors = <&tsens2 4>;
6156
6157 cooling-maps {
6158 map0 {
6159 trip = <&gpu3_alert0>;
6160 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6161 };
6162 };
6163
6164 trips {
6165 gpu3_alert0: trip-point0 {
6166 temperature = <85000>;
6167 hysteresis = <1000>;
6168 type = "passive";
6169 };
6170
6171 trip-point1 {
6172 temperature = <90000>;
6173 hysteresis = <1000>;
6174 type = "hot";
6175 };
6176
6177 trip-point2 {
6178 temperature = <110000>;
6179 hysteresis = <1000>;
6180 type = "critical";
6181 };
6182 };
6183 };
6184
6185 gpuss4-thermal {
6186 polling-delay-passive = <10>;
6187
6188 thermal-sensors = <&tsens2 5>;
6189
6190 cooling-maps {
6191 map0 {
6192 trip = <&gpu4_alert0>;
6193 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6194 };
6195 };
6196
6197 trips {
6198 gpu4_alert0: trip-point0 {
6199 temperature = <85000>;
6200 hysteresis = <1000>;
6201 type = "passive";
6202 };
6203
6204 trip-point1 {
6205 temperature = <90000>;
6206 hysteresis = <1000>;
6207 type = "hot";
6208 };
6209
6210 trip-point2 {
6211 temperature = <110000>;
6212 hysteresis = <1000>;
6213 type = "critical";
6214 };
6215 };
6216 };
6217
6218 gpuss5-thermal {
6219 polling-delay-passive = <10>;
6220
6221 thermal-sensors = <&tsens2 6>;
6222
6223 cooling-maps {
6224 map0 {
6225 trip = <&gpu5_alert0>;
6226 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6227 };
6228 };
6229
6230 trips {
6231 gpu5_alert0: trip-point0 {
6232 temperature = <85000>;
6233 hysteresis = <1000>;
6234 type = "passive";
6235 };
6236
6237 trip-point1 {
6238 temperature = <90000>;
6239 hysteresis = <1000>;
6240 type = "hot";
6241 };
6242
6243 trip-point2 {
6244 temperature = <110000>;
6245 hysteresis = <1000>;
6246 type = "critical";
6247 };
6248 };
6249 };
6250
6251 gpuss6-thermal {
6252 polling-delay-passive = <10>;
6253
6254 thermal-sensors = <&tsens2 7>;
6255
6256 cooling-maps {
6257 map0 {
6258 trip = <&gpu6_alert0>;
6259 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6260 };
6261 };
6262
6263 trips {
6264 gpu6_alert0: trip-point0 {
6265 temperature = <85000>;
6266 hysteresis = <1000>;
6267 type = "passive";
6268 };
6269
6270 trip-point1 {
6271 temperature = <90000>;
6272 hysteresis = <1000>;
6273 type = "hot";
6274 };
6275
6276 trip-point2 {
6277 temperature = <110000>;
6278 hysteresis = <1000>;
6279 type = "critical";
6280 };
6281 };
6282 };
6283
6284 gpuss7-thermal {
6285 polling-delay-passive = <10>;
6286
6287 thermal-sensors = <&tsens2 8>;
6288
6289 cooling-maps {
6290 map0 {
6291 trip = <&gpu7_alert0>;
6292 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6293 };
6294 };
6295
6296 trips {
6297 gpu7_alert0: trip-point0 {
6298 temperature = <85000>;
6299 hysteresis = <1000>;
6300 type = "passive";
6301 };
6302
6303 trip-point1 {
6304 temperature = <90000>;
6305 hysteresis = <1000>;
6306 type = "hot";
6307 };
6308
6309 trip-point2 {
6310 temperature = <110000>;
6311 hysteresis = <1000>;
6312 type = "critical";
6313 };
6314 };
6315 };
6316
6317 modem0-thermal {
6318 thermal-sensors = <&tsens2 9>;
6319
6320 trips {
6321 trip-point0 {
6322 temperature = <90000>;
6323 hysteresis = <2000>;
6324 type = "hot";
6325 };
6326
6327 modem0-critical {
6328 temperature = <110000>;
6329 hysteresis = <0>;
6330 type = "critical";
6331 };
6332 };
6333 };
6334
6335 modem1-thermal {
6336 thermal-sensors = <&tsens2 10>;
6337
6338 trips {
6339 trip-point0 {
6340 temperature = <90000>;
6341 hysteresis = <2000>;
6342 type = "hot";
6343 };
6344
6345 modem1-critical {
6346 temperature = <110000>;
6347 hysteresis = <0>;
6348 type = "critical";
6349 };
6350 };
6351 };
6352
6353 modem2-thermal {
6354 thermal-sensors = <&tsens2 11>;
6355
6356 trips {
6357 trip-point0 {
6358 temperature = <90000>;
6359 hysteresis = <2000>;
6360 type = "hot";
6361 };
6362
6363 modem2-critical {
6364 temperature = <110000>;
6365 hysteresis = <0>;
6366 type = "critical";
6367 };
6368 };
6369 };
6370
6371 modem3-thermal {
6372 thermal-sensors = <&tsens2 12>;
6373
6374 trips {
6375 trip-point0 {
6376 temperature = <90000>;
6377 hysteresis = <2000>;
6378 type = "hot";
6379 };
6380
6381 modem3-critical {
6382 temperature = <110000>;
6383 hysteresis = <0>;
6384 type = "critical";
6385 };
6386 };
6387 };
6388 };
6389
6390 timer {
6391 compatible = "arm,armv8-timer";
6392
6393 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
6394 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
6395 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
6396 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
6397 };
6398 };
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