1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
2 /*
3 * Realtek RTD1395 SoC
4 *
5 * Copyright (c) 2019 Andreas Färber
6 */
7
8 #include "rtd139x.dtsi"
9
10 / {
11 compatible = "realtek,rtd1395";
12
13 cpus {
14 #address-cells = <2>;
15 #size-cells = <0>;
16
17 cpu0: cpu@0 {
18 device_type = "cpu";
19 compatible = "arm,cortex-a53";
20 reg = <0x0 0x0>;
21 next-level-cache = <&l2>;
22 };
23
24 cpu1: cpu@1 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a53";
27 reg = <0x0 0x1>;
28 next-level-cache = <&l2>;
29 };
30
31 cpu2: cpu@2 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a53";
34 reg = <0x0 0x2>;
35 next-level-cache = <&l2>;
36 };
37
38 cpu3: cpu@3 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a53";
41 reg = <0x0 0x3>;
42 next-level-cache = <&l2>;
43 };
44
45 l2: l2-cache {
46 compatible = "cache";
47 cache-level = <2>;
48 cache-unified;
49 };
50 };
51
52 timer {
53 compatible = "arm,armv8-timer";
54 interrupts = <GIC_PPI 13
55 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
56 <GIC_PPI 14
57 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
58 <GIC_PPI 11
59 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
60 <GIC_PPI 10
61 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
62 };
63 };
64
65 &arm_pmu {
66 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
67 };
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