1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
2 /*
3 * Realtek RTD16xx SoC family
4 *
5 * Copyright (c) 2019 Realtek Semiconductor Corp.
6 * Copyright (c) 2019 Andreas Färber
7 */
8
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11
12 / {
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 ranges;
21
22 rpc_comm: rpc@2f000 {
23 reg = <0x2f000 0x1000>;
24 };
25
26 rpc_ringbuf: rpc@1ffe000 {
27 reg = <0x1ffe000 0x4000>;
28 };
29
30 tee: tee@10100000 {
31 reg = <0x10100000 0xf00000>;
32 no-map;
33 };
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a55";
43 reg = <0x0>;
44 enable-method = "psci";
45 next-level-cache = <&l2>;
46 };
47
48 cpu1: cpu@100 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a55";
51 reg = <0x100>;
52 enable-method = "psci";
53 next-level-cache = <&l3>;
54 };
55
56 cpu2: cpu@200 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a55";
59 reg = <0x200>;
60 enable-method = "psci";
61 next-level-cache = <&l3>;
62 };
63
64 cpu3: cpu@300 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a55";
67 reg = <0x300>;
68 enable-method = "psci";
69 next-level-cache = <&l3>;
70 };
71
72 cpu4: cpu@400 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a55";
75 reg = <0x400>;
76 enable-method = "psci";
77 next-level-cache = <&l3>;
78 };
79
80 cpu5: cpu@500 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a55";
83 reg = <0x500>;
84 enable-method = "psci";
85 next-level-cache = <&l3>;
86 };
87
88 l2: l2-cache {
89 compatible = "cache";
90 next-level-cache = <&l3>;
91 cache-level = <2>;
92 cache-unified;
93
94 };
95
96 l3: l3-cache {
97 compatible = "cache";
98 cache-level = <3>;
99 cache-unified;
100 };
101 };
102
103 timer {
104 compatible = "arm,armv8-timer";
105 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
106 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
107 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
108 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
109 };
110
111 arm_pmu: pmu {
112 compatible = "arm,cortex-a55-pmu";
113 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
114 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
115 <&cpu3>, <&cpu4>, <&cpu5>;
116 };
117
118 psci {
119 compatible = "arm,psci-1.0";
120 method = "smc";
121 };
122
123 osc27M: osc {
124 compatible = "fixed-clock";
125 clock-frequency = <27000000>;
126 clock-output-names = "osc27M";
127 #clock-cells = <0>;
128 };
129
130 soc@0 {
131 compatible = "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 ranges = <0x00000000 0x00000000 0x0002e000>, /* boot ROM */
135 <0x98000000 0x98000000 0x68000000>;
136
137 rbus: bus@98000000 {
138 compatible = "simple-bus";
139 reg = <0x98000000 0x200000>;
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0x0 0x98000000 0x200000>;
143
144 crt: syscon@0 {
145 compatible = "syscon", "simple-mfd";
146 reg = <0x0 0x1000>;
147 reg-io-width = <4>;
148 #address-cells = <1>;
149 #size-cells = <1>;
150 ranges = <0x0 0x0 0x1000>;
151 };
152
153 iso: syscon@7000 {
154 compatible = "syscon", "simple-mfd";
155 reg = <0x7000 0x1000>;
156 reg-io-width = <4>;
157 #address-cells = <1>;
158 #size-cells = <1>;
159 ranges = <0x0 0x7000 0x1000>;
160 };
161
162 sb2: syscon@1a000 {
163 compatible = "syscon", "simple-mfd";
164 reg = <0x1a000 0x1000>;
165 reg-io-width = <4>;
166 #address-cells = <1>;
167 #size-cells = <1>;
168 ranges = <0x0 0x1a000 0x1000>;
169 };
170
171 misc: syscon@1b000 {
172 compatible = "syscon", "simple-mfd";
173 reg = <0x1b000 0x1000>;
174 reg-io-width = <4>;
175 #address-cells = <1>;
176 #size-cells = <1>;
177 ranges = <0x0 0x1b000 0x1000>;
178 };
179
180 scpu_wrapper: syscon@1d000 {
181 compatible = "syscon", "simple-mfd";
182 reg = <0x1d000 0x1000>;
183 reg-io-width = <4>;
184 #address-cells = <1>;
185 #size-cells = <1>;
186 ranges = <0x0 0x1d000 0x1000>;
187 };
188 };
189
190 gic: interrupt-controller@ff100000 {
191 compatible = "arm,gic-v3";
192 reg = <0xff100000 0x10000>,
193 <0xff140000 0xc0000>;
194 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
195 interrupt-controller;
196 #interrupt-cells = <3>;
197 };
198 };
199 };
200
201 &iso {
202 uart0: serial@800 {
203 compatible = "snps,dw-apb-uart";
204 reg = <0x800 0x400>;
205 reg-shift = <2>;
206 reg-io-width = <4>;
207 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
208 clock-frequency = <27000000>;
209 status = "disabled";
210 };
211 };
212
213 &misc {
214 uart1: serial@200 {
215 compatible = "snps,dw-apb-uart";
216 reg = <0x200 0x400>;
217 reg-shift = <2>;
218 reg-io-width = <4>;
219 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
220 clock-frequency = <432000000>;
221 status = "disabled";
222 };
223
224 uart2: serial@400 {
225 compatible = "snps,dw-apb-uart";
226 reg = <0x400 0x400>;
227 reg-shift = <2>;
228 reg-io-width = <4>;
229 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
230 clock-frequency = <432000000>;
231 status = "disabled";
232 };
233 };
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