1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h>
11
12 / {
13 compatible = "renesas,r8a774c0";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 /*
18 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default.
20 * Boards that provide audio clocks should override them.
21 */
22 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <0>;
26 };
27
28 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <0>;
32 };
33
34 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <0>;
38 };
39
40 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <0>;
45 };
46
47 cluster1_opp: opp-table-1 {
48 compatible = "operating-points-v2";
49 opp-shared;
50 opp-800000000 {
51 opp-hz = /bits/ 64 <800000000>;
52 clock-latency-ns = <300000>;
53 };
54 opp-1000000000 {
55 opp-hz = /bits/ 64 <1000000000>;
56 clock-latency-ns = <300000>;
57 };
58 opp-1200000000 {
59 opp-hz = /bits/ 64 <1200000000>;
60 clock-latency-ns = <300000>;
61 opp-suspend;
62 };
63 };
64
65 cpus {
66 #address-cells = <1>;
67 #size-cells = <0>;
68
69 a53_0: cpu@0 {
70 compatible = "arm,cortex-a53";
71 reg = <0>;
72 device_type = "cpu";
73 #cooling-cells = <2>;
74 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
75 next-level-cache = <&L2_CA53>;
76 enable-method = "psci";
77 dynamic-power-coefficient = <277>;
78 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
79 operating-points-v2 = <&cluster1_opp>;
80 };
81
82 a53_1: cpu@1 {
83 compatible = "arm,cortex-a53";
84 reg = <1>;
85 device_type = "cpu";
86 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
87 next-level-cache = <&L2_CA53>;
88 enable-method = "psci";
89 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
90 operating-points-v2 = <&cluster1_opp>;
91 };
92
93 L2_CA53: cache-controller-0 {
94 compatible = "cache";
95 power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
96 cache-unified;
97 cache-level = <2>;
98 };
99 };
100
101 extal_clk: extal {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 /* This value must be overridden by the board */
105 clock-frequency = <0>;
106 };
107
108 /* External PCIe clock - can be overridden by the board */
109 pcie_bus_clk: pcie_bus {
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 clock-frequency = <0>;
113 };
114
115 pmu_a53 {
116 compatible = "arm,cortex-a53-pmu";
117 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
118 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-affinity = <&a53_0>, <&a53_1>;
120 };
121
122 psci {
123 compatible = "arm,psci-1.0", "arm,psci-0.2";
124 method = "smc";
125 };
126
127 /* External SCIF clock - to be overridden by boards that provide it */
128 scif_clk: scif {
129 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 clock-frequency = <0>;
132 };
133
134 soc: soc {
135 compatible = "simple-bus";
136 interrupt-parent = <&gic>;
137 #address-cells = <2>;
138 #size-cells = <2>;
139 ranges;
140
141 rwdt: watchdog@e6020000 {
142 compatible = "renesas,r8a774c0-wdt",
143 "renesas,rcar-gen3-wdt";
144 reg = <0 0xe6020000 0 0x0c>;
145 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&cpg CPG_MOD 402>;
147 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
148 resets = <&cpg 402>;
149 status = "disabled";
150 };
151
152 gpio0: gpio@e6050000 {
153 compatible = "renesas,gpio-r8a774c0",
154 "renesas,rcar-gen3-gpio";
155 reg = <0 0xe6050000 0 0x50>;
156 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
157 #gpio-cells = <2>;
158 gpio-controller;
159 gpio-ranges = <&pfc 0 0 18>;
160 #interrupt-cells = <2>;
161 interrupt-controller;
162 clocks = <&cpg CPG_MOD 912>;
163 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
164 resets = <&cpg 912>;
165 };
166
167 gpio1: gpio@e6051000 {
168 compatible = "renesas,gpio-r8a774c0",
169 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6051000 0 0x50>;
171 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>;
173 gpio-controller;
174 gpio-ranges = <&pfc 0 32 23>;
175 #interrupt-cells = <2>;
176 interrupt-controller;
177 clocks = <&cpg CPG_MOD 911>;
178 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
179 resets = <&cpg 911>;
180 };
181
182 gpio2: gpio@e6052000 {
183 compatible = "renesas,gpio-r8a774c0",
184 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6052000 0 0x50>;
186 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>;
188 gpio-controller;
189 gpio-ranges = <&pfc 0 64 26>;
190 #interrupt-cells = <2>;
191 interrupt-controller;
192 clocks = <&cpg CPG_MOD 910>;
193 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
194 resets = <&cpg 910>;
195 };
196
197 gpio3: gpio@e6053000 {
198 compatible = "renesas,gpio-r8a774c0",
199 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6053000 0 0x50>;
201 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>;
203 gpio-controller;
204 gpio-ranges = <&pfc 0 96 16>;
205 #interrupt-cells = <2>;
206 interrupt-controller;
207 clocks = <&cpg CPG_MOD 909>;
208 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
209 resets = <&cpg 909>;
210 };
211
212 gpio4: gpio@e6054000 {
213 compatible = "renesas,gpio-r8a774c0",
214 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6054000 0 0x50>;
216 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>;
218 gpio-controller;
219 gpio-ranges = <&pfc 0 128 11>;
220 #interrupt-cells = <2>;
221 interrupt-controller;
222 clocks = <&cpg CPG_MOD 908>;
223 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
224 resets = <&cpg 908>;
225 };
226
227 gpio5: gpio@e6055000 {
228 compatible = "renesas,gpio-r8a774c0",
229 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6055000 0 0x50>;
231 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>;
233 gpio-controller;
234 gpio-ranges = <&pfc 0 160 20>;
235 #interrupt-cells = <2>;
236 interrupt-controller;
237 clocks = <&cpg CPG_MOD 907>;
238 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
239 resets = <&cpg 907>;
240 };
241
242 gpio6: gpio@e6055400 {
243 compatible = "renesas,gpio-r8a774c0",
244 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055400 0 0x50>;
246 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>;
248 gpio-controller;
249 gpio-ranges = <&pfc 0 192 18>;
250 #interrupt-cells = <2>;
251 interrupt-controller;
252 clocks = <&cpg CPG_MOD 906>;
253 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
254 resets = <&cpg 906>;
255 };
256
257 pfc: pinctrl@e6060000 {
258 compatible = "renesas,pfc-r8a774c0";
259 reg = <0 0xe6060000 0 0x508>;
260 };
261
262 cmt0: timer@e60f0000 {
263 compatible = "renesas,r8a774c0-cmt0",
264 "renesas,rcar-gen3-cmt0";
265 reg = <0 0xe60f0000 0 0x1004>;
266 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&cpg CPG_MOD 303>;
269 clock-names = "fck";
270 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
271 resets = <&cpg 303>;
272 status = "disabled";
273 };
274
275 cmt1: timer@e6130000 {
276 compatible = "renesas,r8a774c0-cmt1",
277 "renesas,rcar-gen3-cmt1";
278 reg = <0 0xe6130000 0 0x1004>;
279 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&cpg CPG_MOD 302>;
288 clock-names = "fck";
289 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
290 resets = <&cpg 302>;
291 status = "disabled";
292 };
293
294 cmt2: timer@e6140000 {
295 compatible = "renesas,r8a774c0-cmt1",
296 "renesas,rcar-gen3-cmt1";
297 reg = <0 0xe6140000 0 0x1004>;
298 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&cpg CPG_MOD 301>;
307 clock-names = "fck";
308 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
309 resets = <&cpg 301>;
310 status = "disabled";
311 };
312
313 cmt3: timer@e6148000 {
314 compatible = "renesas,r8a774c0-cmt1",
315 "renesas,rcar-gen3-cmt1";
316 reg = <0 0xe6148000 0 0x1004>;
317 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cpg CPG_MOD 300>;
326 clock-names = "fck";
327 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
328 resets = <&cpg 300>;
329 status = "disabled";
330 };
331
332 cpg: clock-controller@e6150000 {
333 compatible = "renesas,r8a774c0-cpg-mssr";
334 reg = <0 0xe6150000 0 0x1000>;
335 clocks = <&extal_clk>;
336 clock-names = "extal";
337 #clock-cells = <2>;
338 #power-domain-cells = <0>;
339 #reset-cells = <1>;
340 };
341
342 rst: reset-controller@e6160000 {
343 compatible = "renesas,r8a774c0-rst";
344 reg = <0 0xe6160000 0 0x0200>;
345 };
346
347 sysc: system-controller@e6180000 {
348 compatible = "renesas,r8a774c0-sysc";
349 reg = <0 0xe6180000 0 0x0400>;
350 #power-domain-cells = <1>;
351 };
352
353 thermal: thermal@e6190000 {
354 compatible = "renesas,thermal-r8a774c0";
355 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
356 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cpg CPG_MOD 522>;
360 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
361 resets = <&cpg 522>;
362 #thermal-sensor-cells = <0>;
363 };
364
365 intc_ex: interrupt-controller@e61c0000 {
366 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
367 #interrupt-cells = <2>;
368 interrupt-controller;
369 reg = <0 0xe61c0000 0 0x200>;
370 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cpg CPG_MOD 407>;
377 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
378 resets = <&cpg 407>;
379 };
380
381 tmu0: timer@e61e0000 {
382 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
383 reg = <0 0xe61e0000 0 0x30>;
384 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
387 interrupt-names = "tuni0", "tuni1", "tuni2";
388 clocks = <&cpg CPG_MOD 125>;
389 clock-names = "fck";
390 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
391 resets = <&cpg 125>;
392 status = "disabled";
393 };
394
395 tmu1: timer@e6fc0000 {
396 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
397 reg = <0 0xe6fc0000 0 0x30>;
398 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
403 clocks = <&cpg CPG_MOD 124>;
404 clock-names = "fck";
405 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
406 resets = <&cpg 124>;
407 status = "disabled";
408 };
409
410 tmu2: timer@e6fd0000 {
411 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
412 reg = <0 0xe6fd0000 0 0x30>;
413 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
417 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
418 clocks = <&cpg CPG_MOD 123>;
419 clock-names = "fck";
420 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
421 resets = <&cpg 123>;
422 status = "disabled";
423 };
424
425 tmu3: timer@e6fe0000 {
426 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
427 reg = <0 0xe6fe0000 0 0x30>;
428 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-names = "tuni0", "tuni1", "tuni2";
432 clocks = <&cpg CPG_MOD 122>;
433 clock-names = "fck";
434 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
435 resets = <&cpg 122>;
436 status = "disabled";
437 };
438
439 tmu4: timer@ffc00000 {
440 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
441 reg = <0 0xffc00000 0 0x30>;
442 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-names = "tuni0", "tuni1", "tuni2";
446 clocks = <&cpg CPG_MOD 121>;
447 clock-names = "fck";
448 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
449 resets = <&cpg 121>;
450 status = "disabled";
451 };
452
453 i2c0: i2c@e6500000 {
454 #address-cells = <1>;
455 #size-cells = <0>;
456 compatible = "renesas,i2c-r8a774c0",
457 "renesas,rcar-gen3-i2c";
458 reg = <0 0xe6500000 0 0x40>;
459 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 931>;
461 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
462 resets = <&cpg 931>;
463 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
464 <&dmac2 0x91>, <&dmac2 0x90>;
465 dma-names = "tx", "rx", "tx", "rx";
466 i2c-scl-internal-delay-ns = <110>;
467 status = "disabled";
468 };
469
470 i2c1: i2c@e6508000 {
471 #address-cells = <1>;
472 #size-cells = <0>;
473 compatible = "renesas,i2c-r8a774c0",
474 "renesas,rcar-gen3-i2c";
475 reg = <0 0xe6508000 0 0x40>;
476 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cpg CPG_MOD 930>;
478 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
479 resets = <&cpg 930>;
480 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
481 <&dmac2 0x93>, <&dmac2 0x92>;
482 dma-names = "tx", "rx", "tx", "rx";
483 i2c-scl-internal-delay-ns = <6>;
484 status = "disabled";
485 };
486
487 i2c2: i2c@e6510000 {
488 #address-cells = <1>;
489 #size-cells = <0>;
490 compatible = "renesas,i2c-r8a774c0",
491 "renesas,rcar-gen3-i2c";
492 reg = <0 0xe6510000 0 0x40>;
493 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cpg CPG_MOD 929>;
495 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
496 resets = <&cpg 929>;
497 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
498 <&dmac2 0x95>, <&dmac2 0x94>;
499 dma-names = "tx", "rx", "tx", "rx";
500 i2c-scl-internal-delay-ns = <6>;
501 status = "disabled";
502 };
503
504 i2c3: i2c@e66d0000 {
505 #address-cells = <1>;
506 #size-cells = <0>;
507 compatible = "renesas,i2c-r8a774c0",
508 "renesas,rcar-gen3-i2c";
509 reg = <0 0xe66d0000 0 0x40>;
510 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cpg CPG_MOD 928>;
512 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
513 resets = <&cpg 928>;
514 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
515 dma-names = "tx", "rx";
516 i2c-scl-internal-delay-ns = <110>;
517 status = "disabled";
518 };
519
520 i2c4: i2c@e66d8000 {
521 #address-cells = <1>;
522 #size-cells = <0>;
523 compatible = "renesas,i2c-r8a774c0",
524 "renesas,rcar-gen3-i2c";
525 reg = <0 0xe66d8000 0 0x40>;
526 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cpg CPG_MOD 927>;
528 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
529 resets = <&cpg 927>;
530 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
531 dma-names = "tx", "rx";
532 i2c-scl-internal-delay-ns = <6>;
533 status = "disabled";
534 };
535
536 i2c5: i2c@e66e0000 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 compatible = "renesas,i2c-r8a774c0",
540 "renesas,rcar-gen3-i2c";
541 reg = <0 0xe66e0000 0 0x40>;
542 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cpg CPG_MOD 919>;
544 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
545 resets = <&cpg 919>;
546 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
547 dma-names = "tx", "rx";
548 i2c-scl-internal-delay-ns = <6>;
549 status = "disabled";
550 };
551
552 i2c6: i2c@e66e8000 {
553 #address-cells = <1>;
554 #size-cells = <0>;
555 compatible = "renesas,i2c-r8a774c0",
556 "renesas,rcar-gen3-i2c";
557 reg = <0 0xe66e8000 0 0x40>;
558 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&cpg CPG_MOD 918>;
560 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
561 resets = <&cpg 918>;
562 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
563 dma-names = "tx", "rx";
564 i2c-scl-internal-delay-ns = <6>;
565 status = "disabled";
566 };
567
568 i2c7: i2c@e6690000 {
569 #address-cells = <1>;
570 #size-cells = <0>;
571 compatible = "renesas,i2c-r8a774c0",
572 "renesas,rcar-gen3-i2c";
573 reg = <0 0xe6690000 0 0x40>;
574 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&cpg CPG_MOD 1003>;
576 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
577 resets = <&cpg 1003>;
578 i2c-scl-internal-delay-ns = <6>;
579 status = "disabled";
580 };
581
582 iic_pmic: i2c@e60b0000 {
583 #address-cells = <1>;
584 #size-cells = <0>;
585 compatible = "renesas,iic-r8a774c0",
586 "renesas,rcar-gen3-iic",
587 "renesas,rmobile-iic";
588 reg = <0 0xe60b0000 0 0x425>;
589 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 926>;
591 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
592 resets = <&cpg 926>;
593 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
594 dma-names = "tx", "rx";
595 status = "disabled";
596 };
597
598 hscif0: serial@e6540000 {
599 compatible = "renesas,hscif-r8a774c0",
600 "renesas,rcar-gen3-hscif",
601 "renesas,hscif";
602 reg = <0 0xe6540000 0 0x60>;
603 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cpg CPG_MOD 520>,
605 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
606 <&scif_clk>;
607 clock-names = "fck", "brg_int", "scif_clk";
608 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
609 <&dmac2 0x31>, <&dmac2 0x30>;
610 dma-names = "tx", "rx", "tx", "rx";
611 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
612 resets = <&cpg 520>;
613 status = "disabled";
614 };
615
616 hscif1: serial@e6550000 {
617 compatible = "renesas,hscif-r8a774c0",
618 "renesas,rcar-gen3-hscif",
619 "renesas,hscif";
620 reg = <0 0xe6550000 0 0x60>;
621 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&cpg CPG_MOD 519>,
623 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
624 <&scif_clk>;
625 clock-names = "fck", "brg_int", "scif_clk";
626 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
627 <&dmac2 0x33>, <&dmac2 0x32>;
628 dma-names = "tx", "rx", "tx", "rx";
629 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
630 resets = <&cpg 519>;
631 status = "disabled";
632 };
633
634 hscif2: serial@e6560000 {
635 compatible = "renesas,hscif-r8a774c0",
636 "renesas,rcar-gen3-hscif",
637 "renesas,hscif";
638 reg = <0 0xe6560000 0 0x60>;
639 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&cpg CPG_MOD 518>,
641 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
642 <&scif_clk>;
643 clock-names = "fck", "brg_int", "scif_clk";
644 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
645 <&dmac2 0x35>, <&dmac2 0x34>;
646 dma-names = "tx", "rx", "tx", "rx";
647 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
648 resets = <&cpg 518>;
649 status = "disabled";
650 };
651
652 hscif3: serial@e66a0000 {
653 compatible = "renesas,hscif-r8a774c0",
654 "renesas,rcar-gen3-hscif",
655 "renesas,hscif";
656 reg = <0 0xe66a0000 0 0x60>;
657 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&cpg CPG_MOD 517>,
659 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
660 <&scif_clk>;
661 clock-names = "fck", "brg_int", "scif_clk";
662 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
663 dma-names = "tx", "rx";
664 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
665 resets = <&cpg 517>;
666 status = "disabled";
667 };
668
669 hscif4: serial@e66b0000 {
670 compatible = "renesas,hscif-r8a774c0",
671 "renesas,rcar-gen3-hscif",
672 "renesas,hscif";
673 reg = <0 0xe66b0000 0 0x60>;
674 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&cpg CPG_MOD 516>,
676 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
677 <&scif_clk>;
678 clock-names = "fck", "brg_int", "scif_clk";
679 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
680 dma-names = "tx", "rx";
681 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
682 resets = <&cpg 516>;
683 status = "disabled";
684 };
685
686 hsusb: usb@e6590000 {
687 compatible = "renesas,usbhs-r8a774c0",
688 "renesas,rcar-gen3-usbhs";
689 reg = <0 0xe6590000 0 0x200>;
690 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
692 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
693 <&usb_dmac1 0>, <&usb_dmac1 1>;
694 dma-names = "ch0", "ch1", "ch2", "ch3";
695 renesas,buswait = <11>;
696 phys = <&usb2_phy0 3>;
697 phy-names = "usb";
698 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
699 resets = <&cpg 704>, <&cpg 703>;
700 status = "disabled";
701 };
702
703 usb_dmac0: dma-controller@e65a0000 {
704 compatible = "renesas,r8a774c0-usb-dmac",
705 "renesas,usb-dmac";
706 reg = <0 0xe65a0000 0 0x100>;
707 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-names = "ch0", "ch1";
710 clocks = <&cpg CPG_MOD 330>;
711 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
712 resets = <&cpg 330>;
713 #dma-cells = <1>;
714 dma-channels = <2>;
715 };
716
717 usb_dmac1: dma-controller@e65b0000 {
718 compatible = "renesas,r8a774c0-usb-dmac",
719 "renesas,usb-dmac";
720 reg = <0 0xe65b0000 0 0x100>;
721 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
723 interrupt-names = "ch0", "ch1";
724 clocks = <&cpg CPG_MOD 331>;
725 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
726 resets = <&cpg 331>;
727 #dma-cells = <1>;
728 dma-channels = <2>;
729 };
730
731 dmac0: dma-controller@e6700000 {
732 compatible = "renesas,dmac-r8a774c0",
733 "renesas,rcar-dmac";
734 reg = <0 0xe6700000 0 0x10000>;
735 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
752 interrupt-names = "error",
753 "ch0", "ch1", "ch2", "ch3",
754 "ch4", "ch5", "ch6", "ch7",
755 "ch8", "ch9", "ch10", "ch11",
756 "ch12", "ch13", "ch14", "ch15";
757 clocks = <&cpg CPG_MOD 219>;
758 clock-names = "fck";
759 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
760 resets = <&cpg 219>;
761 #dma-cells = <1>;
762 dma-channels = <16>;
763 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
764 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
765 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
766 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
767 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
768 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
769 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
770 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
771 };
772
773 dmac1: dma-controller@e7300000 {
774 compatible = "renesas,dmac-r8a774c0",
775 "renesas,rcar-dmac";
776 reg = <0 0xe7300000 0 0x10000>;
777 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
794 interrupt-names = "error",
795 "ch0", "ch1", "ch2", "ch3",
796 "ch4", "ch5", "ch6", "ch7",
797 "ch8", "ch9", "ch10", "ch11",
798 "ch12", "ch13", "ch14", "ch15";
799 clocks = <&cpg CPG_MOD 218>;
800 clock-names = "fck";
801 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
802 resets = <&cpg 218>;
803 #dma-cells = <1>;
804 dma-channels = <16>;
805 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
806 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
807 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
808 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
809 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
810 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
811 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
812 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
813 };
814
815 dmac2: dma-controller@e7310000 {
816 compatible = "renesas,dmac-r8a774c0",
817 "renesas,rcar-dmac";
818 reg = <0 0xe7310000 0 0x10000>;
819 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
825 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
826 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
828 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
829 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
830 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
832 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "error",
837 "ch0", "ch1", "ch2", "ch3",
838 "ch4", "ch5", "ch6", "ch7",
839 "ch8", "ch9", "ch10", "ch11",
840 "ch12", "ch13", "ch14", "ch15";
841 clocks = <&cpg CPG_MOD 217>;
842 clock-names = "fck";
843 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
844 resets = <&cpg 217>;
845 #dma-cells = <1>;
846 dma-channels = <16>;
847 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
848 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
849 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
850 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
851 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
852 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
853 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
854 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
855 };
856
857 ipmmu_ds0: iommu@e6740000 {
858 compatible = "renesas,ipmmu-r8a774c0";
859 reg = <0 0xe6740000 0 0x1000>;
860 renesas,ipmmu-main = <&ipmmu_mm 0>;
861 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
862 #iommu-cells = <1>;
863 };
864
865 ipmmu_ds1: iommu@e7740000 {
866 compatible = "renesas,ipmmu-r8a774c0";
867 reg = <0 0xe7740000 0 0x1000>;
868 renesas,ipmmu-main = <&ipmmu_mm 1>;
869 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
870 #iommu-cells = <1>;
871 };
872
873 ipmmu_hc: iommu@e6570000 {
874 compatible = "renesas,ipmmu-r8a774c0";
875 reg = <0 0xe6570000 0 0x1000>;
876 renesas,ipmmu-main = <&ipmmu_mm 2>;
877 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
878 #iommu-cells = <1>;
879 };
880
881 ipmmu_mm: iommu@e67b0000 {
882 compatible = "renesas,ipmmu-r8a774c0";
883 reg = <0 0xe67b0000 0 0x1000>;
884 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
886 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
887 #iommu-cells = <1>;
888 };
889
890 ipmmu_mp: iommu@ec670000 {
891 compatible = "renesas,ipmmu-r8a774c0";
892 reg = <0 0xec670000 0 0x1000>;
893 renesas,ipmmu-main = <&ipmmu_mm 4>;
894 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
895 #iommu-cells = <1>;
896 };
897
898 ipmmu_pv0: iommu@fd800000 {
899 compatible = "renesas,ipmmu-r8a774c0";
900 reg = <0 0xfd800000 0 0x1000>;
901 renesas,ipmmu-main = <&ipmmu_mm 6>;
902 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
903 #iommu-cells = <1>;
904 };
905
906 ipmmu_vc0: iommu@fe6b0000 {
907 compatible = "renesas,ipmmu-r8a774c0";
908 reg = <0 0xfe6b0000 0 0x1000>;
909 renesas,ipmmu-main = <&ipmmu_mm 12>;
910 power-domains = <&sysc R8A774C0_PD_A3VC>;
911 #iommu-cells = <1>;
912 };
913
914 ipmmu_vi0: iommu@febd0000 {
915 compatible = "renesas,ipmmu-r8a774c0";
916 reg = <0 0xfebd0000 0 0x1000>;
917 renesas,ipmmu-main = <&ipmmu_mm 14>;
918 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
919 #iommu-cells = <1>;
920 };
921
922 ipmmu_vp0: iommu@fe990000 {
923 compatible = "renesas,ipmmu-r8a774c0";
924 reg = <0 0xfe990000 0 0x1000>;
925 renesas,ipmmu-main = <&ipmmu_mm 16>;
926 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
927 #iommu-cells = <1>;
928 };
929
930 avb: ethernet@e6800000 {
931 compatible = "renesas,etheravb-r8a774c0",
932 "renesas,etheravb-rcar-gen3";
933 reg = <0 0xe6800000 0 0x800>;
934 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
959 interrupt-names = "ch0", "ch1", "ch2", "ch3",
960 "ch4", "ch5", "ch6", "ch7",
961 "ch8", "ch9", "ch10", "ch11",
962 "ch12", "ch13", "ch14", "ch15",
963 "ch16", "ch17", "ch18", "ch19",
964 "ch20", "ch21", "ch22", "ch23",
965 "ch24";
966 clocks = <&cpg CPG_MOD 812>;
967 clock-names = "fck";
968 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
969 resets = <&cpg 812>;
970 phy-mode = "rgmii";
971 rx-internal-delay-ps = <0>;
972 iommus = <&ipmmu_ds0 16>;
973 #address-cells = <1>;
974 #size-cells = <0>;
975 status = "disabled";
976 };
977
978 can0: can@e6c30000 {
979 compatible = "renesas,can-r8a774c0",
980 "renesas,rcar-gen3-can";
981 reg = <0 0xe6c30000 0 0x1000>;
982 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&cpg CPG_MOD 916>,
984 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
985 <&can_clk>;
986 clock-names = "clkp1", "clkp2", "can_clk";
987 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
988 assigned-clock-rates = <40000000>;
989 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
990 resets = <&cpg 916>;
991 status = "disabled";
992 };
993
994 can1: can@e6c38000 {
995 compatible = "renesas,can-r8a774c0",
996 "renesas,rcar-gen3-can";
997 reg = <0 0xe6c38000 0 0x1000>;
998 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&cpg CPG_MOD 915>,
1000 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1001 <&can_clk>;
1002 clock-names = "clkp1", "clkp2", "can_clk";
1003 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1004 assigned-clock-rates = <40000000>;
1005 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1006 resets = <&cpg 915>;
1007 status = "disabled";
1008 };
1009
1010 canfd: can@e66c0000 {
1011 compatible = "renesas,r8a774c0-canfd",
1012 "renesas,rcar-gen3-canfd";
1013 reg = <0 0xe66c0000 0 0x8000>;
1014 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1016 interrupt-names = "ch_int", "g_int";
1017 clocks = <&cpg CPG_MOD 914>,
1018 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1019 <&can_clk>;
1020 clock-names = "fck", "canfd", "can_clk";
1021 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1022 assigned-clock-rates = <40000000>;
1023 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1024 resets = <&cpg 914>;
1025 status = "disabled";
1026
1027 channel0 {
1028 status = "disabled";
1029 };
1030
1031 channel1 {
1032 status = "disabled";
1033 };
1034 };
1035
1036 pwm0: pwm@e6e30000 {
1037 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1038 reg = <0 0xe6e30000 0 0x8>;
1039 clocks = <&cpg CPG_MOD 523>;
1040 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1041 resets = <&cpg 523>;
1042 #pwm-cells = <2>;
1043 status = "disabled";
1044 };
1045
1046 pwm1: pwm@e6e31000 {
1047 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1048 reg = <0 0xe6e31000 0 0x8>;
1049 clocks = <&cpg CPG_MOD 523>;
1050 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1051 resets = <&cpg 523>;
1052 #pwm-cells = <2>;
1053 status = "disabled";
1054 };
1055
1056 pwm2: pwm@e6e32000 {
1057 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1058 reg = <0 0xe6e32000 0 0x8>;
1059 clocks = <&cpg CPG_MOD 523>;
1060 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1061 resets = <&cpg 523>;
1062 #pwm-cells = <2>;
1063 status = "disabled";
1064 };
1065
1066 pwm3: pwm@e6e33000 {
1067 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1068 reg = <0 0xe6e33000 0 0x8>;
1069 clocks = <&cpg CPG_MOD 523>;
1070 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1071 resets = <&cpg 523>;
1072 #pwm-cells = <2>;
1073 status = "disabled";
1074 };
1075
1076 pwm4: pwm@e6e34000 {
1077 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1078 reg = <0 0xe6e34000 0 0x8>;
1079 clocks = <&cpg CPG_MOD 523>;
1080 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1081 resets = <&cpg 523>;
1082 #pwm-cells = <2>;
1083 status = "disabled";
1084 };
1085
1086 pwm5: pwm@e6e35000 {
1087 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1088 reg = <0 0xe6e35000 0 0x8>;
1089 clocks = <&cpg CPG_MOD 523>;
1090 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1091 resets = <&cpg 523>;
1092 #pwm-cells = <2>;
1093 status = "disabled";
1094 };
1095
1096 pwm6: pwm@e6e36000 {
1097 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1098 reg = <0 0xe6e36000 0 0x8>;
1099 clocks = <&cpg CPG_MOD 523>;
1100 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1101 resets = <&cpg 523>;
1102 #pwm-cells = <2>;
1103 status = "disabled";
1104 };
1105
1106 scif0: serial@e6e60000 {
1107 compatible = "renesas,scif-r8a774c0",
1108 "renesas,rcar-gen3-scif", "renesas,scif";
1109 reg = <0 0xe6e60000 0 64>;
1110 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1111 clocks = <&cpg CPG_MOD 207>,
1112 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1113 <&scif_clk>;
1114 clock-names = "fck", "brg_int", "scif_clk";
1115 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1116 <&dmac2 0x51>, <&dmac2 0x50>;
1117 dma-names = "tx", "rx", "tx", "rx";
1118 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1119 resets = <&cpg 207>;
1120 status = "disabled";
1121 };
1122
1123 scif1: serial@e6e68000 {
1124 compatible = "renesas,scif-r8a774c0",
1125 "renesas,rcar-gen3-scif", "renesas,scif";
1126 reg = <0 0xe6e68000 0 64>;
1127 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1128 clocks = <&cpg CPG_MOD 206>,
1129 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1130 <&scif_clk>;
1131 clock-names = "fck", "brg_int", "scif_clk";
1132 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1133 <&dmac2 0x53>, <&dmac2 0x52>;
1134 dma-names = "tx", "rx", "tx", "rx";
1135 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1136 resets = <&cpg 206>;
1137 status = "disabled";
1138 };
1139
1140 scif2: serial@e6e88000 {
1141 compatible = "renesas,scif-r8a774c0",
1142 "renesas,rcar-gen3-scif", "renesas,scif";
1143 reg = <0 0xe6e88000 0 64>;
1144 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&cpg CPG_MOD 310>,
1146 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1147 <&scif_clk>;
1148 clock-names = "fck", "brg_int", "scif_clk";
1149 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1150 <&dmac2 0x13>, <&dmac2 0x12>;
1151 dma-names = "tx", "rx", "tx", "rx";
1152 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1153 resets = <&cpg 310>;
1154 status = "disabled";
1155 };
1156
1157 scif3: serial@e6c50000 {
1158 compatible = "renesas,scif-r8a774c0",
1159 "renesas,rcar-gen3-scif", "renesas,scif";
1160 reg = <0 0xe6c50000 0 64>;
1161 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&cpg CPG_MOD 204>,
1163 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1164 <&scif_clk>;
1165 clock-names = "fck", "brg_int", "scif_clk";
1166 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1167 dma-names = "tx", "rx";
1168 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1169 resets = <&cpg 204>;
1170 status = "disabled";
1171 };
1172
1173 scif4: serial@e6c40000 {
1174 compatible = "renesas,scif-r8a774c0",
1175 "renesas,rcar-gen3-scif", "renesas,scif";
1176 reg = <0 0xe6c40000 0 64>;
1177 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cpg CPG_MOD 203>,
1179 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1180 <&scif_clk>;
1181 clock-names = "fck", "brg_int", "scif_clk";
1182 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1183 dma-names = "tx", "rx";
1184 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1185 resets = <&cpg 203>;
1186 status = "disabled";
1187 };
1188
1189 scif5: serial@e6f30000 {
1190 compatible = "renesas,scif-r8a774c0",
1191 "renesas,rcar-gen3-scif", "renesas,scif";
1192 reg = <0 0xe6f30000 0 64>;
1193 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cpg CPG_MOD 202>,
1195 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1196 <&scif_clk>;
1197 clock-names = "fck", "brg_int", "scif_clk";
1198 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1199 dma-names = "tx", "rx";
1200 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1201 resets = <&cpg 202>;
1202 status = "disabled";
1203 };
1204
1205 msiof0: spi@e6e90000 {
1206 compatible = "renesas,msiof-r8a774c0",
1207 "renesas,rcar-gen3-msiof";
1208 reg = <0 0xe6e90000 0 0x0064>;
1209 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MOD 211>;
1211 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1212 <&dmac2 0x41>, <&dmac2 0x40>;
1213 dma-names = "tx", "rx", "tx", "rx";
1214 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1215 resets = <&cpg 211>;
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1218 status = "disabled";
1219 };
1220
1221 msiof1: spi@e6ea0000 {
1222 compatible = "renesas,msiof-r8a774c0",
1223 "renesas,rcar-gen3-msiof";
1224 reg = <0 0xe6ea0000 0 0x0064>;
1225 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cpg CPG_MOD 210>;
1227 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1228 dma-names = "tx", "rx";
1229 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1230 resets = <&cpg 210>;
1231 #address-cells = <1>;
1232 #size-cells = <0>;
1233 status = "disabled";
1234 };
1235
1236 msiof2: spi@e6c00000 {
1237 compatible = "renesas,msiof-r8a774c0",
1238 "renesas,rcar-gen3-msiof";
1239 reg = <0 0xe6c00000 0 0x0064>;
1240 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&cpg CPG_MOD 209>;
1242 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1243 dma-names = "tx", "rx";
1244 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1245 resets = <&cpg 209>;
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1248 status = "disabled";
1249 };
1250
1251 msiof3: spi@e6c10000 {
1252 compatible = "renesas,msiof-r8a774c0",
1253 "renesas,rcar-gen3-msiof";
1254 reg = <0 0xe6c10000 0 0x0064>;
1255 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&cpg CPG_MOD 208>;
1257 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1258 dma-names = "tx", "rx";
1259 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1260 resets = <&cpg 208>;
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1263 status = "disabled";
1264 };
1265
1266 vin4: video@e6ef4000 {
1267 compatible = "renesas,vin-r8a774c0";
1268 reg = <0 0xe6ef4000 0 0x1000>;
1269 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1270 clocks = <&cpg CPG_MOD 807>;
1271 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1272 resets = <&cpg 807>;
1273 renesas,id = <4>;
1274 status = "disabled";
1275
1276 ports {
1277 #address-cells = <1>;
1278 #size-cells = <0>;
1279
1280 port@1 {
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1283
1284 reg = <1>;
1285
1286 vin4csi40: endpoint@2 {
1287 reg = <2>;
1288 remote-endpoint = <&csi40vin4>;
1289 };
1290 };
1291 };
1292 };
1293
1294 vin5: video@e6ef5000 {
1295 compatible = "renesas,vin-r8a774c0";
1296 reg = <0 0xe6ef5000 0 0x1000>;
1297 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&cpg CPG_MOD 806>;
1299 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1300 resets = <&cpg 806>;
1301 renesas,id = <5>;
1302 status = "disabled";
1303
1304 ports {
1305 #address-cells = <1>;
1306 #size-cells = <0>;
1307
1308 port@1 {
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1311
1312 reg = <1>;
1313
1314 vin5csi40: endpoint@2 {
1315 reg = <2>;
1316 remote-endpoint = <&csi40vin5>;
1317 };
1318 };
1319 };
1320 };
1321
1322 rcar_sound: sound@ec500000 {
1323 /*
1324 * #sound-dai-cells is required if simple-card
1325 *
1326 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1327 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1328 */
1329 /*
1330 * #clock-cells is required for audio_clkout0/1/2/3
1331 *
1332 * clkout : #clock-cells = <0>; <&rcar_sound>;
1333 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1334 */
1335 compatible = "renesas,rcar_sound-r8a774c0",
1336 "renesas,rcar_sound-gen3";
1337 reg = <0 0xec500000 0 0x1000>, /* SCU */
1338 <0 0xec5a0000 0 0x100>, /* ADG */
1339 <0 0xec540000 0 0x1000>, /* SSIU */
1340 <0 0xec541000 0 0x280>, /* SSI */
1341 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1342 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1343
1344 clocks = <&cpg CPG_MOD 1005>,
1345 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1346 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1347 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1348 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1349 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1350 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1351 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1352 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1353 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1354 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1355 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1356 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1357 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1358 <&audio_clk_a>, <&audio_clk_b>,
1359 <&audio_clk_c>,
1360 <&cpg CPG_MOD 922>;
1361 clock-names = "ssi-all",
1362 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1363 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1364 "ssi.1", "ssi.0",
1365 "src.9", "src.8", "src.7", "src.6",
1366 "src.5", "src.4", "src.3", "src.2",
1367 "src.1", "src.0",
1368 "mix.1", "mix.0",
1369 "ctu.1", "ctu.0",
1370 "dvc.0", "dvc.1",
1371 "clk_a", "clk_b", "clk_c", "clk_i";
1372 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1373 resets = <&cpg 1005>,
1374 <&cpg 1006>, <&cpg 1007>,
1375 <&cpg 1008>, <&cpg 1009>,
1376 <&cpg 1010>, <&cpg 1011>,
1377 <&cpg 1012>, <&cpg 1013>,
1378 <&cpg 1014>, <&cpg 1015>;
1379 reset-names = "ssi-all",
1380 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1381 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1382 "ssi.1", "ssi.0";
1383 status = "disabled";
1384
1385 rcar_sound,ctu {
1386 ctu00: ctu-0 { };
1387 ctu01: ctu-1 { };
1388 ctu02: ctu-2 { };
1389 ctu03: ctu-3 { };
1390 ctu10: ctu-4 { };
1391 ctu11: ctu-5 { };
1392 ctu12: ctu-6 { };
1393 ctu13: ctu-7 { };
1394 };
1395
1396 rcar_sound,dvc {
1397 dvc0: dvc-0 {
1398 dmas = <&audma0 0xbc>;
1399 dma-names = "tx";
1400 };
1401 dvc1: dvc-1 {
1402 dmas = <&audma0 0xbe>;
1403 dma-names = "tx";
1404 };
1405 };
1406
1407 rcar_sound,mix {
1408 mix0: mix-0 { };
1409 mix1: mix-1 { };
1410 };
1411
1412 rcar_sound,src {
1413 src0: src-0 {
1414 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1415 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1416 dma-names = "rx", "tx";
1417 };
1418 src1: src-1 {
1419 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1420 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1421 dma-names = "rx", "tx";
1422 };
1423 src2: src-2 {
1424 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1425 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1426 dma-names = "rx", "tx";
1427 };
1428 src3: src-3 {
1429 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1430 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1431 dma-names = "rx", "tx";
1432 };
1433 src4: src-4 {
1434 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1436 dma-names = "rx", "tx";
1437 };
1438 src5: src-5 {
1439 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1440 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1441 dma-names = "rx", "tx";
1442 };
1443 src6: src-6 {
1444 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1445 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1446 dma-names = "rx", "tx";
1447 };
1448 src7: src-7 {
1449 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1450 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1451 dma-names = "rx", "tx";
1452 };
1453 src8: src-8 {
1454 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1455 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1456 dma-names = "rx", "tx";
1457 };
1458 src9: src-9 {
1459 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1460 dmas = <&audma0 0x97>, <&audma0 0xba>;
1461 dma-names = "rx", "tx";
1462 };
1463 };
1464
1465 rcar_sound,ssi {
1466 ssi0: ssi-0 {
1467 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1468 dmas = <&audma0 0x01>, <&audma0 0x02>,
1469 <&audma0 0x15>, <&audma0 0x16>;
1470 dma-names = "rx", "tx", "rxu", "txu";
1471 };
1472 ssi1: ssi-1 {
1473 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1474 dmas = <&audma0 0x03>, <&audma0 0x04>,
1475 <&audma0 0x49>, <&audma0 0x4a>;
1476 dma-names = "rx", "tx", "rxu", "txu";
1477 };
1478 ssi2: ssi-2 {
1479 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&audma0 0x05>, <&audma0 0x06>,
1481 <&audma0 0x63>, <&audma0 0x64>;
1482 dma-names = "rx", "tx", "rxu", "txu";
1483 };
1484 ssi3: ssi-3 {
1485 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1486 dmas = <&audma0 0x07>, <&audma0 0x08>,
1487 <&audma0 0x6f>, <&audma0 0x70>;
1488 dma-names = "rx", "tx", "rxu", "txu";
1489 };
1490 ssi4: ssi-4 {
1491 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1492 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1493 <&audma0 0x71>, <&audma0 0x72>;
1494 dma-names = "rx", "tx", "rxu", "txu";
1495 };
1496 ssi5: ssi-5 {
1497 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1498 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1499 <&audma0 0x73>, <&audma0 0x74>;
1500 dma-names = "rx", "tx", "rxu", "txu";
1501 };
1502 ssi6: ssi-6 {
1503 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1504 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1505 <&audma0 0x75>, <&audma0 0x76>;
1506 dma-names = "rx", "tx", "rxu", "txu";
1507 };
1508 ssi7: ssi-7 {
1509 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1510 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1511 <&audma0 0x79>, <&audma0 0x7a>;
1512 dma-names = "rx", "tx", "rxu", "txu";
1513 };
1514 ssi8: ssi-8 {
1515 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1516 dmas = <&audma0 0x11>, <&audma0 0x12>,
1517 <&audma0 0x7b>, <&audma0 0x7c>;
1518 dma-names = "rx", "tx", "rxu", "txu";
1519 };
1520 ssi9: ssi-9 {
1521 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1522 dmas = <&audma0 0x13>, <&audma0 0x14>,
1523 <&audma0 0x7d>, <&audma0 0x7e>;
1524 dma-names = "rx", "tx", "rxu", "txu";
1525 };
1526 };
1527 };
1528
1529 audma0: dma-controller@ec700000 {
1530 compatible = "renesas,dmac-r8a774c0",
1531 "renesas,rcar-dmac";
1532 reg = <0 0xec700000 0 0x10000>;
1533 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1541 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1542 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1543 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1544 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1545 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1546 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1547 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1548 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1549 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1550 interrupt-names = "error",
1551 "ch0", "ch1", "ch2", "ch3",
1552 "ch4", "ch5", "ch6", "ch7",
1553 "ch8", "ch9", "ch10", "ch11",
1554 "ch12", "ch13", "ch14", "ch15";
1555 clocks = <&cpg CPG_MOD 502>;
1556 clock-names = "fck";
1557 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1558 resets = <&cpg 502>;
1559 #dma-cells = <1>;
1560 dma-channels = <16>;
1561 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1562 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1563 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1564 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1565 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1566 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1567 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1568 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1569 };
1570
1571 xhci0: usb@ee000000 {
1572 compatible = "renesas,xhci-r8a774c0",
1573 "renesas,rcar-gen3-xhci";
1574 reg = <0 0xee000000 0 0xc00>;
1575 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1576 clocks = <&cpg CPG_MOD 328>;
1577 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1578 resets = <&cpg 328>;
1579 status = "disabled";
1580 };
1581
1582 usb3_peri0: usb@ee020000 {
1583 compatible = "renesas,r8a774c0-usb3-peri",
1584 "renesas,rcar-gen3-usb3-peri";
1585 reg = <0 0xee020000 0 0x400>;
1586 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1587 clocks = <&cpg CPG_MOD 328>;
1588 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1589 resets = <&cpg 328>;
1590 status = "disabled";
1591 };
1592
1593 ohci0: usb@ee080000 {
1594 compatible = "generic-ohci";
1595 reg = <0 0xee080000 0 0x100>;
1596 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1597 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1598 phys = <&usb2_phy0 1>;
1599 phy-names = "usb";
1600 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1601 resets = <&cpg 703>, <&cpg 704>;
1602 status = "disabled";
1603 };
1604
1605 ehci0: usb@ee080100 {
1606 compatible = "generic-ehci";
1607 reg = <0 0xee080100 0 0x100>;
1608 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1609 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1610 phys = <&usb2_phy0 2>;
1611 phy-names = "usb";
1612 companion = <&ohci0>;
1613 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1614 resets = <&cpg 703>, <&cpg 704>;
1615 status = "disabled";
1616 };
1617
1618 usb2_phy0: usb-phy@ee080200 {
1619 compatible = "renesas,usb2-phy-r8a774c0",
1620 "renesas,rcar-gen3-usb2-phy";
1621 reg = <0 0xee080200 0 0x700>;
1622 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1623 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1624 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1625 resets = <&cpg 703>, <&cpg 704>;
1626 #phy-cells = <1>;
1627 status = "disabled";
1628 };
1629
1630 sdhi0: mmc@ee100000 {
1631 compatible = "renesas,sdhi-r8a774c0",
1632 "renesas,rcar-gen3-sdhi";
1633 reg = <0 0xee100000 0 0x2000>;
1634 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1635 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>;
1636 clock-names = "core", "clkh";
1637 max-frequency = <200000000>;
1638 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1639 resets = <&cpg 314>;
1640 status = "disabled";
1641 };
1642
1643 sdhi1: mmc@ee120000 {
1644 compatible = "renesas,sdhi-r8a774c0",
1645 "renesas,rcar-gen3-sdhi";
1646 reg = <0 0xee120000 0 0x2000>;
1647 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1648 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>;
1649 clock-names = "core", "clkh";
1650 max-frequency = <200000000>;
1651 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1652 resets = <&cpg 313>;
1653 status = "disabled";
1654 };
1655
1656 sdhi3: mmc@ee160000 {
1657 compatible = "renesas,sdhi-r8a774c0",
1658 "renesas,rcar-gen3-sdhi";
1659 reg = <0 0xee160000 0 0x2000>;
1660 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1661 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>;
1662 clock-names = "core", "clkh";
1663 max-frequency = <200000000>;
1664 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1665 resets = <&cpg 311>;
1666 status = "disabled";
1667 };
1668
1669 rpc: spi@ee200000 {
1670 compatible = "renesas,r8a774c0-rpc-if",
1671 "renesas,rcar-gen3-rpc-if";
1672 reg = <0 0xee200000 0 0x200>,
1673 <0 0x08000000 0 0x4000000>,
1674 <0 0xee208000 0 0x100>;
1675 reg-names = "regs", "dirmap", "wbuf";
1676 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1677 clocks = <&cpg CPG_MOD 917>;
1678 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1679 resets = <&cpg 917>;
1680 #address-cells = <1>;
1681 #size-cells = <0>;
1682 status = "disabled";
1683 };
1684
1685 gic: interrupt-controller@f1010000 {
1686 compatible = "arm,gic-400";
1687 #interrupt-cells = <3>;
1688 #address-cells = <0>;
1689 interrupt-controller;
1690 reg = <0x0 0xf1010000 0 0x1000>,
1691 <0x0 0xf1020000 0 0x20000>,
1692 <0x0 0xf1040000 0 0x20000>,
1693 <0x0 0xf1060000 0 0x20000>;
1694 interrupts = <GIC_PPI 9
1695 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1696 clocks = <&cpg CPG_MOD 408>;
1697 clock-names = "clk";
1698 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1699 resets = <&cpg 408>;
1700 };
1701
1702 pciec0: pcie@fe000000 {
1703 compatible = "renesas,pcie-r8a774c0",
1704 "renesas,pcie-rcar-gen3";
1705 reg = <0 0xfe000000 0 0x80000>;
1706 #address-cells = <3>;
1707 #size-cells = <2>;
1708 bus-range = <0x00 0xff>;
1709 device_type = "pci";
1710 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1711 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1712 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1713 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1714 /* Map all possible DDR/IOMMU as inbound ranges */
1715 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1716 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1717 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1718 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1719 #interrupt-cells = <1>;
1720 interrupt-map-mask = <0 0 0 0>;
1721 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1722 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1723 clock-names = "pcie", "pcie_bus";
1724 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1725 resets = <&cpg 319>;
1726 iommu-map = <0 &ipmmu_hc 0 1>;
1727 iommu-map-mask = <0>;
1728 status = "disabled";
1729 };
1730
1731 pciec0_ep: pcie-ep@fe000000 {
1732 compatible = "renesas,r8a774c0-pcie-ep",
1733 "renesas,rcar-gen3-pcie-ep";
1734 reg = <0x0 0xfe000000 0 0x80000>,
1735 <0x0 0xfe100000 0 0x100000>,
1736 <0x0 0xfe200000 0 0x200000>,
1737 <0x0 0x30000000 0 0x8000000>,
1738 <0x0 0x38000000 0 0x8000000>;
1739 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
1740 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1743 clocks = <&cpg CPG_MOD 319>;
1744 clock-names = "pcie";
1745 resets = <&cpg 319>;
1746 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1747 status = "disabled";
1748 };
1749
1750 vspb0: vsp@fe960000 {
1751 compatible = "renesas,vsp2";
1752 reg = <0 0xfe960000 0 0x8000>;
1753 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1754 clocks = <&cpg CPG_MOD 626>;
1755 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1756 resets = <&cpg 626>;
1757 renesas,fcp = <&fcpvb0>;
1758 };
1759
1760 vspd0: vsp@fea20000 {
1761 compatible = "renesas,vsp2";
1762 reg = <0 0xfea20000 0 0x7000>;
1763 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1764 clocks = <&cpg CPG_MOD 623>;
1765 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1766 resets = <&cpg 623>;
1767 renesas,fcp = <&fcpvd0>;
1768 };
1769
1770 vspd1: vsp@fea28000 {
1771 compatible = "renesas,vsp2";
1772 reg = <0 0xfea28000 0 0x7000>;
1773 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1774 clocks = <&cpg CPG_MOD 622>;
1775 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1776 resets = <&cpg 622>;
1777 renesas,fcp = <&fcpvd1>;
1778 };
1779
1780 vspi0: vsp@fe9a0000 {
1781 compatible = "renesas,vsp2";
1782 reg = <0 0xfe9a0000 0 0x8000>;
1783 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1784 clocks = <&cpg CPG_MOD 631>;
1785 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1786 resets = <&cpg 631>;
1787 renesas,fcp = <&fcpvi0>;
1788 };
1789
1790 fcpvb0: fcp@fe96f000 {
1791 compatible = "renesas,fcpv";
1792 reg = <0 0xfe96f000 0 0x200>;
1793 clocks = <&cpg CPG_MOD 607>;
1794 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1795 resets = <&cpg 607>;
1796 iommus = <&ipmmu_vp0 5>;
1797 };
1798
1799 fcpvd0: fcp@fea27000 {
1800 compatible = "renesas,fcpv";
1801 reg = <0 0xfea27000 0 0x200>;
1802 clocks = <&cpg CPG_MOD 603>;
1803 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1804 resets = <&cpg 603>;
1805 iommus = <&ipmmu_vi0 8>;
1806 };
1807
1808 fcpvd1: fcp@fea2f000 {
1809 compatible = "renesas,fcpv";
1810 reg = <0 0xfea2f000 0 0x200>;
1811 clocks = <&cpg CPG_MOD 602>;
1812 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1813 resets = <&cpg 602>;
1814 iommus = <&ipmmu_vi0 9>;
1815 };
1816
1817 fcpvi0: fcp@fe9af000 {
1818 compatible = "renesas,fcpv";
1819 reg = <0 0xfe9af000 0 0x200>;
1820 clocks = <&cpg CPG_MOD 611>;
1821 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1822 resets = <&cpg 611>;
1823 iommus = <&ipmmu_vp0 8>;
1824 };
1825
1826 csi40: csi2@feaa0000 {
1827 compatible = "renesas,r8a774c0-csi2";
1828 reg = <0 0xfeaa0000 0 0x10000>;
1829 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1830 clocks = <&cpg CPG_MOD 716>;
1831 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1832 resets = <&cpg 716>;
1833 status = "disabled";
1834
1835 ports {
1836 #address-cells = <1>;
1837 #size-cells = <0>;
1838
1839 port@0 {
1840 reg = <0>;
1841 };
1842
1843 port@1 {
1844 #address-cells = <1>;
1845 #size-cells = <0>;
1846
1847 reg = <1>;
1848
1849 csi40vin4: endpoint@0 {
1850 reg = <0>;
1851 remote-endpoint = <&vin4csi40>;
1852 };
1853 csi40vin5: endpoint@1 {
1854 reg = <1>;
1855 remote-endpoint = <&vin5csi40>;
1856 };
1857 };
1858 };
1859 };
1860
1861 du: display@feb00000 {
1862 compatible = "renesas,du-r8a774c0";
1863 reg = <0 0xfeb00000 0 0x40000>;
1864 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1865 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1866 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1867 clock-names = "du.0", "du.1";
1868 resets = <&cpg 724>;
1869 reset-names = "du.0";
1870 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1871
1872 status = "disabled";
1873
1874 ports {
1875 #address-cells = <1>;
1876 #size-cells = <0>;
1877
1878 port@0 {
1879 reg = <0>;
1880 };
1881
1882 port@1 {
1883 reg = <1>;
1884 du_out_lvds0: endpoint {
1885 remote-endpoint = <&lvds0_in>;
1886 };
1887 };
1888
1889 port@2 {
1890 reg = <2>;
1891 du_out_lvds1: endpoint {
1892 remote-endpoint = <&lvds1_in>;
1893 };
1894 };
1895 };
1896 };
1897
1898 lvds0: lvds-encoder@feb90000 {
1899 compatible = "renesas,r8a774c0-lvds";
1900 reg = <0 0xfeb90000 0 0x20>;
1901 clocks = <&cpg CPG_MOD 727>;
1902 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1903 resets = <&cpg 727>;
1904 status = "disabled";
1905
1906 renesas,companion = <&lvds1>;
1907
1908 ports {
1909 #address-cells = <1>;
1910 #size-cells = <0>;
1911
1912 port@0 {
1913 reg = <0>;
1914 lvds0_in: endpoint {
1915 remote-endpoint = <&du_out_lvds0>;
1916 };
1917 };
1918
1919 port@1 {
1920 reg = <1>;
1921 };
1922 };
1923 };
1924
1925 lvds1: lvds-encoder@feb90100 {
1926 compatible = "renesas,r8a774c0-lvds";
1927 reg = <0 0xfeb90100 0 0x20>;
1928 clocks = <&cpg CPG_MOD 727>;
1929 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1930 resets = <&cpg 726>;
1931 status = "disabled";
1932
1933 ports {
1934 #address-cells = <1>;
1935 #size-cells = <0>;
1936
1937 port@0 {
1938 reg = <0>;
1939 lvds1_in: endpoint {
1940 remote-endpoint = <&du_out_lvds1>;
1941 };
1942 };
1943
1944 port@1 {
1945 reg = <1>;
1946 };
1947 };
1948 };
1949
1950 prr: chipid@fff00044 {
1951 compatible = "renesas,prr";
1952 reg = <0 0xfff00044 0 4>;
1953 };
1954 };
1955
1956 thermal-zones {
1957 cpu-thermal {
1958 polling-delay-passive = <250>;
1959 polling-delay = <0>;
1960 thermal-sensors = <&thermal>;
1961 sustainable-power = <717>;
1962
1963 cooling-maps {
1964 map0 {
1965 trip = <&target>;
1966 cooling-device = <&a53_0 0 2>;
1967 contribution = <1024>;
1968 };
1969 };
1970
1971 trips {
1972 sensor1_crit: sensor1-crit {
1973 temperature = <120000>;
1974 hysteresis = <2000>;
1975 type = "critical";
1976 };
1977
1978 target: trip-point1 {
1979 temperature = <100000>;
1980 hysteresis = <2000>;
1981 type = "passive";
1982 };
1983 };
1984 };
1985 };
1986
1987 timer {
1988 compatible = "arm,armv8-timer";
1989 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1990 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1991 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1992 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1993 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
1994 };
1995
1996 /* External USB clocks - can be overridden by the board */
1997 usb3s0_clk: usb3s0 {
1998 compatible = "fixed-clock";
1999 #clock-cells = <0>;
2000 clock-frequency = <0>;
2001 };
2002
2003 usb_extal_clk: usb_extal {
2004 compatible = "fixed-clock";
2005 #clock-cells = <0>;
2006 clock-frequency = <0>;
2007 };
2008 };
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