1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the V3H Starter Kit board
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9 /dts-v1/;
10 #include "r8a77980.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12
13 / {
14 model = "Renesas V3H Starter Kit board";
15 compatible = "renesas,v3hsk", "renesas,r8a77980";
16
17 aliases {
18 i2c0 = &i2c0;
19 i2c1 = &i2c1;
20 i2c2 = &i2c2;
21 i2c3 = &i2c3;
22 i2c4 = &i2c4;
23 i2c5 = &i2c5;
24 serial0 = &scif0;
25 ethernet0 = &gether;
26 };
27
28 chosen {
29 stdout-path = "serial0:115200n8";
30 };
31
32 hdmi-out {
33 compatible = "hdmi-connector";
34 type = "a";
35
36 port {
37 hdmi_con: endpoint {
38 remote-endpoint = <&adv7511_out>;
39 };
40 };
41 };
42
43 lvds-decoder {
44 compatible = "thine,thc63lvd1024";
45 vcc-supply = <&vcc3v3_d5>;
46
47 ports {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 port@0 {
52 reg = <0>;
53 thc63lvd1024_in: endpoint {
54 remote-endpoint = <&lvds0_out>;
55 };
56 };
57
58 port@2 {
59 reg = <2>;
60 thc63lvd1024_out: endpoint {
61 remote-endpoint = <&adv7511_in>;
62 };
63 };
64 };
65 };
66
67 memory@48000000 {
68 device_type = "memory";
69 /* first 128MB is reserved for secure area. */
70 reg = <0 0x48000000 0 0x78000000>;
71 };
72
73 osc1_clk: osc1-clock {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <148500000>;
77 };
78
79 vcc1v8_d4: regulator-0 {
80 compatible = "regulator-fixed";
81 regulator-name = "VCC1V8_D4";
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <1800000>;
84 regulator-boot-on;
85 regulator-always-on;
86 };
87
88 vcc3v3_d5: regulator-1 {
89 compatible = "regulator-fixed";
90 regulator-name = "VCC3V3_D5";
91 regulator-min-microvolt = <3300000>;
92 regulator-max-microvolt = <3300000>;
93 regulator-boot-on;
94 regulator-always-on;
95 };
96 };
97
98 &du {
99 clocks = <&cpg CPG_MOD 724>,
100 <&osc1_clk>;
101 clock-names = "du.0", "dclkin.0";
102 status = "okay";
103 };
104
105 &extal_clk {
106 clock-frequency = <16666666>;
107 };
108
109 &extalr_clk {
110 clock-frequency = <32768>;
111 };
112
113 &gether {
114 pinctrl-0 = <&gether_pins>;
115 pinctrl-names = "default";
116
117 phy-mode = "rgmii";
118 phy-handle = <&phy0>;
119 renesas,no-ether-link;
120 status = "okay";
121
122 phy0: ethernet-phy@0 {
123 compatible = "ethernet-phy-id0022.1622",
124 "ethernet-phy-ieee802.3-c22";
125 rxc-skew-ps = <1500>;
126 reg = <0>;
127 interrupt-parent = <&gpio4>;
128 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
129 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
130 };
131 };
132
133 &i2c0 {
134 pinctrl-0 = <&i2c0_pins>;
135 pinctrl-names = "default";
136
137 status = "okay";
138 clock-frequency = <400000>;
139
140 hdmi@39 {
141 compatible = "adi,adv7511w";
142 #sound-dai-cells = <0>;
143 reg = <0x39>;
144 interrupt-parent = <&gpio1>;
145 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
146 avdd-supply = <&vcc1v8_d4>;
147 dvdd-supply = <&vcc1v8_d4>;
148 pvdd-supply = <&vcc1v8_d4>;
149 bgvdd-supply = <&vcc1v8_d4>;
150 dvdd-3v-supply = <&vcc3v3_d5>;
151
152 adi,input-depth = <8>;
153 adi,input-colorspace = "rgb";
154 adi,input-clock = "1x";
155
156 ports {
157 #address-cells = <1>;
158 #size-cells = <0>;
159
160 port@0 {
161 reg = <0>;
162 adv7511_in: endpoint {
163 remote-endpoint = <&thc63lvd1024_out>;
164 };
165 };
166
167 port@1 {
168 reg = <1>;
169 adv7511_out: endpoint {
170 remote-endpoint = <&hdmi_con>;
171 };
172 };
173 };
174 };
175 };
176
177 &lvds0 {
178 status = "okay";
179
180 ports {
181 port@1 {
182 lvds0_out: endpoint {
183 remote-endpoint = <&thc63lvd1024_in>;
184 };
185 };
186 };
187 };
188
189 &pfc {
190 gether_pins: gether {
191 groups = "gether_mdio_a", "gether_rgmii",
192 "gether_txcrefclk", "gether_txcrefclk_mega";
193 function = "gether";
194 };
195
196 i2c0_pins: i2c0 {
197 groups = "i2c0";
198 function = "i2c0";
199 };
200
201 qspi0_pins: qspi0 {
202 groups = "qspi0_ctrl", "qspi0_data4";
203 function = "qspi0";
204 };
205
206 scif0_pins: scif0 {
207 groups = "scif0_data";
208 function = "scif0";
209 };
210
211 scif_clk_pins: scif_clk {
212 groups = "scif_clk_b";
213 function = "scif_clk";
214 };
215 };
216
217 &rpc {
218 pinctrl-0 = <&qspi0_pins>;
219 pinctrl-names = "default";
220
221 status = "okay";
222
223 flash@0 {
224 compatible = "spansion,s25fs512s", "jedec,spi-nor";
225 reg = <0>;
226 spi-max-frequency = <50000000>;
227 spi-rx-bus-width = <4>;
228
229 partitions {
230 compatible = "fixed-partitions";
231 #address-cells = <1>;
232 #size-cells = <1>;
233
234 bootparam@0 {
235 reg = <0x00000000 0x040000>;
236 read-only;
237 };
238 cr7@40000 {
239 reg = <0x00040000 0x080000>;
240 read-only;
241 };
242 cert_header_sa3@c0000 {
243 reg = <0x000c0000 0x080000>;
244 read-only;
245 };
246 bl2@140000 {
247 reg = <0x00140000 0x040000>;
248 read-only;
249 };
250 cert_header_sa6@180000 {
251 reg = <0x00180000 0x040000>;
252 read-only;
253 };
254 bl31@1c0000 {
255 reg = <0x001c0000 0x460000>;
256 read-only;
257 };
258 uboot@640000 {
259 reg = <0x00640000 0x0c0000>;
260 read-only;
261 };
262 uboot-env@700000 {
263 reg = <0x00700000 0x040000>;
264 read-only;
265 };
266 dtb@740000 {
267 reg = <0x00740000 0x080000>;
268 };
269 kernel@7c0000 {
270 reg = <0x007c0000 0x1400000>;
271 };
272 user@1bc0000 {
273 reg = <0x01bc0000 0x2440000>;
274 };
275 };
276 };
277 };
278
279 &rwdt {
280 timeout-sec = <60>;
281 status = "okay";
282 };
283
284 &scif0 {
285 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
286 pinctrl-names = "default";
287
288 status = "okay";
289 };
290
291 &scif_clk {
292 clock-frequency = <14745600>;
293 };
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