1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the R-Car V3H (R8A77980) SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/r8a77980-sysc.h>
13
14 / {
15 compatible = "renesas,r8a77980";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 /* External CAN clock - to be overridden by boards that provide it */
20 can_clk: can {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <0>;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 a53_0: cpu@0 {
31 device_type = "cpu";
32 compatible = "arm,cortex-a53";
33 reg = <0>;
34 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
35 power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
36 next-level-cache = <&L2_CA53>;
37 enable-method = "psci";
38 };
39
40 a53_1: cpu@1 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a53";
43 reg = <1>;
44 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
45 power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
46 next-level-cache = <&L2_CA53>;
47 enable-method = "psci";
48 };
49
50 a53_2: cpu@2 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a53";
53 reg = <2>;
54 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
55 power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
56 next-level-cache = <&L2_CA53>;
57 enable-method = "psci";
58 };
59
60 a53_3: cpu@3 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a53";
63 reg = <3>;
64 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
65 power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
66 next-level-cache = <&L2_CA53>;
67 enable-method = "psci";
68 };
69
70 L2_CA53: cache-controller {
71 compatible = "cache";
72 power-domains = <&sysc R8A77980_PD_CA53_SCU>;
73 cache-unified;
74 cache-level = <2>;
75 };
76 };
77
78 extal_clk: extal {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 /* This value must be overridden by the board */
82 clock-frequency = <0>;
83 };
84
85 extalr_clk: extalr {
86 compatible = "fixed-clock";
87 #clock-cells = <0>;
88 /* This value must be overridden by the board */
89 clock-frequency = <0>;
90 };
91
92 /* External PCIe clock - can be overridden by the board */
93 pcie_bus_clk: pcie_bus {
94 compatible = "fixed-clock";
95 #clock-cells = <0>;
96 clock-frequency = <0>;
97 };
98
99 pmu_a53 {
100 compatible = "arm,cortex-a53-pmu";
101 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
102 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
103 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
104 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
105 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
106 };
107
108 psci {
109 compatible = "arm,psci-1.0", "arm,psci-0.2";
110 method = "smc";
111 };
112
113 /* External SCIF clock - to be overridden by boards that provide it */
114 scif_clk: scif {
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
117 clock-frequency = <0>;
118 };
119
120 soc {
121 compatible = "simple-bus";
122 interrupt-parent = <&gic>;
123
124 #address-cells = <2>;
125 #size-cells = <2>;
126 ranges;
127
128 rwdt: watchdog@e6020000 {
129 compatible = "renesas,r8a77980-wdt",
130 "renesas,rcar-gen3-wdt";
131 reg = <0 0xe6020000 0 0x0c>;
132 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&cpg CPG_MOD 402>;
134 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
135 resets = <&cpg 402>;
136 status = "disabled";
137 };
138
139 gpio0: gpio@e6050000 {
140 compatible = "renesas,gpio-r8a77980",
141 "renesas,rcar-gen3-gpio";
142 reg = <0 0xe6050000 0 0x50>;
143 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
144 #gpio-cells = <2>;
145 gpio-controller;
146 gpio-ranges = <&pfc 0 0 22>;
147 #interrupt-cells = <2>;
148 interrupt-controller;
149 clocks = <&cpg CPG_MOD 912>;
150 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
151 resets = <&cpg 912>;
152 };
153
154 gpio1: gpio@e6051000 {
155 compatible = "renesas,gpio-r8a77980",
156 "renesas,rcar-gen3-gpio";
157 reg = <0 0xe6051000 0 0x50>;
158 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
159 #gpio-cells = <2>;
160 gpio-controller;
161 gpio-ranges = <&pfc 0 32 28>;
162 #interrupt-cells = <2>;
163 interrupt-controller;
164 clocks = <&cpg CPG_MOD 911>;
165 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
166 resets = <&cpg 911>;
167 };
168
169 gpio2: gpio@e6052000 {
170 compatible = "renesas,gpio-r8a77980",
171 "renesas,rcar-gen3-gpio";
172 reg = <0 0xe6052000 0 0x50>;
173 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
174 #gpio-cells = <2>;
175 gpio-controller;
176 gpio-ranges = <&pfc 0 64 30>;
177 #interrupt-cells = <2>;
178 interrupt-controller;
179 clocks = <&cpg CPG_MOD 910>;
180 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
181 resets = <&cpg 910>;
182 };
183
184 gpio3: gpio@e6053000 {
185 compatible = "renesas,gpio-r8a77980",
186 "renesas,rcar-gen3-gpio";
187 reg = <0 0xe6053000 0 0x50>;
188 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
189 #gpio-cells = <2>;
190 gpio-controller;
191 gpio-ranges = <&pfc 0 96 17>;
192 #interrupt-cells = <2>;
193 interrupt-controller;
194 clocks = <&cpg CPG_MOD 909>;
195 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
196 resets = <&cpg 909>;
197 };
198
199 gpio4: gpio@e6054000 {
200 compatible = "renesas,gpio-r8a77980",
201 "renesas,rcar-gen3-gpio";
202 reg = <0 0xe6054000 0 0x50>;
203 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
204 #gpio-cells = <2>;
205 gpio-controller;
206 gpio-ranges = <&pfc 0 128 25>;
207 #interrupt-cells = <2>;
208 interrupt-controller;
209 clocks = <&cpg CPG_MOD 908>;
210 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
211 resets = <&cpg 908>;
212 };
213
214 gpio5: gpio@e6055000 {
215 compatible = "renesas,gpio-r8a77980",
216 "renesas,rcar-gen3-gpio";
217 reg = <0 0xe6055000 0 0x50>;
218 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
219 #gpio-cells = <2>;
220 gpio-controller;
221 gpio-ranges = <&pfc 0 160 15>;
222 #interrupt-cells = <2>;
223 interrupt-controller;
224 clocks = <&cpg CPG_MOD 907>;
225 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
226 resets = <&cpg 907>;
227 };
228
229 pfc: pinctrl@e6060000 {
230 compatible = "renesas,pfc-r8a77980";
231 reg = <0 0xe6060000 0 0x50c>;
232 };
233
234 cmt0: timer@e60f0000 {
235 compatible = "renesas,r8a77980-cmt0",
236 "renesas,rcar-gen3-cmt0";
237 reg = <0 0xe60f0000 0 0x1004>;
238 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&cpg CPG_MOD 303>;
241 clock-names = "fck";
242 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
243 resets = <&cpg 303>;
244 status = "disabled";
245 };
246
247 cmt1: timer@e6130000 {
248 compatible = "renesas,r8a77980-cmt1",
249 "renesas,rcar-gen3-cmt1";
250 reg = <0 0xe6130000 0 0x1004>;
251 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&cpg CPG_MOD 302>;
260 clock-names = "fck";
261 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
262 resets = <&cpg 302>;
263 status = "disabled";
264 };
265
266 cmt2: timer@e6140000 {
267 compatible = "renesas,r8a77980-cmt1",
268 "renesas,rcar-gen3-cmt1";
269 reg = <0 0xe6140000 0 0x1004>;
270 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&cpg CPG_MOD 301>;
279 clock-names = "fck";
280 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
281 resets = <&cpg 301>;
282 status = "disabled";
283 };
284
285 cmt3: timer@e6148000 {
286 compatible = "renesas,r8a77980-cmt1",
287 "renesas,rcar-gen3-cmt1";
288 reg = <0 0xe6148000 0 0x1004>;
289 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&cpg CPG_MOD 300>;
298 clock-names = "fck";
299 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
300 resets = <&cpg 300>;
301 status = "disabled";
302 };
303
304 cpg: clock-controller@e6150000 {
305 compatible = "renesas,r8a77980-cpg-mssr";
306 reg = <0 0xe6150000 0 0x1000>;
307 clocks = <&extal_clk>, <&extalr_clk>;
308 clock-names = "extal", "extalr";
309 #clock-cells = <2>;
310 #power-domain-cells = <0>;
311 #reset-cells = <1>;
312 };
313
314 rst: reset-controller@e6160000 {
315 compatible = "renesas,r8a77980-rst";
316 reg = <0 0xe6160000 0 0x200>;
317 };
318
319 sysc: system-controller@e6180000 {
320 compatible = "renesas,r8a77980-sysc";
321 reg = <0 0xe6180000 0 0x440>;
322 #power-domain-cells = <1>;
323 };
324
325 tsc: thermal@e6198000 {
326 compatible = "renesas,r8a77980-thermal";
327 reg = <0 0xe6198000 0 0x100>,
328 <0 0xe61a0000 0 0x100>;
329 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&cpg CPG_MOD 522>;
333 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
334 resets = <&cpg 522>;
335 #thermal-sensor-cells = <1>;
336 };
337
338 intc_ex: interrupt-controller@e61c0000 {
339 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
340 #interrupt-cells = <2>;
341 interrupt-controller;
342 reg = <0 0xe61c0000 0 0x200>;
343 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&cpg CPG_MOD 407>;
350 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
351 resets = <&cpg 407>;
352 };
353
354 tmu0: timer@e61e0000 {
355 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
356 reg = <0 0xe61e0000 0 0x30>;
357 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-names = "tuni0", "tuni1", "tuni2";
361 clocks = <&cpg CPG_MOD 125>;
362 clock-names = "fck";
363 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
364 resets = <&cpg 125>;
365 status = "disabled";
366 };
367
368 tmu1: timer@e6fc0000 {
369 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
370 reg = <0 0xe6fc0000 0 0x30>;
371 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
376 clocks = <&cpg CPG_MOD 124>;
377 clock-names = "fck";
378 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
379 resets = <&cpg 124>;
380 status = "disabled";
381 };
382
383 tmu2: timer@e6fd0000 {
384 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
385 reg = <0 0xe6fd0000 0 0x30>;
386 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
391 clocks = <&cpg CPG_MOD 123>;
392 clock-names = "fck";
393 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
394 resets = <&cpg 123>;
395 status = "disabled";
396 };
397
398 tmu3: timer@e6fe0000 {
399 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
400 reg = <0 0xe6fe0000 0 0x30>;
401 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
405 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
406 clocks = <&cpg CPG_MOD 122>;
407 clock-names = "fck";
408 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
409 resets = <&cpg 122>;
410 status = "disabled";
411 };
412
413 tmu4: timer@ffc00000 {
414 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
415 reg = <0 0xffc00000 0 0x30>;
416 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
420 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
421 clocks = <&cpg CPG_MOD 121>;
422 clock-names = "fck";
423 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
424 resets = <&cpg 121>;
425 status = "disabled";
426 };
427
428 i2c0: i2c@e6500000 {
429 compatible = "renesas,i2c-r8a77980",
430 "renesas,rcar-gen3-i2c";
431 reg = <0 0xe6500000 0 0x40>;
432 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cpg CPG_MOD 931>;
434 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
435 resets = <&cpg 931>;
436 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
437 <&dmac2 0x91>, <&dmac2 0x90>;
438 dma-names = "tx", "rx", "tx", "rx";
439 i2c-scl-internal-delay-ns = <6>;
440 #address-cells = <1>;
441 #size-cells = <0>;
442 status = "disabled";
443 };
444
445 i2c1: i2c@e6508000 {
446 compatible = "renesas,i2c-r8a77980",
447 "renesas,rcar-gen3-i2c";
448 reg = <0 0xe6508000 0 0x40>;
449 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&cpg CPG_MOD 930>;
451 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
452 resets = <&cpg 930>;
453 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
454 <&dmac2 0x93>, <&dmac2 0x92>;
455 dma-names = "tx", "rx", "tx", "rx";
456 i2c-scl-internal-delay-ns = <6>;
457 #address-cells = <1>;
458 #size-cells = <0>;
459 status = "disabled";
460 };
461
462 i2c2: i2c@e6510000 {
463 compatible = "renesas,i2c-r8a77980",
464 "renesas,rcar-gen3-i2c";
465 reg = <0 0xe6510000 0 0x40>;
466 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&cpg CPG_MOD 929>;
468 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
469 resets = <&cpg 929>;
470 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
471 <&dmac2 0x95>, <&dmac2 0x94>;
472 dma-names = "tx", "rx", "tx", "rx";
473 i2c-scl-internal-delay-ns = <6>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 status = "disabled";
477 };
478
479 i2c3: i2c@e66d0000 {
480 compatible = "renesas,i2c-r8a77980",
481 "renesas,rcar-gen3-i2c";
482 reg = <0 0xe66d0000 0 0x40>;
483 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&cpg CPG_MOD 928>;
485 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
486 resets = <&cpg 928>;
487 i2c-scl-internal-delay-ns = <6>;
488 #address-cells = <1>;
489 #size-cells = <0>;
490 status = "disabled";
491 };
492
493 i2c4: i2c@e66d8000 {
494 compatible = "renesas,i2c-r8a77980",
495 "renesas,rcar-gen3-i2c";
496 reg = <0 0xe66d8000 0 0x40>;
497 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cpg CPG_MOD 927>;
499 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
500 resets = <&cpg 927>;
501 i2c-scl-internal-delay-ns = <6>;
502 #address-cells = <1>;
503 #size-cells = <0>;
504 status = "disabled";
505 };
506
507 i2c5: i2c@e66e0000 {
508 compatible = "renesas,i2c-r8a77980",
509 "renesas,rcar-gen3-i2c";
510 reg = <0 0xe66e0000 0 0x40>;
511 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&cpg CPG_MOD 919>;
513 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
514 resets = <&cpg 919>;
515 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
516 <&dmac2 0x9b>, <&dmac2 0x9a>;
517 dma-names = "tx", "rx", "tx", "rx";
518 i2c-scl-internal-delay-ns = <6>;
519 #address-cells = <1>;
520 #size-cells = <0>;
521 status = "disabled";
522 };
523
524 hscif0: serial@e6540000 {
525 compatible = "renesas,hscif-r8a77980",
526 "renesas,rcar-gen3-hscif",
527 "renesas,hscif";
528 reg = <0 0xe6540000 0 0x60>;
529 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&cpg CPG_MOD 520>,
531 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
532 <&scif_clk>;
533 clock-names = "fck", "brg_int", "scif_clk";
534 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
535 <&dmac2 0x31>, <&dmac2 0x30>;
536 dma-names = "tx", "rx", "tx", "rx";
537 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
538 resets = <&cpg 520>;
539 status = "disabled";
540 };
541
542 hscif1: serial@e6550000 {
543 compatible = "renesas,hscif-r8a77980",
544 "renesas,rcar-gen3-hscif",
545 "renesas,hscif";
546 reg = <0 0xe6550000 0 0x60>;
547 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cpg CPG_MOD 519>,
549 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
550 <&scif_clk>;
551 clock-names = "fck", "brg_int", "scif_clk";
552 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
553 <&dmac2 0x33>, <&dmac2 0x32>;
554 dma-names = "tx", "rx", "tx", "rx";
555 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
556 resets = <&cpg 519>;
557 status = "disabled";
558 };
559
560 hscif2: serial@e6560000 {
561 compatible = "renesas,hscif-r8a77980",
562 "renesas,rcar-gen3-hscif",
563 "renesas,hscif";
564 reg = <0 0xe6560000 0 0x60>;
565 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&cpg CPG_MOD 518>,
567 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
568 <&scif_clk>;
569 clock-names = "fck", "brg_int", "scif_clk";
570 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
571 <&dmac2 0x35>, <&dmac2 0x34>;
572 dma-names = "tx", "rx", "tx", "rx";
573 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
574 resets = <&cpg 518>;
575 status = "disabled";
576 };
577
578 hscif3: serial@e66a0000 {
579 compatible = "renesas,hscif-r8a77980",
580 "renesas,rcar-gen3-hscif",
581 "renesas,hscif";
582 reg = <0 0xe66a0000 0 0x60>;
583 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&cpg CPG_MOD 517>,
585 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
586 <&scif_clk>;
587 clock-names = "fck", "brg_int", "scif_clk";
588 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
589 <&dmac2 0x37>, <&dmac2 0x36>;
590 dma-names = "tx", "rx", "tx", "rx";
591 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
592 resets = <&cpg 517>;
593 status = "disabled";
594 };
595
596 pcie_phy: pcie-phy@e65d0000 {
597 compatible = "renesas,r8a77980-pcie-phy";
598 reg = <0 0xe65d0000 0 0x8000>;
599 #phy-cells = <0>;
600 clocks = <&cpg CPG_MOD 319>;
601 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
602 resets = <&cpg 319>;
603 status = "disabled";
604 };
605
606 canfd: can@e66c0000 {
607 compatible = "renesas,r8a77980-canfd",
608 "renesas,rcar-gen3-canfd";
609 reg = <0 0xe66c0000 0 0x8000>;
610 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
612 interrupt-names = "ch_int", "g_int";
613 clocks = <&cpg CPG_MOD 914>,
614 <&cpg CPG_CORE R8A77980_CLK_CANFD>,
615 <&can_clk>;
616 clock-names = "fck", "canfd", "can_clk";
617 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
618 assigned-clock-rates = <40000000>;
619 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
620 resets = <&cpg 914>;
621 status = "disabled";
622
623 channel0 {
624 status = "disabled";
625 };
626
627 channel1 {
628 status = "disabled";
629 };
630 };
631
632 avb: ethernet@e6800000 {
633 compatible = "renesas,etheravb-r8a77980",
634 "renesas,etheravb-rcar-gen3";
635 reg = <0 0xe6800000 0 0x800>;
636 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
661 interrupt-names = "ch0", "ch1", "ch2", "ch3",
662 "ch4", "ch5", "ch6", "ch7",
663 "ch8", "ch9", "ch10", "ch11",
664 "ch12", "ch13", "ch14", "ch15",
665 "ch16", "ch17", "ch18", "ch19",
666 "ch20", "ch21", "ch22", "ch23",
667 "ch24";
668 clocks = <&cpg CPG_MOD 812>;
669 clock-names = "fck";
670 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
671 resets = <&cpg 812>;
672 phy-mode = "rgmii";
673 rx-internal-delay-ps = <0>;
674 tx-internal-delay-ps = <2000>;
675 iommus = <&ipmmu_ds1 33>;
676 #address-cells = <1>;
677 #size-cells = <0>;
678 status = "disabled";
679 };
680
681 pwm0: pwm@e6e30000 {
682 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
683 reg = <0 0xe6e30000 0 0x10>;
684 #pwm-cells = <2>;
685 clocks = <&cpg CPG_MOD 523>;
686 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
687 resets = <&cpg 523>;
688 status = "disabled";
689 };
690
691 pwm1: pwm@e6e31000 {
692 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
693 reg = <0 0xe6e31000 0 0x10>;
694 #pwm-cells = <2>;
695 clocks = <&cpg CPG_MOD 523>;
696 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
697 resets = <&cpg 523>;
698 status = "disabled";
699 };
700
701 pwm2: pwm@e6e32000 {
702 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
703 reg = <0 0xe6e32000 0 0x10>;
704 #pwm-cells = <2>;
705 clocks = <&cpg CPG_MOD 523>;
706 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
707 resets = <&cpg 523>;
708 status = "disabled";
709 };
710
711 pwm3: pwm@e6e33000 {
712 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
713 reg = <0 0xe6e33000 0 0x10>;
714 #pwm-cells = <2>;
715 clocks = <&cpg CPG_MOD 523>;
716 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
717 resets = <&cpg 523>;
718 status = "disabled";
719 };
720
721 pwm4: pwm@e6e34000 {
722 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
723 reg = <0 0xe6e34000 0 0x10>;
724 #pwm-cells = <2>;
725 clocks = <&cpg CPG_MOD 523>;
726 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
727 resets = <&cpg 523>;
728 status = "disabled";
729 };
730
731 scif0: serial@e6e60000 {
732 compatible = "renesas,scif-r8a77980",
733 "renesas,rcar-gen3-scif",
734 "renesas,scif";
735 reg = <0 0xe6e60000 0 0x40>;
736 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 207>,
738 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
739 <&scif_clk>;
740 clock-names = "fck", "brg_int", "scif_clk";
741 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
742 <&dmac2 0x51>, <&dmac2 0x50>;
743 dma-names = "tx", "rx", "tx", "rx";
744 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
745 resets = <&cpg 207>;
746 status = "disabled";
747 };
748
749 scif1: serial@e6e68000 {
750 compatible = "renesas,scif-r8a77980",
751 "renesas,rcar-gen3-scif",
752 "renesas,scif";
753 reg = <0 0xe6e68000 0 0x40>;
754 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&cpg CPG_MOD 206>,
756 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
757 <&scif_clk>;
758 clock-names = "fck", "brg_int", "scif_clk";
759 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
760 <&dmac2 0x53>, <&dmac2 0x52>;
761 dma-names = "tx", "rx", "tx", "rx";
762 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
763 resets = <&cpg 206>;
764 status = "disabled";
765 };
766
767 scif3: serial@e6c50000 {
768 compatible = "renesas,scif-r8a77980",
769 "renesas,rcar-gen3-scif",
770 "renesas,scif";
771 reg = <0 0xe6c50000 0 0x40>;
772 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&cpg CPG_MOD 204>,
774 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
775 <&scif_clk>;
776 clock-names = "fck", "brg_int", "scif_clk";
777 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
778 <&dmac2 0x57>, <&dmac2 0x56>;
779 dma-names = "tx", "rx", "tx", "rx";
780 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
781 resets = <&cpg 204>;
782 status = "disabled";
783 };
784
785 scif4: serial@e6c40000 {
786 compatible = "renesas,scif-r8a77980",
787 "renesas,rcar-gen3-scif",
788 "renesas,scif";
789 reg = <0 0xe6c40000 0 0x40>;
790 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&cpg CPG_MOD 203>,
792 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
793 <&scif_clk>;
794 clock-names = "fck", "brg_int", "scif_clk";
795 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
796 <&dmac2 0x59>, <&dmac2 0x58>;
797 dma-names = "tx", "rx", "tx", "rx";
798 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
799 resets = <&cpg 203>;
800 status = "disabled";
801 };
802
803 tpu: pwm@e6e80000 {
804 compatible = "renesas,tpu-r8a77980", "renesas,tpu";
805 reg = <0 0xe6e80000 0 0x148>;
806 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&cpg CPG_MOD 304>;
808 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
809 resets = <&cpg 304>;
810 #pwm-cells = <3>;
811 status = "disabled";
812 };
813
814 msiof0: spi@e6e90000 {
815 compatible = "renesas,msiof-r8a77980",
816 "renesas,rcar-gen3-msiof";
817 reg = <0 0xe6e90000 0 0x64>;
818 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&cpg CPG_MOD 211>;
820 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
821 resets = <&cpg 211>;
822 #address-cells = <1>;
823 #size-cells = <0>;
824 status = "disabled";
825 };
826
827 msiof1: spi@e6ea0000 {
828 compatible = "renesas,msiof-r8a77980",
829 "renesas,rcar-gen3-msiof";
830 reg = <0 0xe6ea0000 0 0x0064>;
831 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&cpg CPG_MOD 210>;
833 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
834 resets = <&cpg 210>;
835 #address-cells = <1>;
836 #size-cells = <0>;
837 status = "disabled";
838 };
839
840 msiof2: spi@e6c00000 {
841 compatible = "renesas,msiof-r8a77980",
842 "renesas,rcar-gen3-msiof";
843 reg = <0 0xe6c00000 0 0x0064>;
844 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&cpg CPG_MOD 209>;
846 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
847 resets = <&cpg 209>;
848 #address-cells = <1>;
849 #size-cells = <0>;
850 status = "disabled";
851 };
852
853 msiof3: spi@e6c10000 {
854 compatible = "renesas,msiof-r8a77980",
855 "renesas,rcar-gen3-msiof";
856 reg = <0 0xe6c10000 0 0x0064>;
857 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&cpg CPG_MOD 208>;
859 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
860 resets = <&cpg 208>;
861 #address-cells = <1>;
862 #size-cells = <0>;
863 status = "disabled";
864 };
865
866 vin0: video@e6ef0000 {
867 compatible = "renesas,vin-r8a77980";
868 reg = <0 0xe6ef0000 0 0x1000>;
869 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&cpg CPG_MOD 811>;
871 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
872 resets = <&cpg 811>;
873 renesas,id = <0>;
874 status = "disabled";
875
876 ports {
877 #address-cells = <1>;
878 #size-cells = <0>;
879
880 port@1 {
881 #address-cells = <1>;
882 #size-cells = <0>;
883
884 reg = <1>;
885
886 vin0csi40: endpoint@2 {
887 reg = <2>;
888 remote-endpoint = <&csi40vin0>;
889 };
890 };
891 };
892 };
893
894 vin1: video@e6ef1000 {
895 compatible = "renesas,vin-r8a77980";
896 reg = <0 0xe6ef1000 0 0x1000>;
897 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&cpg CPG_MOD 810>;
899 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
900 status = "disabled";
901 renesas,id = <1>;
902 resets = <&cpg 810>;
903
904 ports {
905 #address-cells = <1>;
906 #size-cells = <0>;
907
908 port@1 {
909 #address-cells = <1>;
910 #size-cells = <0>;
911
912 reg = <1>;
913
914 vin1csi40: endpoint@2 {
915 reg = <2>;
916 remote-endpoint = <&csi40vin1>;
917 };
918 };
919 };
920 };
921
922 vin2: video@e6ef2000 {
923 compatible = "renesas,vin-r8a77980";
924 reg = <0 0xe6ef2000 0 0x1000>;
925 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&cpg CPG_MOD 809>;
927 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
928 resets = <&cpg 809>;
929 renesas,id = <2>;
930 status = "disabled";
931
932 ports {
933 #address-cells = <1>;
934 #size-cells = <0>;
935
936 port@1 {
937 #address-cells = <1>;
938 #size-cells = <0>;
939
940 reg = <1>;
941
942 vin2csi40: endpoint@2 {
943 reg = <2>;
944 remote-endpoint = <&csi40vin2>;
945 };
946 };
947 };
948 };
949
950 vin3: video@e6ef3000 {
951 compatible = "renesas,vin-r8a77980";
952 reg = <0 0xe6ef3000 0 0x1000>;
953 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
954 clocks = <&cpg CPG_MOD 808>;
955 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
956 resets = <&cpg 808>;
957 renesas,id = <3>;
958 status = "disabled";
959
960 ports {
961 #address-cells = <1>;
962 #size-cells = <0>;
963
964 port@1 {
965 #address-cells = <1>;
966 #size-cells = <0>;
967
968 reg = <1>;
969
970 vin3csi40: endpoint@2 {
971 reg = <2>;
972 remote-endpoint = <&csi40vin3>;
973 };
974 };
975 };
976 };
977
978 vin4: video@e6ef4000 {
979 compatible = "renesas,vin-r8a77980";
980 reg = <0 0xe6ef4000 0 0x1000>;
981 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&cpg CPG_MOD 807>;
983 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
984 resets = <&cpg 807>;
985 renesas,id = <4>;
986 status = "disabled";
987
988 ports {
989 #address-cells = <1>;
990 #size-cells = <0>;
991
992 port@1 {
993 #address-cells = <1>;
994 #size-cells = <0>;
995
996 reg = <1>;
997
998 vin4csi41: endpoint@3 {
999 reg = <3>;
1000 remote-endpoint = <&csi41vin4>;
1001 };
1002 };
1003 };
1004 };
1005
1006 vin5: video@e6ef5000 {
1007 compatible = "renesas,vin-r8a77980";
1008 reg = <0 0xe6ef5000 0 0x1000>;
1009 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cpg CPG_MOD 806>;
1011 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1012 resets = <&cpg 806>;
1013 renesas,id = <5>;
1014 status = "disabled";
1015
1016 ports {
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1019
1020 port@1 {
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023
1024 reg = <1>;
1025
1026 vin5csi41: endpoint@3 {
1027 reg = <3>;
1028 remote-endpoint = <&csi41vin5>;
1029 };
1030 };
1031 };
1032 };
1033
1034 vin6: video@e6ef6000 {
1035 compatible = "renesas,vin-r8a77980";
1036 reg = <0 0xe6ef6000 0 0x1000>;
1037 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&cpg CPG_MOD 805>;
1039 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1040 resets = <&cpg 805>;
1041 renesas,id = <6>;
1042 status = "disabled";
1043
1044 ports {
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1047
1048 port@1 {
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1051
1052 reg = <1>;
1053
1054 vin6csi41: endpoint@3 {
1055 reg = <3>;
1056 remote-endpoint = <&csi41vin6>;
1057 };
1058 };
1059 };
1060 };
1061
1062 vin7: video@e6ef7000 {
1063 compatible = "renesas,vin-r8a77980";
1064 reg = <0 0xe6ef7000 0 0x1000>;
1065 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&cpg CPG_MOD 804>;
1067 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1068 resets = <&cpg 804>;
1069 renesas,id = <7>;
1070 status = "disabled";
1071
1072 ports {
1073 #address-cells = <1>;
1074 #size-cells = <0>;
1075
1076 port@1 {
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1079
1080 reg = <1>;
1081
1082 vin7csi41: endpoint@3 {
1083 reg = <3>;
1084 remote-endpoint = <&csi41vin7>;
1085 };
1086 };
1087 };
1088 };
1089
1090 vin8: video@e6ef8000 {
1091 compatible = "renesas,vin-r8a77980";
1092 reg = <0 0xe6ef8000 0 0x1000>;
1093 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1094 clocks = <&cpg CPG_MOD 628>;
1095 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1096 resets = <&cpg 628>;
1097 renesas,id = <8>;
1098 status = "disabled";
1099 };
1100
1101 vin9: video@e6ef9000 {
1102 compatible = "renesas,vin-r8a77980";
1103 reg = <0 0xe6ef9000 0 0x1000>;
1104 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1105 clocks = <&cpg CPG_MOD 627>;
1106 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1107 resets = <&cpg 627>;
1108 renesas,id = <9>;
1109 status = "disabled";
1110 };
1111
1112 vin10: video@e6efa000 {
1113 compatible = "renesas,vin-r8a77980";
1114 reg = <0 0xe6efa000 0 0x1000>;
1115 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&cpg CPG_MOD 625>;
1117 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1118 resets = <&cpg 625>;
1119 renesas,id = <10>;
1120 status = "disabled";
1121 };
1122
1123 vin11: video@e6efb000 {
1124 compatible = "renesas,vin-r8a77980";
1125 reg = <0 0xe6efb000 0 0x1000>;
1126 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1127 clocks = <&cpg CPG_MOD 618>;
1128 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1129 resets = <&cpg 618>;
1130 renesas,id = <11>;
1131 status = "disabled";
1132 };
1133
1134 vin12: video@e6efc000 {
1135 compatible = "renesas,vin-r8a77980";
1136 reg = <0 0xe6efc000 0 0x1000>;
1137 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1138 clocks = <&cpg CPG_MOD 612>;
1139 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1140 resets = <&cpg 612>;
1141 renesas,id = <12>;
1142 status = "disabled";
1143 };
1144
1145 vin13: video@e6efd000 {
1146 compatible = "renesas,vin-r8a77980";
1147 reg = <0 0xe6efd000 0 0x1000>;
1148 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1149 clocks = <&cpg CPG_MOD 608>;
1150 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1151 resets = <&cpg 608>;
1152 renesas,id = <13>;
1153 status = "disabled";
1154 };
1155
1156 vin14: video@e6efe000 {
1157 compatible = "renesas,vin-r8a77980";
1158 reg = <0 0xe6efe000 0 0x1000>;
1159 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&cpg CPG_MOD 605>;
1161 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1162 resets = <&cpg 605>;
1163 renesas,id = <14>;
1164 status = "disabled";
1165 };
1166
1167 vin15: video@e6eff000 {
1168 compatible = "renesas,vin-r8a77980";
1169 reg = <0 0xe6eff000 0 0x1000>;
1170 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
1171 clocks = <&cpg CPG_MOD 604>;
1172 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1173 resets = <&cpg 604>;
1174 renesas,id = <15>;
1175 status = "disabled";
1176 };
1177
1178 dmac1: dma-controller@e7300000 {
1179 compatible = "renesas,dmac-r8a77980",
1180 "renesas,rcar-dmac";
1181 reg = <0 0xe7300000 0 0x10000>;
1182 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1183 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1184 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
1191 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
1192 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
1193 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
1194 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
1195 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
1196 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
1197 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
1198 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1199 interrupt-names = "error",
1200 "ch0", "ch1", "ch2", "ch3",
1201 "ch4", "ch5", "ch6", "ch7",
1202 "ch8", "ch9", "ch10", "ch11",
1203 "ch12", "ch13", "ch14", "ch15";
1204 clocks = <&cpg CPG_MOD 218>;
1205 clock-names = "fck";
1206 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1207 resets = <&cpg 218>;
1208 #dma-cells = <1>;
1209 dma-channels = <16>;
1210 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1211 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1212 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1213 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1214 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1215 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1216 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1217 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1218 };
1219
1220 dmac2: dma-controller@e7310000 {
1221 compatible = "renesas,dmac-r8a77980",
1222 "renesas,rcar-dmac";
1223 reg = <0 0xe7310000 0 0x10000>;
1224 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1241 interrupt-names = "error",
1242 "ch0", "ch1", "ch2", "ch3",
1243 "ch4", "ch5", "ch6", "ch7",
1244 "ch8", "ch9", "ch10", "ch11",
1245 "ch12", "ch13", "ch14", "ch15";
1246 clocks = <&cpg CPG_MOD 217>;
1247 clock-names = "fck";
1248 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1249 resets = <&cpg 217>;
1250 #dma-cells = <1>;
1251 dma-channels = <16>;
1252 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1253 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1254 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1255 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1256 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1257 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1258 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1259 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1260 };
1261
1262 gether: ethernet@e7400000 {
1263 compatible = "renesas,gether-r8a77980";
1264 reg = <0 0xe7400000 0 0x1000>;
1265 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1266 clocks = <&cpg CPG_MOD 813>;
1267 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1268 resets = <&cpg 813>;
1269 #address-cells = <1>;
1270 #size-cells = <0>;
1271 status = "disabled";
1272 };
1273
1274 ipmmu_ds1: iommu@e7740000 {
1275 compatible = "renesas,ipmmu-r8a77980";
1276 reg = <0 0xe7740000 0 0x1000>;
1277 renesas,ipmmu-main = <&ipmmu_mm 0>;
1278 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1279 #iommu-cells = <1>;
1280 };
1281
1282 ipmmu_ir: iommu@ff8b0000 {
1283 compatible = "renesas,ipmmu-r8a77980";
1284 reg = <0 0xff8b0000 0 0x1000>;
1285 renesas,ipmmu-main = <&ipmmu_mm 3>;
1286 power-domains = <&sysc R8A77980_PD_A3IR>;
1287 #iommu-cells = <1>;
1288 };
1289
1290 ipmmu_mm: iommu@e67b0000 {
1291 compatible = "renesas,ipmmu-r8a77980";
1292 reg = <0 0xe67b0000 0 0x1000>;
1293 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1294 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1295 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1296 #iommu-cells = <1>;
1297 };
1298
1299 ipmmu_rt: iommu@ffc80000 {
1300 compatible = "renesas,ipmmu-r8a77980";
1301 reg = <0 0xffc80000 0 0x1000>;
1302 renesas,ipmmu-main = <&ipmmu_mm 10>;
1303 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1304 #iommu-cells = <1>;
1305 };
1306
1307 ipmmu_vc0: iommu@fe990000 {
1308 compatible = "renesas,ipmmu-r8a77980";
1309 reg = <0 0xfe990000 0 0x1000>;
1310 renesas,ipmmu-main = <&ipmmu_mm 12>;
1311 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1312 #iommu-cells = <1>;
1313 };
1314
1315 ipmmu_vi0: iommu@febd0000 {
1316 compatible = "renesas,ipmmu-r8a77980";
1317 reg = <0 0xfebd0000 0 0x1000>;
1318 renesas,ipmmu-main = <&ipmmu_mm 14>;
1319 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1320 #iommu-cells = <1>;
1321 };
1322
1323 ipmmu_vip0: iommu@e7b00000 {
1324 compatible = "renesas,ipmmu-r8a77980";
1325 reg = <0 0xe7b00000 0 0x1000>;
1326 renesas,ipmmu-main = <&ipmmu_mm 4>;
1327 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1328 #iommu-cells = <1>;
1329 };
1330
1331 ipmmu_vip1: iommu@e7960000 {
1332 compatible = "renesas,ipmmu-r8a77980";
1333 reg = <0 0xe7960000 0 0x1000>;
1334 renesas,ipmmu-main = <&ipmmu_mm 11>;
1335 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1336 #iommu-cells = <1>;
1337 };
1338
1339 mmc0: mmc@ee140000 {
1340 compatible = "renesas,sdhi-r8a77980",
1341 "renesas,rcar-gen3-sdhi";
1342 reg = <0 0xee140000 0 0x2000>;
1343 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1344 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>;
1345 clock-names = "core", "clkh";
1346 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1347 resets = <&cpg 314>;
1348 max-frequency = <200000000>;
1349 iommus = <&ipmmu_ds1 32>;
1350 status = "disabled";
1351 };
1352
1353 rpc: spi@ee200000 {
1354 compatible = "renesas,r8a77980-rpc-if",
1355 "renesas,rcar-gen3-rpc-if";
1356 reg = <0 0xee200000 0 0x200>,
1357 <0 0x08000000 0 0x4000000>,
1358 <0 0xee208000 0 0x100>;
1359 reg-names = "regs", "dirmap", "wbuf";
1360 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1361 clocks = <&cpg CPG_MOD 917>;
1362 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1363 resets = <&cpg 917>;
1364 #address-cells = <1>;
1365 #size-cells = <0>;
1366 status = "disabled";
1367 };
1368
1369 gic: interrupt-controller@f1010000 {
1370 compatible = "arm,gic-400";
1371 #interrupt-cells = <3>;
1372 #address-cells = <0>;
1373 interrupt-controller;
1374 reg = <0x0 0xf1010000 0 0x1000>,
1375 <0x0 0xf1020000 0 0x20000>,
1376 <0x0 0xf1040000 0 0x20000>,
1377 <0x0 0xf1060000 0 0x20000>;
1378 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
1379 IRQ_TYPE_LEVEL_HIGH)>;
1380 clocks = <&cpg CPG_MOD 408>;
1381 clock-names = "clk";
1382 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1383 resets = <&cpg 408>;
1384 };
1385
1386 pciec: pcie@fe000000 {
1387 compatible = "renesas,pcie-r8a77980",
1388 "renesas,pcie-rcar-gen3";
1389 reg = <0 0xfe000000 0 0x80000>;
1390 #address-cells = <3>;
1391 #size-cells = <2>;
1392 bus-range = <0x00 0xff>;
1393 device_type = "pci";
1394 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>,
1395 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>,
1396 <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
1397 <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>;
1398 /* Map all possible DDR/IOMMU as inbound ranges */
1399 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1400 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1402 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1403 #interrupt-cells = <1>;
1404 interrupt-map-mask = <0 0 0 0>;
1405 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1406 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1407 clock-names = "pcie", "pcie_bus";
1408 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1409 resets = <&cpg 319>;
1410 phys = <&pcie_phy>;
1411 phy-names = "pcie";
1412 iommu-map = <0 &ipmmu_vi0 5 1>;
1413 iommu-map-mask = <0>;
1414 status = "disabled";
1415 };
1416
1417 vspd0: vsp@fea20000 {
1418 compatible = "renesas,vsp2";
1419 reg = <0 0xfea20000 0 0x5000>;
1420 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1421 clocks = <&cpg CPG_MOD 623>;
1422 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1423 resets = <&cpg 623>;
1424 renesas,fcp = <&fcpvd0>;
1425 };
1426
1427 fcpvd0: fcp@fea27000 {
1428 compatible = "renesas,fcpv";
1429 reg = <0 0xfea27000 0 0x200>;
1430 clocks = <&cpg CPG_MOD 603>;
1431 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1432 resets = <&cpg 603>;
1433 };
1434
1435 csi40: csi2@feaa0000 {
1436 compatible = "renesas,r8a77980-csi2";
1437 reg = <0 0xfeaa0000 0 0x10000>;
1438 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1439 clocks = <&cpg CPG_MOD 716>;
1440 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1441 resets = <&cpg 716>;
1442 status = "disabled";
1443
1444 ports {
1445 #address-cells = <1>;
1446 #size-cells = <0>;
1447
1448 port@0 {
1449 reg = <0>;
1450 };
1451
1452 port@1 {
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1455
1456 reg = <1>;
1457
1458 csi40vin0: endpoint@0 {
1459 reg = <0>;
1460 remote-endpoint = <&vin0csi40>;
1461 };
1462 csi40vin1: endpoint@1 {
1463 reg = <1>;
1464 remote-endpoint = <&vin1csi40>;
1465 };
1466 csi40vin2: endpoint@2 {
1467 reg = <2>;
1468 remote-endpoint = <&vin2csi40>;
1469 };
1470 csi40vin3: endpoint@3 {
1471 reg = <3>;
1472 remote-endpoint = <&vin3csi40>;
1473 };
1474 };
1475 };
1476 };
1477
1478 csi41: csi2@feab0000 {
1479 compatible = "renesas,r8a77980-csi2";
1480 reg = <0 0xfeab0000 0 0x10000>;
1481 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1482 clocks = <&cpg CPG_MOD 715>;
1483 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1484 resets = <&cpg 715>;
1485 status = "disabled";
1486
1487 ports {
1488 #address-cells = <1>;
1489 #size-cells = <0>;
1490
1491 port@0 {
1492 reg = <0>;
1493 };
1494
1495 port@1 {
1496 #address-cells = <1>;
1497 #size-cells = <0>;
1498
1499 reg = <1>;
1500
1501 csi41vin4: endpoint@0 {
1502 reg = <0>;
1503 remote-endpoint = <&vin4csi41>;
1504 };
1505 csi41vin5: endpoint@1 {
1506 reg = <1>;
1507 remote-endpoint = <&vin5csi41>;
1508 };
1509 csi41vin6: endpoint@2 {
1510 reg = <2>;
1511 remote-endpoint = <&vin6csi41>;
1512 };
1513 csi41vin7: endpoint@3 {
1514 reg = <3>;
1515 remote-endpoint = <&vin7csi41>;
1516 };
1517 };
1518 };
1519 };
1520
1521 du: display@feb00000 {
1522 compatible = "renesas,du-r8a77980";
1523 reg = <0 0xfeb00000 0 0x80000>;
1524 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1525 clocks = <&cpg CPG_MOD 724>;
1526 clock-names = "du.0";
1527 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1528 resets = <&cpg 724>;
1529 reset-names = "du.0";
1530 renesas,vsps = <&vspd0 0>;
1531
1532 status = "disabled";
1533
1534 ports {
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1537
1538 port@0 {
1539 reg = <0>;
1540 };
1541
1542 port@1 {
1543 reg = <1>;
1544 du_out_lvds0: endpoint {
1545 remote-endpoint = <&lvds0_in>;
1546 };
1547 };
1548 };
1549 };
1550
1551 lvds0: lvds-encoder@feb90000 {
1552 compatible = "renesas,r8a77980-lvds";
1553 reg = <0 0xfeb90000 0 0x14>;
1554 clocks = <&cpg CPG_MOD 727>;
1555 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1556 resets = <&cpg 727>;
1557 status = "disabled";
1558
1559 ports {
1560 #address-cells = <1>;
1561 #size-cells = <0>;
1562
1563 port@0 {
1564 reg = <0>;
1565 lvds0_in: endpoint {
1566 remote-endpoint =
1567 <&du_out_lvds0>;
1568 };
1569 };
1570
1571 port@1 {
1572 reg = <1>;
1573 };
1574 };
1575 };
1576
1577 prr: chipid@fff00044 {
1578 compatible = "renesas,prr";
1579 reg = <0 0xfff00044 0 4>;
1580 };
1581 };
1582
1583 thermal-zones {
1584 sensor1_thermal: sensor1-thermal {
1585 polling-delay-passive = <250>;
1586 polling-delay = <1000>;
1587 thermal-sensors = <&tsc 0>;
1588
1589 trips {
1590 sensor1-passive {
1591 temperature = <95000>;
1592 hysteresis = <1000>;
1593 type = "passive";
1594 };
1595 sensor1-critical {
1596 temperature = <120000>;
1597 hysteresis = <1000>;
1598 type = "critical";
1599 };
1600 };
1601 };
1602
1603 sensor2_thermal: sensor2-thermal {
1604 polling-delay-passive = <250>;
1605 polling-delay = <1000>;
1606 thermal-sensors = <&tsc 1>;
1607
1608 trips {
1609 sensor2-passive {
1610 temperature = <95000>;
1611 hysteresis = <1000>;
1612 type = "passive";
1613 };
1614 sensor2-critical {
1615 temperature = <120000>;
1616 hysteresis = <1000>;
1617 type = "critical";
1618 };
1619 };
1620 };
1621 };
1622
1623 timer {
1624 compatible = "arm,armv8-timer";
1625 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
1626 IRQ_TYPE_LEVEL_LOW)>,
1627 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
1628 IRQ_TYPE_LEVEL_LOW)>,
1629 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
1630 IRQ_TYPE_LEVEL_LOW)>,
1631 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
1632 IRQ_TYPE_LEVEL_LOW)>;
1633 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
1634 };
1635 };
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