1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
4 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba
7 */
8
9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a77995-sysc.h>
12
13 / {
14 compatible = "renesas,r8a77995";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 /*
19 * The external audio clocks are configured as 0 Hz fixed frequency
20 * clocks by default.
21 * Boards that provide audio clocks should override them.
22 */
23 audio_clk_a: audio_clk_a {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
27 };
28
29 audio_clk_b: audio_clk_b {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
33 };
34
35 /* External CAN clock - to be overridden by boards that provide it */
36 can_clk: can {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <0>;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 a53_0: cpu@0 {
47 compatible = "arm,cortex-a53";
48 reg = <0x0>;
49 device_type = "cpu";
50 power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
51 next-level-cache = <&L2_CA53>;
52 enable-method = "psci";
53 };
54
55 L2_CA53: cache-controller-1 {
56 compatible = "cache";
57 power-domains = <&sysc R8A77995_PD_CA53_SCU>;
58 cache-unified;
59 cache-level = <2>;
60 };
61 };
62
63 extal_clk: extal {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 /* This value must be overridden by the board */
67 clock-frequency = <0>;
68 };
69
70 pmu_a53 {
71 compatible = "arm,cortex-a53-pmu";
72 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
73 };
74
75 psci {
76 compatible = "arm,psci-1.0", "arm,psci-0.2";
77 method = "smc";
78 };
79
80 scif_clk: scif {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <0>;
84 };
85
86 soc {
87 compatible = "simple-bus";
88 interrupt-parent = <&gic>;
89 #address-cells = <2>;
90 #size-cells = <2>;
91 ranges;
92
93 rwdt: watchdog@e6020000 {
94 compatible = "renesas,r8a77995-wdt",
95 "renesas,rcar-gen3-wdt";
96 reg = <0 0xe6020000 0 0x0c>;
97 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&cpg CPG_MOD 402>;
99 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
100 resets = <&cpg 402>;
101 status = "disabled";
102 };
103
104 gpio0: gpio@e6050000 {
105 compatible = "renesas,gpio-r8a77995",
106 "renesas,rcar-gen3-gpio";
107 reg = <0 0xe6050000 0 0x50>;
108 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
109 #gpio-cells = <2>;
110 gpio-controller;
111 gpio-ranges = <&pfc 0 0 9>;
112 #interrupt-cells = <2>;
113 interrupt-controller;
114 clocks = <&cpg CPG_MOD 912>;
115 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
116 resets = <&cpg 912>;
117 };
118
119 gpio1: gpio@e6051000 {
120 compatible = "renesas,gpio-r8a77995",
121 "renesas,rcar-gen3-gpio";
122 reg = <0 0xe6051000 0 0x50>;
123 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
124 #gpio-cells = <2>;
125 gpio-controller;
126 gpio-ranges = <&pfc 0 32 32>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
129 clocks = <&cpg CPG_MOD 911>;
130 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
131 resets = <&cpg 911>;
132 };
133
134 gpio2: gpio@e6052000 {
135 compatible = "renesas,gpio-r8a77995",
136 "renesas,rcar-gen3-gpio";
137 reg = <0 0xe6052000 0 0x50>;
138 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
139 #gpio-cells = <2>;
140 gpio-controller;
141 gpio-ranges = <&pfc 0 64 32>;
142 #interrupt-cells = <2>;
143 interrupt-controller;
144 clocks = <&cpg CPG_MOD 910>;
145 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
146 resets = <&cpg 910>;
147 };
148
149 gpio3: gpio@e6053000 {
150 compatible = "renesas,gpio-r8a77995",
151 "renesas,rcar-gen3-gpio";
152 reg = <0 0xe6053000 0 0x50>;
153 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
154 #gpio-cells = <2>;
155 gpio-controller;
156 gpio-ranges = <&pfc 0 96 10>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
159 clocks = <&cpg CPG_MOD 909>;
160 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
161 resets = <&cpg 909>;
162 };
163
164 gpio4: gpio@e6054000 {
165 compatible = "renesas,gpio-r8a77995",
166 "renesas,rcar-gen3-gpio";
167 reg = <0 0xe6054000 0 0x50>;
168 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
169 #gpio-cells = <2>;
170 gpio-controller;
171 gpio-ranges = <&pfc 0 128 32>;
172 #interrupt-cells = <2>;
173 interrupt-controller;
174 clocks = <&cpg CPG_MOD 908>;
175 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
176 resets = <&cpg 908>;
177 };
178
179 gpio5: gpio@e6055000 {
180 compatible = "renesas,gpio-r8a77995",
181 "renesas,rcar-gen3-gpio";
182 reg = <0 0xe6055000 0 0x50>;
183 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
184 #gpio-cells = <2>;
185 gpio-controller;
186 gpio-ranges = <&pfc 0 160 21>;
187 #interrupt-cells = <2>;
188 interrupt-controller;
189 clocks = <&cpg CPG_MOD 907>;
190 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
191 resets = <&cpg 907>;
192 };
193
194 gpio6: gpio@e6055400 {
195 compatible = "renesas,gpio-r8a77995",
196 "renesas,rcar-gen3-gpio";
197 reg = <0 0xe6055400 0 0x50>;
198 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
199 #gpio-cells = <2>;
200 gpio-controller;
201 gpio-ranges = <&pfc 0 192 14>;
202 #interrupt-cells = <2>;
203 interrupt-controller;
204 clocks = <&cpg CPG_MOD 906>;
205 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
206 resets = <&cpg 906>;
207 };
208
209 pfc: pinctrl@e6060000 {
210 compatible = "renesas,pfc-r8a77995";
211 reg = <0 0xe6060000 0 0x508>;
212 };
213
214 cmt0: timer@e60f0000 {
215 compatible = "renesas,r8a77995-cmt0",
216 "renesas,rcar-gen3-cmt0";
217 reg = <0 0xe60f0000 0 0x1004>;
218 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&cpg CPG_MOD 303>;
221 clock-names = "fck";
222 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
223 resets = <&cpg 303>;
224 status = "disabled";
225 };
226
227 cmt1: timer@e6130000 {
228 compatible = "renesas,r8a77995-cmt1",
229 "renesas,rcar-gen3-cmt1";
230 reg = <0 0xe6130000 0 0x1004>;
231 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&cpg CPG_MOD 302>;
240 clock-names = "fck";
241 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
242 resets = <&cpg 302>;
243 status = "disabled";
244 };
245
246 cmt2: timer@e6140000 {
247 compatible = "renesas,r8a77995-cmt1",
248 "renesas,rcar-gen3-cmt1";
249 reg = <0 0xe6140000 0 0x1004>;
250 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cpg CPG_MOD 301>;
259 clock-names = "fck";
260 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
261 resets = <&cpg 301>;
262 status = "disabled";
263 };
264
265 cmt3: timer@e6148000 {
266 compatible = "renesas,r8a77995-cmt1",
267 "renesas,rcar-gen3-cmt1";
268 reg = <0 0xe6148000 0 0x1004>;
269 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&cpg CPG_MOD 300>;
278 clock-names = "fck";
279 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
280 resets = <&cpg 300>;
281 status = "disabled";
282 };
283
284 cpg: clock-controller@e6150000 {
285 compatible = "renesas,r8a77995-cpg-mssr";
286 reg = <0 0xe6150000 0 0x1000>;
287 clocks = <&extal_clk>;
288 clock-names = "extal";
289 #clock-cells = <2>;
290 #power-domain-cells = <0>;
291 #reset-cells = <1>;
292 };
293
294 rst: reset-controller@e6160000 {
295 compatible = "renesas,r8a77995-rst";
296 reg = <0 0xe6160000 0 0x0200>;
297 };
298
299 sysc: system-controller@e6180000 {
300 compatible = "renesas,r8a77995-sysc";
301 reg = <0 0xe6180000 0 0x0400>;
302 #power-domain-cells = <1>;
303 };
304
305 thermal: thermal@e6190000 {
306 compatible = "renesas,thermal-r8a77995";
307 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
308 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&cpg CPG_MOD 522>;
312 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
313 resets = <&cpg 522>;
314 #thermal-sensor-cells = <0>;
315 };
316
317 intc_ex: interrupt-controller@e61c0000 {
318 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
319 #interrupt-cells = <2>;
320 interrupt-controller;
321 reg = <0 0xe61c0000 0 0x200>;
322 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&cpg CPG_MOD 407>;
329 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
330 resets = <&cpg 407>;
331 };
332
333 tmu0: timer@e61e0000 {
334 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
335 reg = <0 0xe61e0000 0 0x30>;
336 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
339 interrupt-names = "tuni0", "tuni1", "tuni2";
340 clocks = <&cpg CPG_MOD 125>;
341 clock-names = "fck";
342 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
343 resets = <&cpg 125>;
344 status = "disabled";
345 };
346
347 tmu1: timer@e6fc0000 {
348 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
349 reg = <0 0xe6fc0000 0 0x30>;
350 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
354 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
355 clocks = <&cpg CPG_MOD 124>;
356 clock-names = "fck";
357 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
358 resets = <&cpg 124>;
359 status = "disabled";
360 };
361
362 tmu2: timer@e6fd0000 {
363 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
364 reg = <0 0xe6fd0000 0 0x30>;
365 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
369 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
370 clocks = <&cpg CPG_MOD 123>;
371 clock-names = "fck";
372 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
373 resets = <&cpg 123>;
374 status = "disabled";
375 };
376
377 tmu3: timer@e6fe0000 {
378 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
379 reg = <0 0xe6fe0000 0 0x30>;
380 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
383 interrupt-names = "tuni0", "tuni1", "tuni2";
384 clocks = <&cpg CPG_MOD 122>;
385 clock-names = "fck";
386 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
387 resets = <&cpg 122>;
388 status = "disabled";
389 };
390
391 tmu4: timer@ffc00000 {
392 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
393 reg = <0 0xffc00000 0 0x30>;
394 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
397 interrupt-names = "tuni0", "tuni1", "tuni2";
398 clocks = <&cpg CPG_MOD 121>;
399 clock-names = "fck";
400 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
401 resets = <&cpg 121>;
402 status = "disabled";
403 };
404
405 i2c0: i2c@e6500000 {
406 #address-cells = <1>;
407 #size-cells = <0>;
408 compatible = "renesas,i2c-r8a77995",
409 "renesas,rcar-gen3-i2c";
410 reg = <0 0xe6500000 0 0x40>;
411 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&cpg CPG_MOD 931>;
413 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
414 resets = <&cpg 931>;
415 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
416 <&dmac2 0x91>, <&dmac2 0x90>;
417 dma-names = "tx", "rx", "tx", "rx";
418 i2c-scl-internal-delay-ns = <6>;
419 status = "disabled";
420 };
421
422 i2c1: i2c@e6508000 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 compatible = "renesas,i2c-r8a77995",
426 "renesas,rcar-gen3-i2c";
427 reg = <0 0xe6508000 0 0x40>;
428 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cpg CPG_MOD 930>;
430 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
431 resets = <&cpg 930>;
432 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
433 <&dmac2 0x93>, <&dmac2 0x92>;
434 dma-names = "tx", "rx", "tx", "rx";
435 i2c-scl-internal-delay-ns = <6>;
436 status = "disabled";
437 };
438
439 i2c2: i2c@e6510000 {
440 #address-cells = <1>;
441 #size-cells = <0>;
442 compatible = "renesas,i2c-r8a77995",
443 "renesas,rcar-gen3-i2c";
444 reg = <0 0xe6510000 0 0x40>;
445 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&cpg CPG_MOD 929>;
447 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
448 resets = <&cpg 929>;
449 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
450 <&dmac2 0x95>, <&dmac2 0x94>;
451 dma-names = "tx", "rx", "tx", "rx";
452 i2c-scl-internal-delay-ns = <6>;
453 status = "disabled";
454 };
455
456 i2c3: i2c@e66d0000 {
457 #address-cells = <1>;
458 #size-cells = <0>;
459 compatible = "renesas,i2c-r8a77995",
460 "renesas,rcar-gen3-i2c";
461 reg = <0 0xe66d0000 0 0x40>;
462 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&cpg CPG_MOD 928>;
464 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
465 resets = <&cpg 928>;
466 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
467 dma-names = "tx", "rx";
468 i2c-scl-internal-delay-ns = <6>;
469 status = "disabled";
470 };
471
472 hscif0: serial@e6540000 {
473 compatible = "renesas,hscif-r8a77995",
474 "renesas,rcar-gen3-hscif",
475 "renesas,hscif";
476 reg = <0 0xe6540000 0 0x60>;
477 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&cpg CPG_MOD 520>,
479 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
480 <&scif_clk>;
481 clock-names = "fck", "brg_int", "scif_clk";
482 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
483 <&dmac2 0x31>, <&dmac2 0x30>;
484 dma-names = "tx", "rx", "tx", "rx";
485 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
486 resets = <&cpg 520>;
487 status = "disabled";
488 };
489
490 hscif3: serial@e66a0000 {
491 compatible = "renesas,hscif-r8a77995",
492 "renesas,rcar-gen3-hscif",
493 "renesas,hscif";
494 reg = <0 0xe66a0000 0 0x60>;
495 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&cpg CPG_MOD 517>,
497 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
498 <&scif_clk>;
499 clock-names = "fck", "brg_int", "scif_clk";
500 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
501 dma-names = "tx", "rx";
502 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
503 resets = <&cpg 517>;
504 status = "disabled";
505 };
506
507 hsusb: usb@e6590000 {
508 compatible = "renesas,usbhs-r8a77995",
509 "renesas,rcar-gen3-usbhs";
510 reg = <0 0xe6590000 0 0x200>;
511 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
513 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
514 <&usb_dmac1 0>, <&usb_dmac1 1>;
515 dma-names = "ch0", "ch1", "ch2", "ch3";
516 renesas,buswait = <11>;
517 phys = <&usb2_phy0 3>;
518 phy-names = "usb";
519 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
520 resets = <&cpg 704>, <&cpg 703>;
521 status = "disabled";
522 };
523
524 usb_dmac0: dma-controller@e65a0000 {
525 compatible = "renesas,r8a77995-usb-dmac",
526 "renesas,usb-dmac";
527 reg = <0 0xe65a0000 0 0x100>;
528 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
530 interrupt-names = "ch0", "ch1";
531 clocks = <&cpg CPG_MOD 330>;
532 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
533 resets = <&cpg 330>;
534 #dma-cells = <1>;
535 dma-channels = <2>;
536 };
537
538 usb_dmac1: dma-controller@e65b0000 {
539 compatible = "renesas,r8a77995-usb-dmac",
540 "renesas,usb-dmac";
541 reg = <0 0xe65b0000 0 0x100>;
542 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
544 interrupt-names = "ch0", "ch1";
545 clocks = <&cpg CPG_MOD 331>;
546 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
547 resets = <&cpg 331>;
548 #dma-cells = <1>;
549 dma-channels = <2>;
550 };
551
552 arm_cc630p: crypto@e6601000 {
553 compatible = "arm,cryptocell-630p-ree";
554 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
555 reg = <0x0 0xe6601000 0 0x1000>;
556 clocks = <&cpg CPG_MOD 229>;
557 resets = <&cpg 229>;
558 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
559 };
560
561 canfd: can@e66c0000 {
562 compatible = "renesas,r8a77995-canfd",
563 "renesas,rcar-gen3-canfd";
564 reg = <0 0xe66c0000 0 0x8000>;
565 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
567 interrupt-names = "ch_int", "g_int";
568 clocks = <&cpg CPG_MOD 914>,
569 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
570 <&can_clk>;
571 clock-names = "fck", "canfd", "can_clk";
572 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
573 assigned-clock-rates = <40000000>;
574 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
575 resets = <&cpg 914>;
576 status = "disabled";
577
578 channel0 {
579 status = "disabled";
580 };
581
582 channel1 {
583 status = "disabled";
584 };
585 };
586
587 dmac0: dma-controller@e6700000 {
588 compatible = "renesas,dmac-r8a77995",
589 "renesas,rcar-dmac";
590 reg = <0 0xe6700000 0 0x10000>;
591 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
600 interrupt-names = "error",
601 "ch0", "ch1", "ch2", "ch3",
602 "ch4", "ch5", "ch6", "ch7";
603 clocks = <&cpg CPG_MOD 219>;
604 clock-names = "fck";
605 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
606 resets = <&cpg 219>;
607 #dma-cells = <1>;
608 dma-channels = <8>;
609 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
610 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
611 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
612 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>;
613 };
614
615 dmac1: dma-controller@e7300000 {
616 compatible = "renesas,dmac-r8a77995",
617 "renesas,rcar-dmac";
618 reg = <0 0xe7300000 0 0x10000>;
619 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
628 interrupt-names = "error",
629 "ch0", "ch1", "ch2", "ch3",
630 "ch4", "ch5", "ch6", "ch7";
631 clocks = <&cpg CPG_MOD 218>;
632 clock-names = "fck";
633 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
634 resets = <&cpg 218>;
635 #dma-cells = <1>;
636 dma-channels = <8>;
637 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
638 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
639 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
640 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
641 };
642
643 dmac2: dma-controller@e7310000 {
644 compatible = "renesas,dmac-r8a77995",
645 "renesas,rcar-dmac";
646 reg = <0 0xe7310000 0 0x10000>;
647 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
656 interrupt-names = "error",
657 "ch0", "ch1", "ch2", "ch3",
658 "ch4", "ch5", "ch6", "ch7";
659 clocks = <&cpg CPG_MOD 217>;
660 clock-names = "fck";
661 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
662 resets = <&cpg 217>;
663 #dma-cells = <1>;
664 dma-channels = <8>;
665 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
666 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
667 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
668 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
669 };
670
671 ipmmu_ds0: iommu@e6740000 {
672 compatible = "renesas,ipmmu-r8a77995";
673 reg = <0 0xe6740000 0 0x1000>;
674 renesas,ipmmu-main = <&ipmmu_mm 0>;
675 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
676 #iommu-cells = <1>;
677 };
678
679 ipmmu_ds1: iommu@e7740000 {
680 compatible = "renesas,ipmmu-r8a77995";
681 reg = <0 0xe7740000 0 0x1000>;
682 renesas,ipmmu-main = <&ipmmu_mm 1>;
683 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
684 #iommu-cells = <1>;
685 };
686
687 ipmmu_hc: iommu@e6570000 {
688 compatible = "renesas,ipmmu-r8a77995";
689 reg = <0 0xe6570000 0 0x1000>;
690 renesas,ipmmu-main = <&ipmmu_mm 2>;
691 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
692 #iommu-cells = <1>;
693 };
694
695 ipmmu_mm: iommu@e67b0000 {
696 compatible = "renesas,ipmmu-r8a77995";
697 reg = <0 0xe67b0000 0 0x1000>;
698 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
700 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
701 #iommu-cells = <1>;
702 };
703
704 ipmmu_mp: iommu@ec670000 {
705 compatible = "renesas,ipmmu-r8a77995";
706 reg = <0 0xec670000 0 0x1000>;
707 renesas,ipmmu-main = <&ipmmu_mm 4>;
708 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
709 #iommu-cells = <1>;
710 };
711
712 ipmmu_pv0: iommu@fd800000 {
713 compatible = "renesas,ipmmu-r8a77995";
714 reg = <0 0xfd800000 0 0x1000>;
715 renesas,ipmmu-main = <&ipmmu_mm 6>;
716 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
717 #iommu-cells = <1>;
718 };
719
720 ipmmu_rt: iommu@ffc80000 {
721 compatible = "renesas,ipmmu-r8a77995";
722 reg = <0 0xffc80000 0 0x1000>;
723 renesas,ipmmu-main = <&ipmmu_mm 10>;
724 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
725 #iommu-cells = <1>;
726 };
727
728 ipmmu_vc0: iommu@fe6b0000 {
729 compatible = "renesas,ipmmu-r8a77995";
730 reg = <0 0xfe6b0000 0 0x1000>;
731 renesas,ipmmu-main = <&ipmmu_mm 12>;
732 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
733 #iommu-cells = <1>;
734 };
735
736 ipmmu_vi0: iommu@febd0000 {
737 compatible = "renesas,ipmmu-r8a77995";
738 reg = <0 0xfebd0000 0 0x1000>;
739 renesas,ipmmu-main = <&ipmmu_mm 14>;
740 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
741 #iommu-cells = <1>;
742 };
743
744 ipmmu_vp0: iommu@fe990000 {
745 compatible = "renesas,ipmmu-r8a77995";
746 reg = <0 0xfe990000 0 0x1000>;
747 renesas,ipmmu-main = <&ipmmu_mm 16>;
748 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
749 #iommu-cells = <1>;
750 };
751
752 avb: ethernet@e6800000 {
753 compatible = "renesas,etheravb-r8a77995",
754 "renesas,etheravb-rcar-gen3";
755 reg = <0 0xe6800000 0 0x800>;
756 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
776 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
781 interrupt-names = "ch0", "ch1", "ch2", "ch3",
782 "ch4", "ch5", "ch6", "ch7",
783 "ch8", "ch9", "ch10", "ch11",
784 "ch12", "ch13", "ch14", "ch15",
785 "ch16", "ch17", "ch18", "ch19",
786 "ch20", "ch21", "ch22", "ch23",
787 "ch24";
788 clocks = <&cpg CPG_MOD 812>;
789 clock-names = "fck";
790 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
791 resets = <&cpg 812>;
792 phy-mode = "rgmii";
793 rx-internal-delay-ps = <1800>;
794 iommus = <&ipmmu_ds0 16>;
795 #address-cells = <1>;
796 #size-cells = <0>;
797 status = "disabled";
798 };
799
800 can0: can@e6c30000 {
801 compatible = "renesas,can-r8a77995",
802 "renesas,rcar-gen3-can";
803 reg = <0 0xe6c30000 0 0x1000>;
804 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&cpg CPG_MOD 916>,
806 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
807 <&can_clk>;
808 clock-names = "clkp1", "clkp2", "can_clk";
809 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
810 assigned-clock-rates = <40000000>;
811 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
812 resets = <&cpg 916>;
813 status = "disabled";
814 };
815
816 can1: can@e6c38000 {
817 compatible = "renesas,can-r8a77995",
818 "renesas,rcar-gen3-can";
819 reg = <0 0xe6c38000 0 0x1000>;
820 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&cpg CPG_MOD 915>,
822 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
823 <&can_clk>;
824 clock-names = "clkp1", "clkp2", "can_clk";
825 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
826 assigned-clock-rates = <40000000>;
827 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
828 resets = <&cpg 915>;
829 status = "disabled";
830 };
831
832 pwm0: pwm@e6e30000 {
833 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
834 reg = <0 0xe6e30000 0 0x8>;
835 #pwm-cells = <2>;
836 clocks = <&cpg CPG_MOD 523>;
837 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
838 resets = <&cpg 523>;
839 status = "disabled";
840 };
841
842 pwm1: pwm@e6e31000 {
843 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
844 reg = <0 0xe6e31000 0 0x8>;
845 #pwm-cells = <2>;
846 clocks = <&cpg CPG_MOD 523>;
847 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
848 resets = <&cpg 523>;
849 status = "disabled";
850 };
851
852 pwm2: pwm@e6e32000 {
853 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
854 reg = <0 0xe6e32000 0 0x8>;
855 #pwm-cells = <2>;
856 clocks = <&cpg CPG_MOD 523>;
857 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
858 resets = <&cpg 523>;
859 status = "disabled";
860 };
861
862 pwm3: pwm@e6e33000 {
863 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
864 reg = <0 0xe6e33000 0 0x8>;
865 #pwm-cells = <2>;
866 clocks = <&cpg CPG_MOD 523>;
867 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
868 resets = <&cpg 523>;
869 status = "disabled";
870 };
871
872 scif0: serial@e6e60000 {
873 compatible = "renesas,scif-r8a77995",
874 "renesas,rcar-gen3-scif", "renesas,scif";
875 reg = <0 0xe6e60000 0 64>;
876 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
877 clocks = <&cpg CPG_MOD 207>,
878 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
879 <&scif_clk>;
880 clock-names = "fck", "brg_int", "scif_clk";
881 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
882 <&dmac2 0x51>, <&dmac2 0x50>;
883 dma-names = "tx", "rx", "tx", "rx";
884 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
885 resets = <&cpg 207>;
886 status = "disabled";
887 };
888
889 scif1: serial@e6e68000 {
890 compatible = "renesas,scif-r8a77995",
891 "renesas,rcar-gen3-scif", "renesas,scif";
892 reg = <0 0xe6e68000 0 64>;
893 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&cpg CPG_MOD 206>,
895 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
896 <&scif_clk>;
897 clock-names = "fck", "brg_int", "scif_clk";
898 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
899 <&dmac2 0x53>, <&dmac2 0x52>;
900 dma-names = "tx", "rx", "tx", "rx";
901 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
902 resets = <&cpg 206>;
903 status = "disabled";
904 };
905
906 scif2: serial@e6e88000 {
907 compatible = "renesas,scif-r8a77995",
908 "renesas,rcar-gen3-scif", "renesas,scif";
909 reg = <0 0xe6e88000 0 64>;
910 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&cpg CPG_MOD 310>,
912 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
913 <&scif_clk>;
914 clock-names = "fck", "brg_int", "scif_clk";
915 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
916 <&dmac2 0x13>, <&dmac2 0x12>;
917 dma-names = "tx", "rx", "tx", "rx";
918 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
919 resets = <&cpg 310>;
920 status = "disabled";
921 };
922
923 scif3: serial@e6c50000 {
924 compatible = "renesas,scif-r8a77995",
925 "renesas,rcar-gen3-scif", "renesas,scif";
926 reg = <0 0xe6c50000 0 64>;
927 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&cpg CPG_MOD 204>,
929 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
930 <&scif_clk>;
931 clock-names = "fck", "brg_int", "scif_clk";
932 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
933 dma-names = "tx", "rx";
934 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
935 resets = <&cpg 204>;
936 status = "disabled";
937 };
938
939 scif4: serial@e6c40000 {
940 compatible = "renesas,scif-r8a77995",
941 "renesas,rcar-gen3-scif", "renesas,scif";
942 reg = <0 0xe6c40000 0 64>;
943 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&cpg CPG_MOD 203>,
945 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
946 <&scif_clk>;
947 clock-names = "fck", "brg_int", "scif_clk";
948 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
949 dma-names = "tx", "rx";
950 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
951 resets = <&cpg 203>;
952 status = "disabled";
953 };
954
955 scif5: serial@e6f30000 {
956 compatible = "renesas,scif-r8a77995",
957 "renesas,rcar-gen3-scif", "renesas,scif";
958 reg = <0 0xe6f30000 0 64>;
959 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&cpg CPG_MOD 202>,
961 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
962 <&scif_clk>;
963 clock-names = "fck", "brg_int", "scif_clk";
964 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
965 <&dmac2 0x5b>, <&dmac2 0x5a>;
966 dma-names = "tx", "rx", "tx", "rx";
967 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
968 resets = <&cpg 202>;
969 status = "disabled";
970 };
971
972 msiof0: spi@e6e90000 {
973 compatible = "renesas,msiof-r8a77995",
974 "renesas,rcar-gen3-msiof";
975 reg = <0 0xe6e90000 0 0x64>;
976 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
977 clocks = <&cpg CPG_MOD 211>;
978 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
979 <&dmac2 0x41>, <&dmac2 0x40>;
980 dma-names = "tx", "rx", "tx", "rx";
981 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
982 resets = <&cpg 211>;
983 #address-cells = <1>;
984 #size-cells = <0>;
985 status = "disabled";
986 };
987
988 msiof1: spi@e6ea0000 {
989 compatible = "renesas,msiof-r8a77995",
990 "renesas,rcar-gen3-msiof";
991 reg = <0 0xe6ea0000 0 0x64>;
992 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&cpg CPG_MOD 210>;
994 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
995 <&dmac2 0x43>, <&dmac2 0x42>;
996 dma-names = "tx", "rx", "tx", "rx";
997 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
998 resets = <&cpg 210>;
999 #address-cells = <1>;
1000 #size-cells = <0>;
1001 status = "disabled";
1002 };
1003
1004 msiof2: spi@e6c00000 {
1005 compatible = "renesas,msiof-r8a77995",
1006 "renesas,rcar-gen3-msiof";
1007 reg = <0 0xe6c00000 0 0x64>;
1008 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&cpg CPG_MOD 209>;
1010 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1011 dma-names = "tx", "rx";
1012 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1013 resets = <&cpg 209>;
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1016 status = "disabled";
1017 };
1018
1019 msiof3: spi@e6c10000 {
1020 compatible = "renesas,msiof-r8a77995",
1021 "renesas,rcar-gen3-msiof";
1022 reg = <0 0xe6c10000 0 0x64>;
1023 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&cpg CPG_MOD 208>;
1025 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1026 dma-names = "tx", "rx";
1027 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1028 resets = <&cpg 208>;
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1031 status = "disabled";
1032 };
1033
1034 vin4: video@e6ef4000 {
1035 compatible = "renesas,vin-r8a77995";
1036 reg = <0 0xe6ef4000 0 0x1000>;
1037 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&cpg CPG_MOD 807>;
1039 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1040 resets = <&cpg 807>;
1041 renesas,id = <4>;
1042 status = "disabled";
1043 };
1044
1045 rcar_sound: sound@ec500000 {
1046 /*
1047 * #sound-dai-cells is required if simple-card
1048 *
1049 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1050 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1051 */
1052 /*
1053 * #clock-cells is required for audio_clkout0/1/2/3
1054 *
1055 * clkout : #clock-cells = <0>; <&rcar_sound>;
1056 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1057 */
1058 compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3";
1059 reg = <0 0xec500000 0 0x1000>, /* SCU */
1060 <0 0xec5a0000 0 0x100>, /* ADG */
1061 <0 0xec540000 0 0x1000>, /* SSIU */
1062 <0 0xec541000 0 0x280>, /* SSI */
1063 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1064 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1065
1066 clocks = <&cpg CPG_MOD 1005>,
1067 <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
1068 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
1069 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1070 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1071 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1072 <&audio_clk_a>, <&audio_clk_b>,
1073 <&cpg CPG_MOD 922>;
1074 clock-names = "ssi-all",
1075 "ssi.4", "ssi.3",
1076 "src.6", "src.5",
1077 "mix.1", "mix.0",
1078 "ctu.1", "ctu.0",
1079 "dvc.0", "dvc.1",
1080 "clk_a", "clk_b", "clk_i";
1081 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1082 resets = <&cpg 1005>,
1083 <&cpg 1011>, <&cpg 1012>;
1084 reset-names = "ssi-all",
1085 "ssi.4", "ssi.3";
1086 status = "disabled";
1087
1088 rcar_sound,ctu {
1089 ctu00: ctu-0 { };
1090 ctu01: ctu-1 { };
1091 ctu02: ctu-2 { };
1092 ctu03: ctu-3 { };
1093 ctu10: ctu-4 { };
1094 ctu11: ctu-5 { };
1095 ctu12: ctu-6 { };
1096 ctu13: ctu-7 { };
1097 };
1098
1099 rcar_sound,dvc {
1100 dvc0: dvc-0 {
1101 dmas = <&audma0 0xbc>;
1102 dma-names = "tx";
1103 };
1104 dvc1: dvc-1 {
1105 dmas = <&audma0 0xbe>;
1106 dma-names = "tx";
1107 };
1108 };
1109
1110 rcar_sound,mix {
1111 mix0: mix-0 { };
1112 mix1: mix-1 { };
1113 };
1114
1115 rcar_sound,src {
1116 src5: src-5 {
1117 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1118 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1119 dma-names = "rx", "tx";
1120 };
1121 src6: src-6 {
1122 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1123 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1124 dma-names = "rx", "tx";
1125 };
1126 };
1127
1128 rcar_sound,ssi {
1129 ssi3: ssi-3 {
1130 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1131 dmas = <&audma0 0x07>, <&audma0 0x08>,
1132 <&audma0 0x6f>, <&audma0 0x70>;
1133 dma-names = "rx", "tx", "rxu", "txu";
1134 };
1135 ssi4: ssi-4 {
1136 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1137 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1138 <&audma0 0x71>, <&audma0 0x72>;
1139 dma-names = "rx", "tx", "rxu", "txu";
1140 };
1141 };
1142 };
1143
1144 mlp: mlp@ec520000 {
1145 compatible = "renesas,r8a77995-mlp",
1146 "renesas,rcar-gen3-mlp";
1147 reg = <0 0xec520000 0 0x800>;
1148 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&cpg CPG_MOD 802>;
1151 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1152 resets = <&cpg 802>;
1153 status = "disabled";
1154 };
1155
1156 audma0: dma-controller@ec700000 {
1157 compatible = "renesas,dmac-r8a77995",
1158 "renesas,rcar-dmac";
1159 reg = <0 0xec700000 0 0x10000>;
1160 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1164 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1175 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1177 interrupt-names = "error",
1178 "ch0", "ch1", "ch2", "ch3",
1179 "ch4", "ch5", "ch6", "ch7",
1180 "ch8", "ch9", "ch10", "ch11",
1181 "ch12", "ch13", "ch14", "ch15";
1182 clocks = <&cpg CPG_MOD 502>;
1183 clock-names = "fck";
1184 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1185 resets = <&cpg 502>;
1186 #dma-cells = <1>;
1187 dma-channels = <16>;
1188 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1189 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1190 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1191 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1192 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1193 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1194 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1195 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1196 };
1197
1198 ohci0: usb@ee080000 {
1199 compatible = "generic-ohci";
1200 reg = <0 0xee080000 0 0x100>;
1201 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1202 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1203 phys = <&usb2_phy0 1>;
1204 phy-names = "usb";
1205 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1206 resets = <&cpg 703>, <&cpg 704>;
1207 status = "disabled";
1208 };
1209
1210 ehci0: usb@ee080100 {
1211 compatible = "generic-ehci";
1212 reg = <0 0xee080100 0 0x100>;
1213 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1215 phys = <&usb2_phy0 2>;
1216 phy-names = "usb";
1217 companion = <&ohci0>;
1218 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1219 resets = <&cpg 703>, <&cpg 704>;
1220 status = "disabled";
1221 };
1222
1223 usb2_phy0: usb-phy@ee080200 {
1224 compatible = "renesas,usb2-phy-r8a77995",
1225 "renesas,rcar-gen3-usb2-phy";
1226 reg = <0 0xee080200 0 0x700>;
1227 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1228 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1229 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1230 resets = <&cpg 703>, <&cpg 704>;
1231 #phy-cells = <1>;
1232 status = "disabled";
1233 };
1234
1235 sdhi2: mmc@ee140000 {
1236 compatible = "renesas,sdhi-r8a77995",
1237 "renesas,rcar-gen3-sdhi";
1238 reg = <0 0xee140000 0 0x2000>;
1239 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1240 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77995_CLK_SD0H>;
1241 clock-names = "core", "clkh";
1242 max-frequency = <200000000>;
1243 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1244 resets = <&cpg 312>;
1245 iommus = <&ipmmu_ds1 34>;
1246 status = "disabled";
1247 };
1248
1249 rpc: spi@ee200000 {
1250 compatible = "renesas,r8a77995-rpc-if",
1251 "renesas,rcar-gen3-rpc-if";
1252 reg = <0 0xee200000 0 0x200>,
1253 <0 0x08000000 0 0x04000000>,
1254 <0 0xee208000 0 0x100>;
1255 reg-names = "regs", "dirmap", "wbuf";
1256 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&cpg CPG_MOD 917>;
1258 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1259 resets = <&cpg 917>;
1260 #address-cells = <1>;
1261 #size-cells = <0>;
1262 status = "disabled";
1263 };
1264
1265 gic: interrupt-controller@f1010000 {
1266 compatible = "arm,gic-400";
1267 #interrupt-cells = <3>;
1268 #address-cells = <0>;
1269 interrupt-controller;
1270 reg = <0x0 0xf1010000 0 0x1000>,
1271 <0x0 0xf1020000 0 0x20000>,
1272 <0x0 0xf1040000 0 0x20000>,
1273 <0x0 0xf1060000 0 0x20000>;
1274 interrupts = <GIC_PPI 9
1275 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
1276 clocks = <&cpg CPG_MOD 408>;
1277 clock-names = "clk";
1278 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1279 resets = <&cpg 408>;
1280 };
1281
1282 vspbs: vsp@fe960000 {
1283 compatible = "renesas,vsp2";
1284 reg = <0 0xfe960000 0 0x8000>;
1285 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
1286 clocks = <&cpg CPG_MOD 627>;
1287 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1288 resets = <&cpg 627>;
1289 renesas,fcp = <&fcpvb0>;
1290 };
1291
1292 vspd0: vsp@fea20000 {
1293 compatible = "renesas,vsp2";
1294 reg = <0 0xfea20000 0 0x5000>;
1295 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1296 clocks = <&cpg CPG_MOD 623>;
1297 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1298 resets = <&cpg 623>;
1299 renesas,fcp = <&fcpvd0>;
1300 };
1301
1302 vspd1: vsp@fea28000 {
1303 compatible = "renesas,vsp2";
1304 reg = <0 0xfea28000 0 0x5000>;
1305 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1306 clocks = <&cpg CPG_MOD 622>;
1307 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1308 resets = <&cpg 622>;
1309 renesas,fcp = <&fcpvd1>;
1310 };
1311
1312 fcpvb0: fcp@fe96f000 {
1313 compatible = "renesas,fcpv";
1314 reg = <0 0xfe96f000 0 0x200>;
1315 clocks = <&cpg CPG_MOD 607>;
1316 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1317 resets = <&cpg 607>;
1318 iommus = <&ipmmu_vp0 5>;
1319 };
1320
1321 fcpvd0: fcp@fea27000 {
1322 compatible = "renesas,fcpv";
1323 reg = <0 0xfea27000 0 0x200>;
1324 clocks = <&cpg CPG_MOD 603>;
1325 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1326 resets = <&cpg 603>;
1327 iommus = <&ipmmu_vi0 8>;
1328 };
1329
1330 fcpvd1: fcp@fea2f000 {
1331 compatible = "renesas,fcpv";
1332 reg = <0 0xfea2f000 0 0x200>;
1333 clocks = <&cpg CPG_MOD 602>;
1334 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1335 resets = <&cpg 602>;
1336 iommus = <&ipmmu_vi0 9>;
1337 };
1338
1339 cmm0: cmm@fea40000 {
1340 compatible = "renesas,r8a77995-cmm",
1341 "renesas,rcar-gen3-cmm";
1342 reg = <0 0xfea40000 0 0x1000>;
1343 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1344 clocks = <&cpg CPG_MOD 711>;
1345 resets = <&cpg 711>;
1346 };
1347
1348 cmm1: cmm@fea50000 {
1349 compatible = "renesas,r8a77995-cmm",
1350 "renesas,rcar-gen3-cmm";
1351 reg = <0 0xfea50000 0 0x1000>;
1352 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1353 clocks = <&cpg CPG_MOD 710>;
1354 resets = <&cpg 710>;
1355 };
1356
1357 du: display@feb00000 {
1358 compatible = "renesas,du-r8a77995";
1359 reg = <0 0xfeb00000 0 0x40000>;
1360 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1361 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1362 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1363 clock-names = "du.0", "du.1";
1364 resets = <&cpg 724>;
1365 reset-names = "du.0";
1366
1367 renesas,cmms = <&cmm0>, <&cmm1>;
1368 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1369
1370 status = "disabled";
1371
1372 ports {
1373 #address-cells = <1>;
1374 #size-cells = <0>;
1375
1376 port@0 {
1377 reg = <0>;
1378 };
1379
1380 port@1 {
1381 reg = <1>;
1382 du_out_lvds0: endpoint {
1383 remote-endpoint = <&lvds0_in>;
1384 };
1385 };
1386
1387 port@2 {
1388 reg = <2>;
1389 du_out_lvds1: endpoint {
1390 remote-endpoint = <&lvds1_in>;
1391 };
1392 };
1393 };
1394 };
1395
1396 lvds0: lvds-encoder@feb90000 {
1397 compatible = "renesas,r8a77995-lvds";
1398 reg = <0 0xfeb90000 0 0x20>;
1399 clocks = <&cpg CPG_MOD 727>;
1400 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1401 resets = <&cpg 727>;
1402 status = "disabled";
1403
1404 renesas,companion = <&lvds1>;
1405
1406 ports {
1407 #address-cells = <1>;
1408 #size-cells = <0>;
1409
1410 port@0 {
1411 reg = <0>;
1412 lvds0_in: endpoint {
1413 remote-endpoint = <&du_out_lvds0>;
1414 };
1415 };
1416
1417 port@1 {
1418 reg = <1>;
1419 };
1420 };
1421 };
1422
1423 lvds1: lvds-encoder@feb90100 {
1424 compatible = "renesas,r8a77995-lvds";
1425 reg = <0 0xfeb90100 0 0x20>;
1426 clocks = <&cpg CPG_MOD 727>;
1427 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1428 resets = <&cpg 726>;
1429 status = "disabled";
1430
1431 ports {
1432 #address-cells = <1>;
1433 #size-cells = <0>;
1434
1435 port@0 {
1436 reg = <0>;
1437 lvds1_in: endpoint {
1438 remote-endpoint = <&du_out_lvds1>;
1439 };
1440 };
1441
1442 port@1 {
1443 reg = <1>;
1444 };
1445 };
1446 };
1447
1448 prr: chipid@fff00044 {
1449 compatible = "renesas,prr";
1450 reg = <0 0xfff00044 0 4>;
1451 };
1452 };
1453
1454 thermal-zones {
1455 cpu_thermal: cpu-thermal {
1456 polling-delay-passive = <250>;
1457 polling-delay = <1000>;
1458 thermal-sensors = <&thermal>;
1459
1460 cooling-maps {
1461 };
1462
1463 trips {
1464 cpu-crit {
1465 temperature = <120000>;
1466 hysteresis = <2000>;
1467 type = "critical";
1468 };
1469 };
1470 };
1471 };
1472
1473 timer {
1474 compatible = "arm,armv8-timer";
1475 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1476 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1477 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1478 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
1479 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
1480 };
1481 };
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