1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
11
12 / {
13 compatible = "renesas,r8a779f0";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 cluster01_opp: opp-table-0 {
18 compatible = "operating-points-v2";
19 opp-shared;
20
21 opp-500000000 {
22 opp-hz = /bits/ 64 <500000000>;
23 opp-microvolt = <880000>;
24 clock-latency-ns = <500000>;
25 };
26 opp-800000000 {
27 opp-hz = /bits/ 64 <800000000>;
28 opp-microvolt = <880000>;
29 clock-latency-ns = <500000>;
30 };
31 opp-1000000000 {
32 opp-hz = /bits/ 64 <1000000000>;
33 opp-microvolt = <880000>;
34 clock-latency-ns = <500000>;
35 };
36 opp-1200000000 {
37 opp-hz = /bits/ 64 <1200000000>;
38 opp-microvolt = <880000>;
39 clock-latency-ns = <500000>;
40 opp-suspend;
41 };
42 };
43
44 cluster23_opp: opp-table-1 {
45 compatible = "operating-points-v2";
46 opp-shared;
47
48 opp-500000000 {
49 opp-hz = /bits/ 64 <500000000>;
50 opp-microvolt = <880000>;
51 clock-latency-ns = <500000>;
52 };
53 opp-800000000 {
54 opp-hz = /bits/ 64 <800000000>;
55 opp-microvolt = <880000>;
56 clock-latency-ns = <500000>;
57 };
58 opp-1000000000 {
59 opp-hz = /bits/ 64 <1000000000>;
60 opp-microvolt = <880000>;
61 clock-latency-ns = <500000>;
62 };
63 opp-1200000000 {
64 opp-hz = /bits/ 64 <1200000000>;
65 opp-microvolt = <880000>;
66 clock-latency-ns = <500000>;
67 opp-suspend;
68 };
69 };
70
71 cpus {
72 #address-cells = <1>;
73 #size-cells = <0>;
74
75 cpu-map {
76 cluster0 {
77 core0 {
78 cpu = <&a55_0>;
79 };
80 core1 {
81 cpu = <&a55_1>;
82 };
83 };
84
85 cluster1 {
86 core0 {
87 cpu = <&a55_2>;
88 };
89 core1 {
90 cpu = <&a55_3>;
91 };
92 };
93
94 cluster2 {
95 core0 {
96 cpu = <&a55_4>;
97 };
98 core1 {
99 cpu = <&a55_5>;
100 };
101 };
102
103 cluster3 {
104 core0 {
105 cpu = <&a55_6>;
106 };
107 core1 {
108 cpu = <&a55_7>;
109 };
110 };
111 };
112
113 a55_0: cpu@0 {
114 compatible = "arm,cortex-a55";
115 reg = <0>;
116 device_type = "cpu";
117 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
118 next-level-cache = <&L3_CA55_0>;
119 enable-method = "psci";
120 cpu-idle-states = <&CPU_SLEEP_0>;
121 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
122 operating-points-v2 = <&cluster01_opp>;
123 };
124
125 a55_1: cpu@100 {
126 compatible = "arm,cortex-a55";
127 reg = <0x100>;
128 device_type = "cpu";
129 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
130 next-level-cache = <&L3_CA55_0>;
131 enable-method = "psci";
132 cpu-idle-states = <&CPU_SLEEP_0>;
133 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
134 operating-points-v2 = <&cluster01_opp>;
135 };
136
137 a55_2: cpu@10000 {
138 compatible = "arm,cortex-a55";
139 reg = <0x10000>;
140 device_type = "cpu";
141 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
142 next-level-cache = <&L3_CA55_1>;
143 enable-method = "psci";
144 cpu-idle-states = <&CPU_SLEEP_0>;
145 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
146 operating-points-v2 = <&cluster01_opp>;
147 };
148
149 a55_3: cpu@10100 {
150 compatible = "arm,cortex-a55";
151 reg = <0x10100>;
152 device_type = "cpu";
153 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
154 next-level-cache = <&L3_CA55_1>;
155 enable-method = "psci";
156 cpu-idle-states = <&CPU_SLEEP_0>;
157 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
158 operating-points-v2 = <&cluster01_opp>;
159 };
160
161 a55_4: cpu@20000 {
162 compatible = "arm,cortex-a55";
163 reg = <0x20000>;
164 device_type = "cpu";
165 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
166 next-level-cache = <&L3_CA55_2>;
167 enable-method = "psci";
168 cpu-idle-states = <&CPU_SLEEP_0>;
169 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
170 operating-points-v2 = <&cluster23_opp>;
171 };
172
173 a55_5: cpu@20100 {
174 compatible = "arm,cortex-a55";
175 reg = <0x20100>;
176 device_type = "cpu";
177 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
178 next-level-cache = <&L3_CA55_2>;
179 enable-method = "psci";
180 cpu-idle-states = <&CPU_SLEEP_0>;
181 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
182 operating-points-v2 = <&cluster23_opp>;
183 };
184
185 a55_6: cpu@30000 {
186 compatible = "arm,cortex-a55";
187 reg = <0x30000>;
188 device_type = "cpu";
189 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
190 next-level-cache = <&L3_CA55_3>;
191 enable-method = "psci";
192 cpu-idle-states = <&CPU_SLEEP_0>;
193 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
194 operating-points-v2 = <&cluster23_opp>;
195 };
196
197 a55_7: cpu@30100 {
198 compatible = "arm,cortex-a55";
199 reg = <0x30100>;
200 device_type = "cpu";
201 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
202 next-level-cache = <&L3_CA55_3>;
203 enable-method = "psci";
204 cpu-idle-states = <&CPU_SLEEP_0>;
205 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
206 operating-points-v2 = <&cluster23_opp>;
207 };
208
209 L3_CA55_0: cache-controller-0 {
210 compatible = "cache";
211 power-domains = <&sysc R8A779F0_PD_A2E0D0>;
212 cache-unified;
213 cache-level = <3>;
214 };
215
216 L3_CA55_1: cache-controller-1 {
217 compatible = "cache";
218 power-domains = <&sysc R8A779F0_PD_A2E0D1>;
219 cache-unified;
220 cache-level = <3>;
221 };
222
223 L3_CA55_2: cache-controller-2 {
224 compatible = "cache";
225 power-domains = <&sysc R8A779F0_PD_A2E1D0>;
226 cache-unified;
227 cache-level = <3>;
228 };
229
230 L3_CA55_3: cache-controller-3 {
231 compatible = "cache";
232 power-domains = <&sysc R8A779F0_PD_A2E1D1>;
233 cache-unified;
234 cache-level = <3>;
235 };
236
237 idle-states {
238 entry-method = "psci";
239
240 CPU_SLEEP_0: cpu-sleep-0 {
241 compatible = "arm,idle-state";
242 arm,psci-suspend-param = <0x0010000>;
243 local-timer-stop;
244 entry-latency-us = <400>;
245 exit-latency-us = <500>;
246 min-residency-us = <4000>;
247 };
248 };
249 };
250
251 extal_clk: extal {
252 compatible = "fixed-clock";
253 #clock-cells = <0>;
254 /* This value must be overridden by the board */
255 clock-frequency = <0>;
256 };
257
258 extalr_clk: extalr {
259 compatible = "fixed-clock";
260 #clock-cells = <0>;
261 /* This value must be overridden by the board */
262 clock-frequency = <0>;
263 };
264
265 pcie0_clkref: pcie0-clkref {
266 compatible = "fixed-clock";
267 #clock-cells = <0>;
268 /* This value must be overridden by the board */
269 clock-frequency = <0>;
270 };
271
272 pcie1_clkref: pcie1-clkref {
273 compatible = "fixed-clock";
274 #clock-cells = <0>;
275 /* This value must be overridden by the board */
276 clock-frequency = <0>;
277 };
278
279 pmu_a55 {
280 compatible = "arm,cortex-a55-pmu";
281 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
282 };
283
284 psci {
285 compatible = "arm,psci-1.0", "arm,psci-0.2";
286 method = "smc";
287 };
288
289 /* External SCIF clock - to be overridden by boards that provide it */
290 scif_clk: scif {
291 compatible = "fixed-clock";
292 #clock-cells = <0>;
293 clock-frequency = <0>;
294 };
295
296 soc: soc {
297 compatible = "simple-bus";
298 interrupt-parent = <&gic>;
299 #address-cells = <2>;
300 #size-cells = <2>;
301 ranges;
302
303 rwdt: watchdog@e6020000 {
304 compatible = "renesas,r8a779f0-wdt",
305 "renesas,rcar-gen4-wdt";
306 reg = <0 0xe6020000 0 0x0c>;
307 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&cpg CPG_MOD 907>;
309 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
310 resets = <&cpg 907>;
311 status = "disabled";
312 };
313
314 pfc: pinctrl@e6050000 {
315 compatible = "renesas,pfc-r8a779f0";
316 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
317 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
318 };
319
320 gpio0: gpio@e6050180 {
321 compatible = "renesas,gpio-r8a779f0",
322 "renesas,rcar-gen4-gpio";
323 reg = <0 0xe6050180 0 0x54>;
324 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cpg CPG_MOD 915>;
326 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
327 resets = <&cpg 915>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 gpio-ranges = <&pfc 0 0 21>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 };
334
335 gpio1: gpio@e6050980 {
336 compatible = "renesas,gpio-r8a779f0",
337 "renesas,rcar-gen4-gpio";
338 reg = <0 0xe6050980 0 0x54>;
339 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&cpg CPG_MOD 915>;
341 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
342 resets = <&cpg 915>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 gpio-ranges = <&pfc 0 32 25>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 };
349
350 gpio2: gpio@e6051180 {
351 compatible = "renesas,gpio-r8a779f0",
352 "renesas,rcar-gen4-gpio";
353 reg = <0 0xe6051180 0 0x54>;
354 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&cpg CPG_MOD 915>;
356 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
357 resets = <&cpg 915>;
358 gpio-controller;
359 #gpio-cells = <2>;
360 gpio-ranges = <&pfc 0 64 17>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
363 };
364
365 gpio3: gpio@e6051980 {
366 compatible = "renesas,gpio-r8a779f0",
367 "renesas,rcar-gen4-gpio";
368 reg = <0 0xe6051980 0 0x54>;
369 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&cpg CPG_MOD 915>;
371 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
372 resets = <&cpg 915>;
373 gpio-controller;
374 #gpio-cells = <2>;
375 gpio-ranges = <&pfc 0 96 19>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
378 };
379
380 cmt0: timer@e60f0000 {
381 compatible = "renesas,r8a779f0-cmt0",
382 "renesas,rcar-gen4-cmt0";
383 reg = <0 0xe60f0000 0 0x1004>;
384 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&cpg CPG_MOD 910>;
387 clock-names = "fck";
388 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
389 resets = <&cpg 910>;
390 status = "disabled";
391 };
392
393 cmt1: timer@e6130000 {
394 compatible = "renesas,r8a779f0-cmt1",
395 "renesas,rcar-gen4-cmt1";
396 reg = <0 0xe6130000 0 0x1004>;
397 interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&cpg CPG_MOD 911>;
406 clock-names = "fck";
407 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
408 resets = <&cpg 911>;
409 status = "disabled";
410 };
411
412 cmt2: timer@e6140000 {
413 compatible = "renesas,r8a779f0-cmt1",
414 "renesas,rcar-gen4-cmt1";
415 reg = <0 0xe6140000 0 0x1004>;
416 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&cpg CPG_MOD 912>;
425 clock-names = "fck";
426 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
427 resets = <&cpg 912>;
428 status = "disabled";
429 };
430
431 cmt3: timer@e6148000 {
432 compatible = "renesas,r8a779f0-cmt1",
433 "renesas,rcar-gen4-cmt1";
434 reg = <0 0xe6148000 0 0x1004>;
435 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&cpg CPG_MOD 913>;
444 clock-names = "fck";
445 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
446 resets = <&cpg 913>;
447 status = "disabled";
448 };
449
450 cpg: clock-controller@e6150000 {
451 compatible = "renesas,r8a779f0-cpg-mssr";
452 reg = <0 0xe6150000 0 0x4000>;
453 clocks = <&extal_clk>, <&extalr_clk>;
454 clock-names = "extal", "extalr";
455 #clock-cells = <2>;
456 #power-domain-cells = <0>;
457 #reset-cells = <1>;
458 };
459
460 rst: reset-controller@e6160000 {
461 compatible = "renesas,r8a779f0-rst";
462 reg = <0 0xe6160000 0 0x4000>;
463 };
464
465 sysc: system-controller@e6180000 {
466 compatible = "renesas,r8a779f0-sysc";
467 reg = <0 0xe6180000 0 0x4000>;
468 #power-domain-cells = <1>;
469 };
470
471 tsc: thermal@e6198000 {
472 compatible = "renesas,r8a779f0-thermal";
473 /* The 4th sensor is in control domain and not for Linux */
474 reg = <0 0xe6198000 0 0x200>,
475 <0 0xe61a0000 0 0x200>,
476 <0 0xe61a8000 0 0x200>;
477 clocks = <&cpg CPG_MOD 919>;
478 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
479 resets = <&cpg 919>;
480 #thermal-sensor-cells = <1>;
481 };
482
483 intc_ex: interrupt-controller@e61c0000 {
484 compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc";
485 #interrupt-cells = <2>;
486 interrupt-controller;
487 reg = <0 0xe61c0000 0 0x200>;
488 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cpg CPG_CORE R8A779F0_CLK_CL16M>;
495 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
496 };
497
498 tmu0: timer@e61e0000 {
499 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
500 reg = <0 0xe61e0000 0 0x30>;
501 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
504 interrupt-names = "tuni0", "tuni1", "tuni2";
505 clocks = <&cpg CPG_MOD 713>;
506 clock-names = "fck";
507 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
508 resets = <&cpg 713>;
509 status = "disabled";
510 };
511
512 tmu1: timer@e6fc0000 {
513 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
514 reg = <0 0xe6fc0000 0 0x30>;
515 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>;
519 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
520 clocks = <&cpg CPG_MOD 714>;
521 clock-names = "fck";
522 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
523 resets = <&cpg 714>;
524 status = "disabled";
525 };
526
527 tmu2: timer@e6fd0000 {
528 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
529 reg = <0 0xe6fd0000 0 0x30>;
530 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>;
534 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
535 clocks = <&cpg CPG_MOD 715>;
536 clock-names = "fck";
537 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
538 resets = <&cpg 715>;
539 status = "disabled";
540 };
541
542 tmu3: timer@e6fe0000 {
543 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
544 reg = <0 0xe6fe0000 0 0x30>;
545 interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>;
549 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
550 clocks = <&cpg CPG_MOD 716>;
551 clock-names = "fck";
552 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
553 resets = <&cpg 716>;
554 status = "disabled";
555 };
556
557 tmu4: timer@ffc00000 {
558 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
559 reg = <0 0xffc00000 0 0x30>;
560 interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>;
564 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
565 clocks = <&cpg CPG_MOD 717>;
566 clock-names = "fck";
567 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
568 resets = <&cpg 717>;
569 status = "disabled";
570 };
571
572 eth_serdes: phy@e6444000 {
573 compatible = "renesas,r8a779f0-ether-serdes";
574 reg = <0 0xe6444000 0 0x2800>;
575 clocks = <&cpg CPG_MOD 1506>;
576 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
577 resets = <&cpg 1506>;
578 #phy-cells = <1>;
579 status = "disabled";
580 };
581
582 i2c0: i2c@e6500000 {
583 compatible = "renesas,i2c-r8a779f0",
584 "renesas,rcar-gen4-i2c";
585 reg = <0 0xe6500000 0 0x40>;
586 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&cpg CPG_MOD 518>;
588 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
589 resets = <&cpg 518>;
590 dmas = <&dmac0 0x91>, <&dmac0 0x90>,
591 <&dmac1 0x91>, <&dmac1 0x90>;
592 dma-names = "tx", "rx", "tx", "rx";
593 i2c-scl-internal-delay-ns = <110>;
594 #address-cells = <1>;
595 #size-cells = <0>;
596 status = "disabled";
597 };
598
599 i2c1: i2c@e6508000 {
600 compatible = "renesas,i2c-r8a779f0",
601 "renesas,rcar-gen4-i2c";
602 reg = <0 0xe6508000 0 0x40>;
603 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cpg CPG_MOD 519>;
605 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
606 resets = <&cpg 519>;
607 dmas = <&dmac0 0x93>, <&dmac0 0x92>,
608 <&dmac1 0x93>, <&dmac1 0x92>;
609 dma-names = "tx", "rx", "tx", "rx";
610 i2c-scl-internal-delay-ns = <110>;
611 #address-cells = <1>;
612 #size-cells = <0>;
613 status = "disabled";
614 };
615
616 i2c2: i2c@e6510000 {
617 compatible = "renesas,i2c-r8a779f0",
618 "renesas,rcar-gen4-i2c";
619 reg = <0 0xe6510000 0 0x40>;
620 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&cpg CPG_MOD 520>;
622 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
623 resets = <&cpg 520>;
624 dmas = <&dmac0 0x95>, <&dmac0 0x94>,
625 <&dmac1 0x95>, <&dmac1 0x94>;
626 dma-names = "tx", "rx", "tx", "rx";
627 i2c-scl-internal-delay-ns = <110>;
628 #address-cells = <1>;
629 #size-cells = <0>;
630 status = "disabled";
631 };
632
633 i2c3: i2c@e66d0000 {
634 compatible = "renesas,i2c-r8a779f0",
635 "renesas,rcar-gen4-i2c";
636 reg = <0 0xe66d0000 0 0x40>;
637 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&cpg CPG_MOD 521>;
639 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
640 resets = <&cpg 521>;
641 dmas = <&dmac0 0x97>, <&dmac0 0x96>,
642 <&dmac1 0x97>, <&dmac1 0x96>;
643 dma-names = "tx", "rx", "tx", "rx";
644 i2c-scl-internal-delay-ns = <110>;
645 #address-cells = <1>;
646 #size-cells = <0>;
647 status = "disabled";
648 };
649
650 i2c4: i2c@e66d8000 {
651 compatible = "renesas,i2c-r8a779f0",
652 "renesas,rcar-gen4-i2c";
653 reg = <0 0xe66d8000 0 0x40>;
654 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cpg CPG_MOD 522>;
656 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
657 resets = <&cpg 522>;
658 dmas = <&dmac0 0x99>, <&dmac0 0x98>,
659 <&dmac1 0x99>, <&dmac1 0x98>;
660 dma-names = "tx", "rx", "tx", "rx";
661 i2c-scl-internal-delay-ns = <110>;
662 #address-cells = <1>;
663 #size-cells = <0>;
664 status = "disabled";
665 };
666
667 i2c5: i2c@e66e0000 {
668 compatible = "renesas,i2c-r8a779f0",
669 "renesas,rcar-gen4-i2c";
670 reg = <0 0xe66e0000 0 0x40>;
671 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&cpg CPG_MOD 523>;
673 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
674 resets = <&cpg 523>;
675 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
676 <&dmac1 0x9b>, <&dmac1 0x9a>;
677 dma-names = "tx", "rx", "tx", "rx";
678 i2c-scl-internal-delay-ns = <110>;
679 #address-cells = <1>;
680 #size-cells = <0>;
681 status = "disabled";
682 };
683
684 hscif0: serial@e6540000 {
685 compatible = "renesas,hscif-r8a779f0",
686 "renesas,rcar-gen4-hscif", "renesas,hscif";
687 reg = <0 0xe6540000 0 0x60>;
688 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&cpg CPG_MOD 514>,
690 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
691 <&scif_clk>;
692 clock-names = "fck", "brg_int", "scif_clk";
693 dmas = <&dmac0 0x31>, <&dmac0 0x30>,
694 <&dmac1 0x31>, <&dmac1 0x30>;
695 dma-names = "tx", "rx", "tx", "rx";
696 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
697 resets = <&cpg 514>;
698 status = "disabled";
699 };
700
701 hscif1: serial@e6550000 {
702 compatible = "renesas,hscif-r8a779f0",
703 "renesas,rcar-gen4-hscif", "renesas,hscif";
704 reg = <0 0xe6550000 0 0x60>;
705 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cpg CPG_MOD 515>,
707 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
708 <&scif_clk>;
709 clock-names = "fck", "brg_int", "scif_clk";
710 dmas = <&dmac0 0x33>, <&dmac0 0x32>,
711 <&dmac1 0x33>, <&dmac1 0x32>;
712 dma-names = "tx", "rx", "tx", "rx";
713 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
714 resets = <&cpg 515>;
715 status = "disabled";
716 };
717
718 hscif2: serial@e6560000 {
719 compatible = "renesas,hscif-r8a779f0",
720 "renesas,rcar-gen4-hscif", "renesas,hscif";
721 reg = <0 0xe6560000 0 0x60>;
722 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&cpg CPG_MOD 516>,
724 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
725 <&scif_clk>;
726 clock-names = "fck", "brg_int", "scif_clk";
727 dmas = <&dmac0 0x35>, <&dmac0 0x34>,
728 <&dmac1 0x35>, <&dmac1 0x34>;
729 dma-names = "tx", "rx", "tx", "rx";
730 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
731 resets = <&cpg 516>;
732 status = "disabled";
733 };
734
735 hscif3: serial@e66a0000 {
736 compatible = "renesas,hscif-r8a779f0",
737 "renesas,rcar-gen4-hscif", "renesas,hscif";
738 reg = <0 0xe66a0000 0 0x60>;
739 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&cpg CPG_MOD 517>,
741 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
742 <&scif_clk>;
743 clock-names = "fck", "brg_int", "scif_clk";
744 dmas = <&dmac0 0x37>, <&dmac0 0x36>,
745 <&dmac1 0x37>, <&dmac1 0x36>;
746 dma-names = "tx", "rx", "tx", "rx";
747 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
748 resets = <&cpg 517>;
749 status = "disabled";
750 };
751
752 pciec0: pcie@e65d0000 {
753 compatible = "renesas,r8a779f0-pcie",
754 "renesas,rcar-gen4-pcie";
755 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
756 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
757 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
758 <0 0xfe000000 0 0x400000>;
759 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
760 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
764 interrupt-names = "msi", "dma", "sft_ce", "app";
765 clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
766 clock-names = "core", "ref";
767 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
768 resets = <&cpg 624>;
769 reset-names = "pwr";
770 max-link-speed = <4>;
771 num-lanes = <2>;
772 #address-cells = <3>;
773 #size-cells = <2>;
774 bus-range = <0x00 0xff>;
775 device_type = "pci";
776 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
777 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
778 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
779 #interrupt-cells = <1>;
780 interrupt-map-mask = <0 0 0 7>;
781 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
782 <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
783 <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
784 <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
785 snps,enable-cdm-check;
786 status = "disabled";
787 };
788
789 pciec1: pcie@e65d8000 {
790 compatible = "renesas,r8a779f0-pcie",
791 "renesas,rcar-gen4-pcie";
792 reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>,
793 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
794 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
795 <0 0xee900000 0 0x400000>;
796 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
797 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
798 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
799 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
800 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
801 interrupt-names = "msi", "dma", "sft_ce", "app";
802 clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
803 clock-names = "core", "ref";
804 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
805 resets = <&cpg 625>;
806 reset-names = "pwr";
807 max-link-speed = <4>;
808 num-lanes = <2>;
809 #address-cells = <3>;
810 #size-cells = <2>;
811 bus-range = <0x00 0xff>;
812 device_type = "pci";
813 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>,
814 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
815 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
816 #interrupt-cells = <1>;
817 interrupt-map-mask = <0 0 0 7>;
818 interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
819 <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
820 <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
821 <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
822 snps,enable-cdm-check;
823 status = "disabled";
824 };
825
826 pciec0_ep: pcie-ep@e65d0000 {
827 compatible = "renesas,r8a779f0-pcie-ep",
828 "renesas,rcar-gen4-pcie-ep";
829 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
830 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
831 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
832 <0 0xfe000000 0 0x400000>;
833 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
834 interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
837 interrupt-names = "dma", "sft_ce", "app";
838 clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
839 clock-names = "core", "ref";
840 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
841 resets = <&cpg 624>;
842 reset-names = "pwr";
843 max-link-speed = <4>;
844 num-lanes = <2>;
845 max-functions = /bits/ 8 <2>;
846 status = "disabled";
847 };
848
849 pciec1_ep: pcie-ep@e65d8000 {
850 compatible = "renesas,r8a779f0-pcie-ep",
851 "renesas,rcar-gen4-pcie-ep";
852 reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>,
853 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
854 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
855 <0 0xee900000 0 0x400000>;
856 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
857 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
858 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
859 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
860 interrupt-names = "dma", "sft_ce", "app";
861 clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
862 clock-names = "core", "ref";
863 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
864 resets = <&cpg 625>;
865 reset-names = "pwr";
866 max-link-speed = <4>;
867 num-lanes = <2>;
868 max-functions = /bits/ 8 <2>;
869 status = "disabled";
870 };
871
872 ufs: ufs@e6860000 {
873 compatible = "renesas,r8a779f0-ufs";
874 reg = <0 0xe6860000 0 0x100>;
875 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
877 clock-names = "fck", "ref_clk";
878 freq-table-hz = <200000000 200000000>, <38400000 38400000>;
879 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
880 resets = <&cpg 1514>;
881 status = "disabled";
882 };
883
884 rswitch: ethernet@e6880000 {
885 compatible = "renesas,r8a779f0-ether-switch";
886 reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>;
887 reg-names = "base", "secure_base";
888 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
889 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
893 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
894 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
895 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
899 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
900 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
901 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
903 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
904 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
905 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
906 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
907 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
911 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
912 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
913 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
914 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
917 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
918 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
935 interrupt-names = "mfwd_error", "race_error",
936 "coma_error", "gwca0_error",
937 "gwca1_error", "etha0_error",
938 "etha1_error", "etha2_error",
939 "gptp0_status", "gptp1_status",
940 "mfwd_status", "race_status",
941 "coma_status", "gwca0_status",
942 "gwca1_status", "etha0_status",
943 "etha1_status", "etha2_status",
944 "rmac0_status", "rmac1_status",
945 "rmac2_status",
946 "gwca0_rxtx0", "gwca0_rxtx1",
947 "gwca0_rxtx2", "gwca0_rxtx3",
948 "gwca0_rxtx4", "gwca0_rxtx5",
949 "gwca0_rxtx6", "gwca0_rxtx7",
950 "gwca1_rxtx0", "gwca1_rxtx1",
951 "gwca1_rxtx2", "gwca1_rxtx3",
952 "gwca1_rxtx4", "gwca1_rxtx5",
953 "gwca1_rxtx6", "gwca1_rxtx7",
954 "gwca0_rxts0", "gwca0_rxts1",
955 "gwca1_rxts0", "gwca1_rxts1",
956 "rmac0_mdio", "rmac1_mdio",
957 "rmac2_mdio",
958 "rmac0_phy", "rmac1_phy",
959 "rmac2_phy";
960 clocks = <&cpg CPG_MOD 1505>;
961 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
962 resets = <&cpg 1505>;
963 status = "disabled";
964
965 ethernet-ports {
966 #address-cells = <1>;
967 #size-cells = <0>;
968
969 port@0 {
970 reg = <0>;
971 phys = <ð_serdes 0>;
972 };
973 port@1 {
974 reg = <1>;
975 phys = <ð_serdes 1>;
976 };
977 port@2 {
978 reg = <2>;
979 phys = <ð_serdes 2>;
980 };
981 };
982 };
983
984 scif0: serial@e6e60000 {
985 compatible = "renesas,scif-r8a779f0",
986 "renesas,rcar-gen4-scif", "renesas,scif";
987 reg = <0 0xe6e60000 0 64>;
988 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&cpg CPG_MOD 702>,
990 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
991 <&scif_clk>;
992 clock-names = "fck", "brg_int", "scif_clk";
993 dmas = <&dmac0 0x51>, <&dmac0 0x50>,
994 <&dmac1 0x51>, <&dmac1 0x50>;
995 dma-names = "tx", "rx", "tx", "rx";
996 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
997 resets = <&cpg 702>;
998 status = "disabled";
999 };
1000
1001 scif1: serial@e6e68000 {
1002 compatible = "renesas,scif-r8a779f0",
1003 "renesas,rcar-gen4-scif", "renesas,scif";
1004 reg = <0 0xe6e68000 0 64>;
1005 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&cpg CPG_MOD 703>,
1007 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
1008 <&scif_clk>;
1009 clock-names = "fck", "brg_int", "scif_clk";
1010 dmas = <&dmac0 0x53>, <&dmac0 0x52>,
1011 <&dmac1 0x53>, <&dmac1 0x52>;
1012 dma-names = "tx", "rx", "tx", "rx";
1013 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1014 resets = <&cpg 703>;
1015 status = "disabled";
1016 };
1017
1018 scif3: serial@e6c50000 {
1019 compatible = "renesas,scif-r8a779f0",
1020 "renesas,rcar-gen4-scif", "renesas,scif";
1021 reg = <0 0xe6c50000 0 64>;
1022 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&cpg CPG_MOD 704>,
1024 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
1025 <&scif_clk>;
1026 clock-names = "fck", "brg_int", "scif_clk";
1027 dmas = <&dmac0 0x57>, <&dmac0 0x56>,
1028 <&dmac1 0x57>, <&dmac1 0x56>;
1029 dma-names = "tx", "rx", "tx", "rx";
1030 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1031 resets = <&cpg 704>;
1032 status = "disabled";
1033 };
1034
1035 scif4: serial@e6c40000 {
1036 compatible = "renesas,scif-r8a779f0",
1037 "renesas,rcar-gen4-scif", "renesas,scif";
1038 reg = <0 0xe6c40000 0 64>;
1039 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
1040 clocks = <&cpg CPG_MOD 705>,
1041 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
1042 <&scif_clk>;
1043 clock-names = "fck", "brg_int", "scif_clk";
1044 dmas = <&dmac0 0x59>, <&dmac0 0x58>,
1045 <&dmac1 0x59>, <&dmac1 0x58>;
1046 dma-names = "tx", "rx", "tx", "rx";
1047 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1048 resets = <&cpg 705>;
1049 status = "disabled";
1050 };
1051
1052 msiof0: spi@e6e90000 {
1053 compatible = "renesas,msiof-r8a779f0",
1054 "renesas,rcar-gen4-msiof";
1055 reg = <0 0xe6e90000 0 0x0064>;
1056 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&cpg CPG_MOD 618>;
1058 dmas = <&dmac0 0x41>, <&dmac0 0x40>,
1059 <&dmac1 0x41>, <&dmac1 0x40>;
1060 dma-names = "tx", "rx", "tx", "rx";
1061 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1062 resets = <&cpg 618>;
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1065 status = "disabled";
1066 };
1067
1068 msiof1: spi@e6ea0000 {
1069 compatible = "renesas,msiof-r8a779f0",
1070 "renesas,rcar-gen4-msiof";
1071 reg = <0 0xe6ea0000 0 0x0064>;
1072 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&cpg CPG_MOD 619>;
1074 dmas = <&dmac0 0x43>, <&dmac0 0x42>,
1075 <&dmac1 0x43>, <&dmac1 0x42>;
1076 dma-names = "tx", "rx", "tx", "rx";
1077 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1078 resets = <&cpg 619>;
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1081 status = "disabled";
1082 };
1083
1084 msiof2: spi@e6c00000 {
1085 compatible = "renesas,msiof-r8a779f0",
1086 "renesas,rcar-gen4-msiof";
1087 reg = <0 0xe6c00000 0 0x0064>;
1088 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
1089 clocks = <&cpg CPG_MOD 620>;
1090 dmas = <&dmac0 0x45>, <&dmac0 0x44>,
1091 <&dmac1 0x45>, <&dmac1 0x44>;
1092 dma-names = "tx", "rx", "tx", "rx";
1093 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1094 resets = <&cpg 620>;
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1097 status = "disabled";
1098 };
1099
1100 msiof3: spi@e6c10000 {
1101 compatible = "renesas,msiof-r8a779f0",
1102 "renesas,rcar-gen4-msiof";
1103 reg = <0 0xe6c10000 0 0x0064>;
1104 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1105 clocks = <&cpg CPG_MOD 621>;
1106 dmas = <&dmac0 0x47>, <&dmac0 0x46>,
1107 <&dmac1 0x47>, <&dmac1 0x46>;
1108 dma-names = "tx", "rx", "tx", "rx";
1109 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1110 resets = <&cpg 621>;
1111 #address-cells = <1>;
1112 #size-cells = <0>;
1113 status = "disabled";
1114 };
1115
1116 dmac0: dma-controller@e7350000 {
1117 compatible = "renesas,dmac-r8a779f0",
1118 "renesas,rcar-gen4-dmac";
1119 reg = <0 0xe7350000 0 0x1000>,
1120 <0 0xe7300000 0 0x10000>;
1121 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1122 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1123 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1124 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1125 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1126 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1127 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1128 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1129 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1130 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1131 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1132 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1133 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1134 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1135 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1136 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1137 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1138 interrupt-names = "error",
1139 "ch0", "ch1", "ch2", "ch3", "ch4",
1140 "ch5", "ch6", "ch7", "ch8", "ch9",
1141 "ch10", "ch11", "ch12", "ch13",
1142 "ch14", "ch15";
1143 clocks = <&cpg CPG_MOD 709>;
1144 clock-names = "fck";
1145 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1146 resets = <&cpg 709>;
1147 #dma-cells = <1>;
1148 dma-channels = <16>;
1149 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1150 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
1151 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
1152 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
1153 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
1154 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
1155 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
1156 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
1157 };
1158
1159 dmac1: dma-controller@e7351000 {
1160 compatible = "renesas,dmac-r8a779f0",
1161 "renesas,rcar-gen4-dmac";
1162 reg = <0 0xe7351000 0 0x1000>,
1163 <0 0xe7310000 0 0x10000>;
1164 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1175 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1177 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1178 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1179 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1180 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1181 interrupt-names = "error",
1182 "ch0", "ch1", "ch2", "ch3", "ch4",
1183 "ch5", "ch6", "ch7", "ch8", "ch9",
1184 "ch10", "ch11", "ch12", "ch13",
1185 "ch14", "ch15";
1186 clocks = <&cpg CPG_MOD 710>;
1187 clock-names = "fck";
1188 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1189 resets = <&cpg 710>;
1190 #dma-cells = <1>;
1191 dma-channels = <16>;
1192 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
1193 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
1194 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
1195 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
1196 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
1197 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
1198 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
1199 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
1200 };
1201
1202 mmc0: mmc@ee140000 {
1203 compatible = "renesas,sdhi-r8a779f0",
1204 "renesas,rcar-gen4-sdhi";
1205 reg = <0 0xee140000 0 0x2000>;
1206 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1207 clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>;
1208 clock-names = "core", "clkh";
1209 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1210 resets = <&cpg 706>;
1211 max-frequency = <200000000>;
1212 iommus = <&ipmmu_ds0 32>;
1213 status = "disabled";
1214 };
1215
1216 ipmmu_rt0: iommu@ee480000 {
1217 compatible = "renesas,ipmmu-r8a779f0",
1218 "renesas,rcar-gen4-ipmmu-vmsa";
1219 reg = <0 0xee480000 0 0x20000>;
1220 renesas,ipmmu-main = <&ipmmu_mm>;
1221 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1222 #iommu-cells = <1>;
1223 };
1224
1225 ipmmu_rt1: iommu@ee4c0000 {
1226 compatible = "renesas,ipmmu-r8a779f0",
1227 "renesas,rcar-gen4-ipmmu-vmsa";
1228 reg = <0 0xee4c0000 0 0x20000>;
1229 renesas,ipmmu-main = <&ipmmu_mm>;
1230 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1231 #iommu-cells = <1>;
1232 };
1233
1234 ipmmu_ds0: iommu@eed00000 {
1235 compatible = "renesas,ipmmu-r8a779f0",
1236 "renesas,rcar-gen4-ipmmu-vmsa";
1237 reg = <0 0xeed00000 0 0x20000>;
1238 renesas,ipmmu-main = <&ipmmu_mm>;
1239 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1240 #iommu-cells = <1>;
1241 };
1242
1243 ipmmu_hc: iommu@eed40000 {
1244 compatible = "renesas,ipmmu-r8a779f0",
1245 "renesas,rcar-gen4-ipmmu-vmsa";
1246 reg = <0 0xeed40000 0 0x20000>;
1247 renesas,ipmmu-main = <&ipmmu_mm>;
1248 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1249 #iommu-cells = <1>;
1250 };
1251
1252 ipmmu_mm: iommu@eefc0000 {
1253 compatible = "renesas,ipmmu-r8a779f0",
1254 "renesas,rcar-gen4-ipmmu-vmsa";
1255 reg = <0 0xeefc0000 0 0x20000>;
1256 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1258 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1259 #iommu-cells = <1>;
1260 };
1261
1262 gic: interrupt-controller@f1000000 {
1263 compatible = "arm,gic-v3";
1264 #interrupt-cells = <3>;
1265 #address-cells = <0>;
1266 interrupt-controller;
1267 reg = <0x0 0xf1000000 0 0x20000>,
1268 <0x0 0xf1060000 0 0x110000>;
1269 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1270 };
1271
1272 prr: chipid@fff00044 {
1273 compatible = "renesas,prr";
1274 reg = <0 0xfff00044 0 4>;
1275 };
1276 };
1277
1278 thermal-zones {
1279 sensor_thermal_rtcore: sensor1-thermal {
1280 polling-delay-passive = <250>;
1281 polling-delay = <1000>;
1282 thermal-sensors = <&tsc 0>;
1283
1284 trips {
1285 sensor1_crit: sensor1-crit {
1286 temperature = <120000>;
1287 hysteresis = <1000>;
1288 type = "critical";
1289 };
1290 };
1291 };
1292
1293 sensor_thermal_apcore0: sensor2-thermal {
1294 polling-delay-passive = <250>;
1295 polling-delay = <1000>;
1296 thermal-sensors = <&tsc 1>;
1297
1298 trips {
1299 sensor2_crit: sensor2-crit {
1300 temperature = <120000>;
1301 hysteresis = <1000>;
1302 type = "critical";
1303 };
1304 };
1305 };
1306
1307 sensor_thermal_apcore4: sensor3-thermal {
1308 polling-delay-passive = <250>;
1309 polling-delay = <1000>;
1310 thermal-sensors = <&tsc 2>;
1311
1312 trips {
1313 sensor3_crit: sensor3-crit {
1314 temperature = <120000>;
1315 hysteresis = <1000>;
1316 type = "critical";
1317 };
1318 };
1319 };
1320 };
1321
1322 timer {
1323 compatible = "arm,armv8-timer";
1324 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1325 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1326 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1327 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
1328 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
1329 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
1330 "hyp-virt";
1331 };
1332
1333 ufs30_clk: ufs30-clk {
1334 compatible = "fixed-clock";
1335 #clock-cells = <0>;
1336 /* This value must be overridden by the board */
1337 clock-frequency = <0>;
1338 };
1339 };
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