1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /*
3 * Device Tree Source for the RZ/V2L SoC
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
10
11 / {
12 compatible = "renesas,r9a07g054";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 /* This value must be overridden by boards that provide it */
20 clock-frequency = <0>;
21 };
22
23 audio_clk2: audio2-clk {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 /* This value must be overridden by boards that provide it */
27 clock-frequency = <0>;
28 };
29
30 /* External CAN clock - to be overridden by boards that provide it */
31 can_clk: can-clk {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <0>;
35 };
36
37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
38 extal_clk: extal-clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 /* This value must be overridden by the board */
42 clock-frequency = <0>;
43 };
44
45 cluster0_opp: opp-table-0 {
46 compatible = "operating-points-v2";
47 opp-shared;
48
49 opp-150000000 {
50 opp-hz = /bits/ 64 <150000000>;
51 opp-microvolt = <1100000>;
52 clock-latency-ns = <300000>;
53 };
54 opp-300000000 {
55 opp-hz = /bits/ 64 <300000000>;
56 opp-microvolt = <1100000>;
57 clock-latency-ns = <300000>;
58 };
59 opp-600000000 {
60 opp-hz = /bits/ 64 <600000000>;
61 opp-microvolt = <1100000>;
62 clock-latency-ns = <300000>;
63 };
64 opp-1200000000 {
65 opp-hz = /bits/ 64 <1200000000>;
66 opp-microvolt = <1100000>;
67 clock-latency-ns = <300000>;
68 opp-suspend;
69 };
70 };
71
72 cpus {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 cpu-map {
77 cluster0 {
78 core0 {
79 cpu = <&cpu0>;
80 };
81 core1 {
82 cpu = <&cpu1>;
83 };
84 };
85 };
86
87 cpu0: cpu@0 {
88 compatible = "arm,cortex-a55";
89 reg = <0>;
90 device_type = "cpu";
91 #cooling-cells = <2>;
92 next-level-cache = <&L3_CA55>;
93 enable-method = "psci";
94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
95 operating-points-v2 = <&cluster0_opp>;
96 };
97
98 cpu1: cpu@100 {
99 compatible = "arm,cortex-a55";
100 reg = <0x100>;
101 device_type = "cpu";
102 next-level-cache = <&L3_CA55>;
103 enable-method = "psci";
104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
105 operating-points-v2 = <&cluster0_opp>;
106 };
107
108 L3_CA55: cache-controller-0 {
109 compatible = "cache";
110 cache-unified;
111 cache-size = <0x40000>;
112 cache-level = <3>;
113 };
114 };
115
116 gpu_opp_table: opp-table-1 {
117 compatible = "operating-points-v2";
118
119 opp-500000000 {
120 opp-hz = /bits/ 64 <500000000>;
121 opp-microvolt = <1100000>;
122 };
123
124 opp-400000000 {
125 opp-hz = /bits/ 64 <400000000>;
126 opp-microvolt = <1100000>;
127 };
128
129 opp-250000000 {
130 opp-hz = /bits/ 64 <250000000>;
131 opp-microvolt = <1100000>;
132 };
133
134 opp-200000000 {
135 opp-hz = /bits/ 64 <200000000>;
136 opp-microvolt = <1100000>;
137 };
138
139 opp-125000000 {
140 opp-hz = /bits/ 64 <125000000>;
141 opp-microvolt = <1100000>;
142 };
143
144 opp-100000000 {
145 opp-hz = /bits/ 64 <100000000>;
146 opp-microvolt = <1100000>;
147 };
148
149 opp-62500000 {
150 opp-hz = /bits/ 64 <62500000>;
151 opp-microvolt = <1100000>;
152 };
153
154 opp-50000000 {
155 opp-hz = /bits/ 64 <50000000>;
156 opp-microvolt = <1100000>;
157 };
158 };
159
160 pmu {
161 compatible = "arm,cortex-a55-pmu";
162 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
163 };
164
165 psci {
166 compatible = "arm,psci-1.0", "arm,psci-0.2";
167 method = "smc";
168 };
169
170 soc: soc {
171 compatible = "simple-bus";
172 interrupt-parent = <&gic>;
173 #address-cells = <2>;
174 #size-cells = <2>;
175 ranges;
176
177 mtu3: timer@10001200 {
178 compatible = "renesas,r9a07g054-mtu3",
179 "renesas,rz-mtu3";
180 reg = <0 0x10001200 0 0xb00>;
181 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
182 <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
183 <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
184 <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
185 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
186 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
187 <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
188 <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
189 <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
190 <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
191 <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
192 <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
193 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
194 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
195 <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
196 <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
197 <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
198 <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
199 <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
200 <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
201 <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
202 <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
203 <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
204 <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
205 <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
206 <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
207 <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
208 <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
209 <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
210 <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
211 <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
212 <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
213 <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
214 <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
215 <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
216 <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
217 <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
218 <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
219 <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
220 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
221 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
222 <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
223 <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
224 <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
225 interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
226 "tciv0", "tgie0", "tgif0",
227 "tgia1", "tgib1", "tciv1", "tciu1",
228 "tgia2", "tgib2", "tciv2", "tciu2",
229 "tgia3", "tgib3", "tgic3", "tgid3",
230 "tciv3",
231 "tgia4", "tgib4", "tgic4", "tgid4",
232 "tciv4",
233 "tgiu5", "tgiv5", "tgiw5",
234 "tgia6", "tgib6", "tgic6", "tgid6",
235 "tciv6",
236 "tgia7", "tgib7", "tgic7", "tgid7",
237 "tciv7",
238 "tgia8", "tgib8", "tgic8", "tgid8",
239 "tciv8", "tciu8";
240 clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
243 #pwm-cells = <2>;
244 status = "disabled";
245 };
246
247 ssi0: ssi@10049c00 {
248 compatible = "renesas,r9a07g054-ssi",
249 "renesas,rz-ssi";
250 reg = <0 0x10049c00 0 0x400>;
251 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
253 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
254 interrupt-names = "int_req", "dma_rx", "dma_tx";
255 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
256 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
257 <&audio_clk1>, <&audio_clk2>;
258 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
259 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
260 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
261 dma-names = "tx", "rx";
262 power-domains = <&cpg>;
263 #sound-dai-cells = <0>;
264 status = "disabled";
265 };
266
267 ssi1: ssi@1004a000 {
268 compatible = "renesas,r9a07g054-ssi",
269 "renesas,rz-ssi";
270 reg = <0 0x1004a000 0 0x400>;
271 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
273 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
274 interrupt-names = "int_req", "dma_rx", "dma_tx";
275 clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
276 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
277 <&audio_clk1>, <&audio_clk2>;
278 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
279 resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
280 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
281 dma-names = "tx", "rx";
282 power-domains = <&cpg>;
283 #sound-dai-cells = <0>;
284 status = "disabled";
285 };
286
287 ssi2: ssi@1004a400 {
288 compatible = "renesas,r9a07g054-ssi",
289 "renesas,rz-ssi";
290 reg = <0 0x1004a400 0 0x400>;
291 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
293 interrupt-names = "int_req", "dma_rt";
294 clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
295 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
296 <&audio_clk1>, <&audio_clk2>;
297 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
298 resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
299 dmas = <&dmac 0x265f>;
300 dma-names = "rt";
301 power-domains = <&cpg>;
302 #sound-dai-cells = <0>;
303 status = "disabled";
304 };
305
306 ssi3: ssi@1004a800 {
307 compatible = "renesas,r9a07g054-ssi",
308 "renesas,rz-ssi";
309 reg = <0 0x1004a800 0 0x400>;
310 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
312 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
313 interrupt-names = "int_req", "dma_rx", "dma_tx";
314 clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
315 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
316 <&audio_clk1>, <&audio_clk2>;
317 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
318 resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
319 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
320 dma-names = "tx", "rx";
321 power-domains = <&cpg>;
322 #sound-dai-cells = <0>;
323 status = "disabled";
324 };
325
326 spi0: spi@1004ac00 {
327 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
328 reg = <0 0x1004ac00 0 0x400>;
329 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
332 interrupt-names = "error", "rx", "tx";
333 clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
334 resets = <&cpg R9A07G054_RSPI0_RST>;
335 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
336 dma-names = "tx", "rx";
337 power-domains = <&cpg>;
338 num-cs = <1>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 status = "disabled";
342 };
343
344 spi1: spi@1004b000 {
345 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
346 reg = <0 0x1004b000 0 0x400>;
347 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "error", "rx", "tx";
351 clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
352 resets = <&cpg R9A07G054_RSPI1_RST>;
353 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
354 dma-names = "tx", "rx";
355 power-domains = <&cpg>;
356 num-cs = <1>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 status = "disabled";
360 };
361
362 spi2: spi@1004b400 {
363 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
364 reg = <0 0x1004b400 0 0x400>;
365 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-names = "error", "rx", "tx";
369 clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
370 resets = <&cpg R9A07G054_RSPI2_RST>;
371 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
372 dma-names = "tx", "rx";
373 power-domains = <&cpg>;
374 num-cs = <1>;
375 #address-cells = <1>;
376 #size-cells = <0>;
377 status = "disabled";
378 };
379
380 scif0: serial@1004b800 {
381 compatible = "renesas,scif-r9a07g054",
382 "renesas,scif-r9a07g044";
383 reg = <0 0x1004b800 0 0x400>;
384 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-names = "eri", "rxi", "txi",
391 "bri", "dri", "tei";
392 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
393 clock-names = "fck";
394 power-domains = <&cpg>;
395 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
396 status = "disabled";
397 };
398
399 scif1: serial@1004bc00 {
400 compatible = "renesas,scif-r9a07g054",
401 "renesas,scif-r9a07g044";
402 reg = <0 0x1004bc00 0 0x400>;
403 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
409 interrupt-names = "eri", "rxi", "txi",
410 "bri", "dri", "tei";
411 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
412 clock-names = "fck";
413 power-domains = <&cpg>;
414 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
415 status = "disabled";
416 };
417
418 scif2: serial@1004c000 {
419 compatible = "renesas,scif-r9a07g054",
420 "renesas,scif-r9a07g044";
421 reg = <0 0x1004c000 0 0x400>;
422 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
428 interrupt-names = "eri", "rxi", "txi",
429 "bri", "dri", "tei";
430 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
431 clock-names = "fck";
432 power-domains = <&cpg>;
433 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
434 status = "disabled";
435 };
436
437 scif3: serial@1004c400 {
438 compatible = "renesas,scif-r9a07g054",
439 "renesas,scif-r9a07g044";
440 reg = <0 0x1004c400 0 0x400>;
441 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "eri", "rxi", "txi",
448 "bri", "dri", "tei";
449 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
450 clock-names = "fck";
451 power-domains = <&cpg>;
452 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
453 status = "disabled";
454 };
455
456 scif4: serial@1004c800 {
457 compatible = "renesas,scif-r9a07g054",
458 "renesas,scif-r9a07g044";
459 reg = <0 0x1004c800 0 0x400>;
460 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
466 interrupt-names = "eri", "rxi", "txi",
467 "bri", "dri", "tei";
468 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
469 clock-names = "fck";
470 power-domains = <&cpg>;
471 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
472 status = "disabled";
473 };
474
475 sci0: serial@1004d000 {
476 compatible = "renesas,r9a07g054-sci", "renesas,sci";
477 reg = <0 0x1004d000 0 0x400>;
478 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
480 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
481 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
482 interrupt-names = "eri", "rxi", "txi", "tei";
483 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
484 clock-names = "fck";
485 power-domains = <&cpg>;
486 resets = <&cpg R9A07G054_SCI0_RST>;
487 status = "disabled";
488 };
489
490 sci1: serial@1004d400 {
491 compatible = "renesas,r9a07g054-sci", "renesas,sci";
492 reg = <0 0x1004d400 0 0x400>;
493 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
495 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
496 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-names = "eri", "rxi", "txi", "tei";
498 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
499 clock-names = "fck";
500 power-domains = <&cpg>;
501 resets = <&cpg R9A07G054_SCI1_RST>;
502 status = "disabled";
503 };
504
505 canfd: can@10050000 {
506 compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd";
507 reg = <0 0x10050000 0 0x8000>;
508 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
516 interrupt-names = "g_err", "g_recc",
517 "ch0_err", "ch0_rec", "ch0_trx",
518 "ch1_err", "ch1_rec", "ch1_trx";
519 clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
520 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
521 <&can_clk>;
522 clock-names = "fck", "canfd", "can_clk";
523 assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
524 assigned-clock-rates = <50000000>;
525 resets = <&cpg R9A07G054_CANFD_RSTP_N>,
526 <&cpg R9A07G054_CANFD_RSTC_N>;
527 reset-names = "rstp_n", "rstc_n";
528 power-domains = <&cpg>;
529 status = "disabled";
530
531 channel0 {
532 status = "disabled";
533 };
534 channel1 {
535 status = "disabled";
536 };
537 };
538
539 i2c0: i2c@10058000 {
540 #address-cells = <1>;
541 #size-cells = <0>;
542 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
543 reg = <0 0x10058000 0 0x400>;
544 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
546 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
547 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
552 interrupt-names = "tei", "ri", "ti", "spi", "sti",
553 "naki", "ali", "tmoi";
554 clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
555 clock-frequency = <100000>;
556 resets = <&cpg R9A07G054_I2C0_MRST>;
557 power-domains = <&cpg>;
558 status = "disabled";
559 };
560
561 i2c1: i2c@10058400 {
562 #address-cells = <1>;
563 #size-cells = <0>;
564 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
565 reg = <0 0x10058400 0 0x400>;
566 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
568 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
569 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
574 interrupt-names = "tei", "ri", "ti", "spi", "sti",
575 "naki", "ali", "tmoi";
576 clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
577 clock-frequency = <100000>;
578 resets = <&cpg R9A07G054_I2C1_MRST>;
579 power-domains = <&cpg>;
580 status = "disabled";
581 };
582
583 i2c2: i2c@10058800 {
584 #address-cells = <1>;
585 #size-cells = <0>;
586 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
587 reg = <0 0x10058800 0 0x400>;
588 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
590 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
591 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
596 interrupt-names = "tei", "ri", "ti", "spi", "sti",
597 "naki", "ali", "tmoi";
598 clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
599 clock-frequency = <100000>;
600 resets = <&cpg R9A07G054_I2C2_MRST>;
601 power-domains = <&cpg>;
602 status = "disabled";
603 };
604
605 i2c3: i2c@10058c00 {
606 #address-cells = <1>;
607 #size-cells = <0>;
608 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
609 reg = <0 0x10058c00 0 0x400>;
610 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
612 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
613 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
618 interrupt-names = "tei", "ri", "ti", "spi", "sti",
619 "naki", "ali", "tmoi";
620 clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
621 clock-frequency = <100000>;
622 resets = <&cpg R9A07G054_I2C3_MRST>;
623 power-domains = <&cpg>;
624 status = "disabled";
625 };
626
627 adc: adc@10059000 {
628 compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc";
629 reg = <0 0x10059000 0 0x400>;
630 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
631 clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
632 <&cpg CPG_MOD R9A07G054_ADC_PCLK>;
633 clock-names = "adclk", "pclk";
634 resets = <&cpg R9A07G054_ADC_PRESETN>,
635 <&cpg R9A07G054_ADC_ADRST_N>;
636 reset-names = "presetn", "adrst-n";
637 power-domains = <&cpg>;
638 status = "disabled";
639
640 #address-cells = <1>;
641 #size-cells = <0>;
642
643 channel@0 {
644 reg = <0>;
645 };
646 channel@1 {
647 reg = <1>;
648 };
649 channel@2 {
650 reg = <2>;
651 };
652 channel@3 {
653 reg = <3>;
654 };
655 channel@4 {
656 reg = <4>;
657 };
658 channel@5 {
659 reg = <5>;
660 };
661 channel@6 {
662 reg = <6>;
663 };
664 channel@7 {
665 reg = <7>;
666 };
667 };
668
669 tsu: thermal@10059400 {
670 compatible = "renesas,r9a07g054-tsu",
671 "renesas,rzg2l-tsu";
672 reg = <0 0x10059400 0 0x400>;
673 clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
674 resets = <&cpg R9A07G054_TSU_PRESETN>;
675 power-domains = <&cpg>;
676 #thermal-sensor-cells = <1>;
677 };
678
679 sbc: spi@10060000 {
680 compatible = "renesas,r9a07g054-rpc-if",
681 "renesas,rzg2l-rpc-if";
682 reg = <0 0x10060000 0 0x10000>,
683 <0 0x20000000 0 0x10000000>,
684 <0 0x10070000 0 0x10000>;
685 reg-names = "regs", "dirmap", "wbuf";
686 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
688 <&cpg CPG_MOD R9A07G054_SPI_CLK>;
689 resets = <&cpg R9A07G054_SPI_RST>;
690 power-domains = <&cpg>;
691 #address-cells = <1>;
692 #size-cells = <0>;
693 status = "disabled";
694 };
695
696 cru: video@10830000 {
697 compatible = "renesas,r9a07g054-cru", "renesas,rzg2l-cru";
698 reg = <0 0x10830000 0 0x400>;
699 clocks = <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
700 <&cpg CPG_MOD R9A07G054_CRU_PCLK>,
701 <&cpg CPG_MOD R9A07G054_CRU_ACLK>;
702 clock-names = "video", "apb", "axi";
703 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
706 interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
707 resets = <&cpg R9A07G054_CRU_PRESETN>,
708 <&cpg R9A07G054_CRU_ARESETN>;
709 reset-names = "presetn", "aresetn";
710 power-domains = <&cpg>;
711 status = "disabled";
712
713 ports {
714 #address-cells = <1>;
715 #size-cells = <0>;
716
717 port@0 {
718 #address-cells = <1>;
719 #size-cells = <0>;
720
721 reg = <0>;
722 cruparallel: endpoint@0 {
723 reg = <0>;
724 };
725 };
726
727 port@1 {
728 #address-cells = <1>;
729 #size-cells = <0>;
730
731 reg = <1>;
732 crucsi2: endpoint@0 {
733 reg = <0>;
734 remote-endpoint = <&csi2cru>;
735 };
736 };
737 };
738 };
739
740 csi2: csi2@10830400 {
741 compatible = "renesas,r9a07g054-csi2", "renesas,rzg2l-csi2";
742 reg = <0 0x10830400 0 0xfc00>;
743 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&cpg CPG_MOD R9A07G054_CRU_SYSCLK>,
745 <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
746 <&cpg CPG_MOD R9A07G054_CRU_PCLK>;
747 clock-names = "system", "video", "apb";
748 resets = <&cpg R9A07G054_CRU_PRESETN>,
749 <&cpg R9A07G054_CRU_CMN_RSTB>;
750 reset-names = "presetn", "cmn-rstb";
751 power-domains = <&cpg>;
752 status = "disabled";
753
754 ports {
755 #address-cells = <1>;
756 #size-cells = <0>;
757
758 port@0 {
759 reg = <0>;
760 };
761
762 port@1 {
763 #address-cells = <1>;
764 #size-cells = <0>;
765 reg = <1>;
766
767 csi2cru: endpoint@0 {
768 reg = <0>;
769 remote-endpoint = <&crucsi2>;
770 };
771 };
772 };
773 };
774
775 dsi: dsi@10850000 {
776 compatible = "renesas,r9a07g054-mipi-dsi",
777 "renesas,rzg2l-mipi-dsi";
778 reg = <0 0x10850000 0 0x20000>;
779 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
786 interrupt-names = "seq0", "seq1", "vin1", "rcv",
787 "ferr", "ppi", "debug";
788 clocks = <&cpg CPG_MOD R9A07G054_MIPI_DSI_PLLCLK>,
789 <&cpg CPG_MOD R9A07G054_MIPI_DSI_SYSCLK>,
790 <&cpg CPG_MOD R9A07G054_MIPI_DSI_ACLK>,
791 <&cpg CPG_MOD R9A07G054_MIPI_DSI_PCLK>,
792 <&cpg CPG_MOD R9A07G054_MIPI_DSI_VCLK>,
793 <&cpg CPG_MOD R9A07G054_MIPI_DSI_LPCLK>;
794 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
795 resets = <&cpg R9A07G054_MIPI_DSI_CMN_RSTB>,
796 <&cpg R9A07G054_MIPI_DSI_ARESET_N>,
797 <&cpg R9A07G054_MIPI_DSI_PRESET_N>;
798 reset-names = "rst", "arst", "prst";
799 power-domains = <&cpg>;
800 status = "disabled";
801
802 ports {
803 #address-cells = <1>;
804 #size-cells = <0>;
805
806 port@0 {
807 reg = <0>;
808 dsi0_in: endpoint {
809 remote-endpoint = <&du_out_dsi>;
810 };
811 };
812
813 port@1 {
814 reg = <1>;
815 };
816 };
817 };
818
819 vspd: vsp@10870000 {
820 compatible = "renesas,r9a07g054-vsp2",
821 "renesas,r9a07g044-vsp2";
822 reg = <0 0x10870000 0 0x10000>;
823 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
825 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
826 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
827 clock-names = "aclk", "pclk", "vclk";
828 power-domains = <&cpg>;
829 resets = <&cpg R9A07G054_LCDC_RESET_N>;
830 renesas,fcp = <&fcpvd>;
831 };
832
833 fcpvd: fcp@10880000 {
834 compatible = "renesas,r9a07g054-fcpvd",
835 "renesas,fcpv";
836 reg = <0 0x10880000 0 0x10000>;
837 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
838 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
839 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
840 clock-names = "aclk", "pclk", "vclk";
841 power-domains = <&cpg>;
842 resets = <&cpg R9A07G054_LCDC_RESET_N>;
843 };
844
845 du: display@10890000 {
846 compatible = "renesas,r9a07g054-du",
847 "renesas,r9a07g044-du";
848 reg = <0 0x10890000 0 0x10000>;
849 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
851 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
852 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
853 clock-names = "aclk", "pclk", "vclk";
854 power-domains = <&cpg>;
855 resets = <&cpg R9A07G054_LCDC_RESET_N>;
856 renesas,vsps = <&vspd 0>;
857 status = "disabled";
858
859 ports {
860 #address-cells = <1>;
861 #size-cells = <0>;
862
863 port@0 {
864 reg = <0>;
865 du_out_dsi: endpoint {
866 remote-endpoint = <&dsi0_in>;
867 };
868 };
869
870 port@1 {
871 reg = <1>;
872 };
873 };
874 };
875
876 cpg: clock-controller@11010000 {
877 compatible = "renesas,r9a07g054-cpg";
878 reg = <0 0x11010000 0 0x10000>;
879 clocks = <&extal_clk>;
880 clock-names = "extal";
881 #clock-cells = <2>;
882 #reset-cells = <1>;
883 #power-domain-cells = <0>;
884 };
885
886 sysc: system-controller@11020000 {
887 compatible = "renesas,r9a07g054-sysc";
888 reg = <0 0x11020000 0 0x10000>;
889 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
893 interrupt-names = "lpm_int", "ca55stbydone_int",
894 "cm33stbyr_int", "ca55_deny";
895 status = "disabled";
896 };
897
898 pinctrl: pinctrl@11030000 {
899 compatible = "renesas,r9a07g054-pinctrl",
900 "renesas,r9a07g044-pinctrl";
901 reg = <0 0x11030000 0 0x10000>;
902 gpio-controller;
903 #gpio-cells = <2>;
904 #interrupt-cells = <2>;
905 interrupt-parent = <&irqc>;
906 interrupt-controller;
907 gpio-ranges = <&pinctrl 0 0 392>;
908 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
909 power-domains = <&cpg>;
910 resets = <&cpg R9A07G054_GPIO_RSTN>,
911 <&cpg R9A07G054_GPIO_PORT_RESETN>,
912 <&cpg R9A07G054_GPIO_SPARE_RESETN>;
913 };
914
915 irqc: interrupt-controller@110a0000 {
916 compatible = "renesas,r9a07g054-irqc",
917 "renesas,rzg2l-irqc";
918 #interrupt-cells = <2>;
919 #address-cells = <0>;
920 interrupt-controller;
921 reg = <0 0x110a0000 0 0x10000>;
922 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
964 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
965 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
966 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
967 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
968 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
969 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
970 interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
971 "irq4", "irq5", "irq6", "irq7",
972 "tint0", "tint1", "tint2", "tint3",
973 "tint4", "tint5", "tint6", "tint7",
974 "tint8", "tint9", "tint10", "tint11",
975 "tint12", "tint13", "tint14", "tint15",
976 "tint16", "tint17", "tint18", "tint19",
977 "tint20", "tint21", "tint22", "tint23",
978 "tint24", "tint25", "tint26", "tint27",
979 "tint28", "tint29", "tint30", "tint31",
980 "bus-err", "ec7tie1-0", "ec7tie2-0",
981 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
982 "ec7tiovf-1";
983 clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
984 <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
985 clock-names = "clk", "pclk";
986 power-domains = <&cpg>;
987 resets = <&cpg R9A07G054_IA55_RESETN>;
988 };
989
990 dmac: dma-controller@11820000 {
991 compatible = "renesas,r9a07g054-dmac",
992 "renesas,rz-dmac";
993 reg = <0 0x11820000 0 0x10000>,
994 <0 0x11830000 0 0x10000>;
995 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
996 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
997 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
998 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
999 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
1000 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
1001 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
1002 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
1003 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
1004 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
1005 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
1006 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
1007 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1008 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
1009 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
1010 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
1011 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
1012 interrupt-names = "error",
1013 "ch0", "ch1", "ch2", "ch3",
1014 "ch4", "ch5", "ch6", "ch7",
1015 "ch8", "ch9", "ch10", "ch11",
1016 "ch12", "ch13", "ch14", "ch15";
1017 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
1018 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
1019 clock-names = "main", "register";
1020 power-domains = <&cpg>;
1021 resets = <&cpg R9A07G054_DMAC_ARESETN>,
1022 <&cpg R9A07G054_DMAC_RST_ASYNC>;
1023 reset-names = "arst", "rst_async";
1024 #dma-cells = <1>;
1025 dma-channels = <16>;
1026 };
1027
1028 gpu: gpu@11840000 {
1029 compatible = "renesas,r9a07g054-mali",
1030 "arm,mali-bifrost";
1031 reg = <0x0 0x11840000 0x0 0x10000>;
1032 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1036 interrupt-names = "job", "mmu", "gpu", "event";
1037 clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
1038 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
1039 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
1040 clock-names = "gpu", "bus", "bus_ace";
1041 power-domains = <&cpg>;
1042 resets = <&cpg R9A07G054_GPU_RESETN>,
1043 <&cpg R9A07G054_GPU_AXI_RESETN>,
1044 <&cpg R9A07G054_GPU_ACE_RESETN>;
1045 reset-names = "rst", "axi_rst", "ace_rst";
1046 operating-points-v2 = <&gpu_opp_table>;
1047 };
1048
1049 gic: interrupt-controller@11900000 {
1050 compatible = "arm,gic-v3";
1051 #interrupt-cells = <3>;
1052 #address-cells = <0>;
1053 interrupt-controller;
1054 reg = <0x0 0x11900000 0 0x40000>,
1055 <0x0 0x11940000 0 0x60000>;
1056 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1057 };
1058
1059 sdhi0: mmc@11c00000 {
1060 compatible = "renesas,sdhi-r9a07g054",
1061 "renesas,rzg2l-sdhi";
1062 reg = <0x0 0x11c00000 0 0x10000>;
1063 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1064 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
1066 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
1067 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
1068 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
1069 clock-names = "core", "clkh", "cd", "aclk";
1070 resets = <&cpg R9A07G054_SDHI0_IXRST>;
1071 power-domains = <&cpg>;
1072 status = "disabled";
1073 };
1074
1075 sdhi1: mmc@11c10000 {
1076 compatible = "renesas,sdhi-r9a07g054",
1077 "renesas,rzg2l-sdhi";
1078 reg = <0x0 0x11c10000 0 0x10000>;
1079 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1080 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
1082 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
1083 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
1084 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
1085 clock-names = "core", "clkh", "cd", "aclk";
1086 resets = <&cpg R9A07G054_SDHI1_IXRST>;
1087 power-domains = <&cpg>;
1088 status = "disabled";
1089 };
1090
1091 eth0: ethernet@11c20000 {
1092 compatible = "renesas,r9a07g054-gbeth",
1093 "renesas,rzg2l-gbeth";
1094 reg = <0 0x11c20000 0 0x10000>;
1095 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1096 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1098 interrupt-names = "mux", "fil", "arp_ns";
1099 phy-mode = "rgmii";
1100 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
1101 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
1102 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1103 clock-names = "axi", "chi", "refclk";
1104 resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
1105 power-domains = <&cpg>;
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1108 status = "disabled";
1109 };
1110
1111 eth1: ethernet@11c30000 {
1112 compatible = "renesas,r9a07g054-gbeth",
1113 "renesas,rzg2l-gbeth";
1114 reg = <0 0x11c30000 0 0x10000>;
1115 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1116 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1117 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1118 interrupt-names = "mux", "fil", "arp_ns";
1119 phy-mode = "rgmii";
1120 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
1121 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
1122 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1123 clock-names = "axi", "chi", "refclk";
1124 resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
1125 power-domains = <&cpg>;
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1128 status = "disabled";
1129 };
1130
1131 phyrst: usbphy-ctrl@11c40000 {
1132 compatible = "renesas,r9a07g054-usbphy-ctrl",
1133 "renesas,rzg2l-usbphy-ctrl";
1134 reg = <0 0x11c40000 0 0x10000>;
1135 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
1136 resets = <&cpg R9A07G054_USB_PRESETN>;
1137 power-domains = <&cpg>;
1138 #reset-cells = <1>;
1139 status = "disabled";
1140 };
1141
1142 ohci0: usb@11c50000 {
1143 compatible = "generic-ohci";
1144 reg = <0 0x11c50000 0 0x100>;
1145 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1146 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1147 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1148 resets = <&phyrst 0>,
1149 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1150 phys = <&usb2_phy0 1>;
1151 phy-names = "usb";
1152 power-domains = <&cpg>;
1153 status = "disabled";
1154 };
1155
1156 ohci1: usb@11c70000 {
1157 compatible = "generic-ohci";
1158 reg = <0 0x11c70000 0 0x100>;
1159 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1161 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1162 resets = <&phyrst 1>,
1163 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1164 phys = <&usb2_phy1 1>;
1165 phy-names = "usb";
1166 power-domains = <&cpg>;
1167 status = "disabled";
1168 };
1169
1170 ehci0: usb@11c50100 {
1171 compatible = "generic-ehci";
1172 reg = <0 0x11c50100 0 0x100>;
1173 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1174 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1175 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1176 resets = <&phyrst 0>,
1177 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1178 phys = <&usb2_phy0 2>;
1179 phy-names = "usb";
1180 companion = <&ohci0>;
1181 power-domains = <&cpg>;
1182 status = "disabled";
1183 };
1184
1185 ehci1: usb@11c70100 {
1186 compatible = "generic-ehci";
1187 reg = <0 0x11c70100 0 0x100>;
1188 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1189 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1190 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1191 resets = <&phyrst 1>,
1192 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1193 phys = <&usb2_phy1 2>;
1194 phy-names = "usb";
1195 companion = <&ohci1>;
1196 power-domains = <&cpg>;
1197 status = "disabled";
1198 };
1199
1200 usb2_phy0: usb-phy@11c50200 {
1201 compatible = "renesas,usb2-phy-r9a07g054",
1202 "renesas,rzg2l-usb2-phy";
1203 reg = <0 0x11c50200 0 0x700>;
1204 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1206 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1207 resets = <&phyrst 0>;
1208 #phy-cells = <1>;
1209 power-domains = <&cpg>;
1210 status = "disabled";
1211 };
1212
1213 usb2_phy1: usb-phy@11c70200 {
1214 compatible = "renesas,usb2-phy-r9a07g054",
1215 "renesas,rzg2l-usb2-phy";
1216 reg = <0 0x11c70200 0 0x700>;
1217 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1218 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1219 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1220 resets = <&phyrst 1>;
1221 #phy-cells = <1>;
1222 power-domains = <&cpg>;
1223 status = "disabled";
1224 };
1225
1226 hsusb: usb@11c60000 {
1227 compatible = "renesas,usbhs-r9a07g054",
1228 "renesas,rzg2l-usbhs";
1229 reg = <0 0x11c60000 0 0x10000>;
1230 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
1231 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1234 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1235 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
1236 resets = <&phyrst 0>,
1237 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
1238 renesas,buswait = <7>;
1239 phys = <&usb2_phy0 3>;
1240 phy-names = "usb";
1241 power-domains = <&cpg>;
1242 status = "disabled";
1243 };
1244
1245 wdt0: watchdog@12800800 {
1246 compatible = "renesas,r9a07g054-wdt",
1247 "renesas,rzg2l-wdt";
1248 reg = <0 0x12800800 0 0x400>;
1249 clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
1250 <&cpg CPG_MOD R9A07G054_WDT0_CLK>;
1251 clock-names = "pclk", "oscclk";
1252 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1254 interrupt-names = "wdt", "perrout";
1255 resets = <&cpg R9A07G054_WDT0_PRESETN>;
1256 power-domains = <&cpg>;
1257 status = "disabled";
1258 };
1259
1260 wdt1: watchdog@12800c00 {
1261 compatible = "renesas,r9a07g054-wdt",
1262 "renesas,rzg2l-wdt";
1263 reg = <0 0x12800C00 0 0x400>;
1264 clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
1265 <&cpg CPG_MOD R9A07G054_WDT1_CLK>;
1266 clock-names = "pclk", "oscclk";
1267 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1269 interrupt-names = "wdt", "perrout";
1270 resets = <&cpg R9A07G054_WDT1_PRESETN>;
1271 power-domains = <&cpg>;
1272 status = "disabled";
1273 };
1274
1275 ostm0: timer@12801000 {
1276 compatible = "renesas,r9a07g054-ostm",
1277 "renesas,ostm";
1278 reg = <0x0 0x12801000 0x0 0x400>;
1279 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
1280 clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
1281 resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
1282 power-domains = <&cpg>;
1283 status = "disabled";
1284 };
1285
1286 ostm1: timer@12801400 {
1287 compatible = "renesas,r9a07g054-ostm",
1288 "renesas,ostm";
1289 reg = <0x0 0x12801400 0x0 0x400>;
1290 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
1291 clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
1292 resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
1293 power-domains = <&cpg>;
1294 status = "disabled";
1295 };
1296
1297 ostm2: timer@12801800 {
1298 compatible = "renesas,r9a07g054-ostm",
1299 "renesas,ostm";
1300 reg = <0x0 0x12801800 0x0 0x400>;
1301 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
1302 clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
1303 resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
1304 power-domains = <&cpg>;
1305 status = "disabled";
1306 };
1307 };
1308
1309 thermal-zones {
1310 cpu-thermal {
1311 polling-delay-passive = <250>;
1312 polling-delay = <1000>;
1313 thermal-sensors = <&tsu 0>;
1314 sustainable-power = <717>;
1315
1316 cooling-maps {
1317 map0 {
1318 trip = <&target>;
1319 cooling-device = <&cpu0 0 2>;
1320 contribution = <1024>;
1321 };
1322 };
1323
1324 trips {
1325 sensor_crit: sensor-crit {
1326 temperature = <125000>;
1327 hysteresis = <1000>;
1328 type = "critical";
1329 };
1330
1331 target: trip-point {
1332 temperature = <100000>;
1333 hysteresis = <1000>;
1334 type = "passive";
1335 };
1336 };
1337 };
1338 };
1339
1340 timer {
1341 compatible = "arm,armv8-timer";
1342 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1343 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1344 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1345 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
1346 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
1347 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
1348 "hyp-virt";
1349 };
1350 };
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