1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /*
3 * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11 / {
12 aliases {
13 serial1 = &scif2;
14 i2c3 = &i2c3;
15 };
16
17 osc1: cec-clock {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <12000000>;
21 };
22
23 hdmi-out {
24 compatible = "hdmi-connector";
25 type = "d";
26
27 port {
28 hdmi_con_out: endpoint {
29 remote-endpoint = <&adv7535_out>;
30 };
31 };
32 };
33 };
34
35 &cpu_dai {
36 sound-dai = <&ssi0>;
37 };
38
39 &dsi {
40 status = "okay";
41
42 ports {
43 port@1 {
44 dsi0_out: endpoint {
45 data-lanes = <1 2 3 4>;
46 remote-endpoint = <&adv7535_in>;
47 };
48 };
49 };
50 };
51
52 &du {
53 status = "okay";
54 };
55
56 &i2c1 {
57 adv7535: hdmi@3d {
58 compatible = "adi,adv7535";
59 reg = <0x3d>;
60
61 interrupt-parent = <&pinctrl>;
62 interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>;
63 clocks = <&osc1>;
64 clock-names = "cec";
65 avdd-supply = <®_1p8v>;
66 dvdd-supply = <®_1p8v>;
67 pvdd-supply = <®_1p8v>;
68 a2vdd-supply = <®_1p8v>;
69 v3p3-supply = <®_3p3v>;
70 v1p2-supply = <®_1p8v>;
71
72 adi,dsi-lanes = <4>;
73
74 ports {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 port@0 {
79 reg = <0>;
80 adv7535_in: endpoint {
81 remote-endpoint = <&dsi0_out>;
82 };
83 };
84
85 port@1 {
86 reg = <1>;
87 adv7535_out: endpoint {
88 remote-endpoint = <&hdmi_con_out>;
89 };
90 };
91 };
92 };
93 };
94
95 &i2c3 {
96 pinctrl-0 = <&i2c3_pins>;
97 pinctrl-names = "default";
98 clock-frequency = <400000>;
99
100 status = "okay";
101
102 wm8978: codec@1a {
103 compatible = "wlf,wm8978";
104 #sound-dai-cells = <0>;
105 reg = <0x1a>;
106 };
107
108 versa3: clock-generator@68 {
109 compatible = "renesas,5p35023";
110 reg = <0x68>;
111 #clock-cells = <1>;
112 clocks = <&x1>;
113
114 renesas,settings = [
115 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
116 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
117 80 b0 45 c4 95
118 ];
119
120 assigned-clocks = <&versa3 0>, <&versa3 1>,
121 <&versa3 2>, <&versa3 3>,
122 <&versa3 4>, <&versa3 5>;
123 assigned-clock-rates = <24000000>, <11289600>,
124 <11289600>, <12000000>,
125 <25000000>, <12288000>;
126 };
127 };
128
129 #if PMOD_MTU3
130 &mtu3 {
131 pinctrl-0 = <&mtu3_pins>;
132 pinctrl-names = "default";
133
134 status = "okay";
135 };
136
137 #if MTU3_COUNTER_Z_PHASE_SIGNAL
138 /* SDHI cd pin is muxed with counter Z phase signal */
139 &sdhi1 {
140 status = "disabled";
141 };
142 #endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
143
144 &spi1 {
145 status = "disabled";
146 };
147 #endif /* PMOD_MTU3 */
148
149 /*
150 * To enable SCIF2 (SER0) on PMOD1 (CN7)
151 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
152 * SW2 should be at position 2->3 so that SER0_TX line is activated
153 * SW3 should be at position 2->3 so that SER0_RX line is activated
154 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
155 */
156 #if PMOD1_SER0
157 &scif2 {
158 pinctrl-0 = <&scif2_pins>;
159 pinctrl-names = "default";
160
161 uart-has-rtscts;
162 status = "okay";
163 };
164 #endif
165
166 &ssi0 {
167 pinctrl-0 = <&ssi0_pins>;
168 pinctrl-names = "default";
169
170 status = "okay";
171 };
172
173 &vccq_sdhi1 {
174 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
175 };
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