1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /*
3 * Device Tree Source for the RZ/G2UL SMARC SOM common parts
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11
12 / {
13 aliases {
14 ethernet0 = ð0;
15 ethernet1 = ð1;
16 };
17
18 chosen {
19 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
20 };
21
22 memory@48000000 {
23 device_type = "memory";
24 /* first 128MB is reserved for secure area. */
25 reg = <0x0 0x48000000 0x0 0x38000000>;
26 };
27
28 reg_1p8v: regulator-1p8v {
29 compatible = "regulator-fixed";
30 regulator-name = "fixed-1.8V";
31 regulator-min-microvolt = <1800000>;
32 regulator-max-microvolt = <1800000>;
33 regulator-boot-on;
34 regulator-always-on;
35 };
36
37 reg_3p3v: regulator-3p3v {
38 compatible = "regulator-fixed";
39 regulator-name = "fixed-3.3V";
40 regulator-min-microvolt = <3300000>;
41 regulator-max-microvolt = <3300000>;
42 regulator-boot-on;
43 regulator-always-on;
44 };
45
46 #if !(SW_SW0_DEV_SEL)
47 vccq_sdhi0: regulator-vccq-sdhi0 {
48 compatible = "regulator-gpio";
49
50 regulator-name = "SDHI0 VccQ";
51 regulator-min-microvolt = <1800000>;
52 regulator-max-microvolt = <3300000>;
53 states = <3300000 1>, <1800000 0>;
54 regulator-boot-on;
55 gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>;
56 regulator-always-on;
57 };
58 #endif
59 };
60
61 #if (SW_SW0_DEV_SEL)
62 &adc {
63 pinctrl-0 = <&adc_pins>;
64 pinctrl-names = "default";
65 status = "okay";
66 };
67 #endif
68
69 #if (!SW_ET0_EN_N)
70 ð0 {
71 pinctrl-0 = <ð0_pins>;
72 pinctrl-names = "default";
73 phy-handle = <&phy0>;
74 phy-mode = "rgmii-id";
75 status = "okay";
76
77 phy0: ethernet-phy@7 {
78 compatible = "ethernet-phy-id0022.1640",
79 "ethernet-phy-ieee802.3-c22";
80 reg = <7>;
81 interrupt-parent = <&irqc>;
82 interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
83 rxc-skew-psec = <2400>;
84 txc-skew-psec = <2400>;
85 rxdv-skew-psec = <0>;
86 txen-skew-psec = <0>;
87 rxd0-skew-psec = <0>;
88 rxd1-skew-psec = <0>;
89 rxd2-skew-psec = <0>;
90 rxd3-skew-psec = <0>;
91 txd0-skew-psec = <0>;
92 txd1-skew-psec = <0>;
93 txd2-skew-psec = <0>;
94 txd3-skew-psec = <0>;
95 };
96 };
97 #endif
98
99 ð1 {
100 pinctrl-0 = <ð1_pins>;
101 pinctrl-names = "default";
102 phy-handle = <&phy1>;
103 phy-mode = "rgmii-id";
104 status = "okay";
105
106 phy1: ethernet-phy@7 {
107 compatible = "ethernet-phy-id0022.1640",
108 "ethernet-phy-ieee802.3-c22";
109 reg = <7>;
110 interrupt-parent = <&irqc>;
111 interrupts = <RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>;
112 rxc-skew-psec = <2400>;
113 txc-skew-psec = <2400>;
114 rxdv-skew-psec = <0>;
115 txen-skew-psec = <0>;
116 rxd0-skew-psec = <0>;
117 rxd1-skew-psec = <0>;
118 rxd2-skew-psec = <0>;
119 rxd3-skew-psec = <0>;
120 txd0-skew-psec = <0>;
121 txd1-skew-psec = <0>;
122 txd2-skew-psec = <0>;
123 txd3-skew-psec = <0>;
124 };
125 };
126
127 &extal_clk {
128 clock-frequency = <24000000>;
129 };
130
131 &ostm1 {
132 status = "okay";
133 };
134
135 &ostm2 {
136 status = "okay";
137 };
138
139 &pinctrl {
140 adc_pins: adc {
141 pinmux = <RZG2L_PORT_PINMUX(6, 2, 1)>; /* ADC_TRG */
142 };
143
144 eth0_pins: eth0 {
145 pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
146 <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
147 <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
148 <RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */
149 <RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
150 <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
151 <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
152 <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
153 <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
154 <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
155 <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
156 <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
157 <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
158 <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
159 <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
160 <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
161 };
162
163 eth1_pins: eth1 {
164 pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
165 <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
166 <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
167 <RZG2L_PORT_PINMUX(7, 0, 1)>, /* ET1_TXC */
168 <RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
169 <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
170 <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
171 <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
172 <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
173 <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
174 <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
175 <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
176 <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
177 <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
178 <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
179 <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
180 };
181
182 sdhi0_emmc_pins: sd0emmc {
183 sd0_emmc_data {
184 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
185 "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
186 power-source = <1800>;
187 };
188
189 sd0_emmc_ctrl {
190 pins = "SD0_CLK", "SD0_CMD";
191 power-source = <1800>;
192 };
193
194 sd0_emmc_rst {
195 pins = "SD0_RST#";
196 power-source = <1800>;
197 };
198 };
199
200 sdhi0_pins: sd0 {
201 sd0_data {
202 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
203 power-source = <3300>;
204 };
205
206 sd0_ctrl {
207 pins = "SD0_CLK", "SD0_CMD";
208 power-source = <3300>;
209 };
210
211 sd0_mux {
212 pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
213 };
214 };
215
216 sdhi0_pins_uhs: sd0_uhs {
217 sd0_data_uhs {
218 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
219 power-source = <1800>;
220 };
221
222 sd0_ctrl_uhs {
223 pins = "SD0_CLK", "SD0_CMD";
224 power-source = <1800>;
225 };
226
227 sd0_mux_uhs {
228 pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
229 };
230 };
231 };
232
233 #if (SW_SW0_DEV_SEL)
234 &sdhi0 {
235 pinctrl-0 = <&sdhi0_emmc_pins>;
236 pinctrl-1 = <&sdhi0_emmc_pins>;
237 pinctrl-names = "default", "state_uhs";
238
239 vmmc-supply = <®_3p3v>;
240 vqmmc-supply = <®_1p8v>;
241 bus-width = <8>;
242 mmc-hs200-1_8v;
243 non-removable;
244 fixed-emmc-driver-type = <1>;
245 status = "okay";
246 };
247 #else
248 &sdhi0 {
249 pinctrl-0 = <&sdhi0_pins>;
250 pinctrl-1 = <&sdhi0_pins_uhs>;
251 pinctrl-names = "default", "state_uhs";
252
253 vmmc-supply = <®_3p3v>;
254 vqmmc-supply = <&vccq_sdhi0>;
255 bus-width = <4>;
256 sd-uhs-sdr50;
257 sd-uhs-sdr104;
258 status = "okay";
259 };
260 #endif
261
262 &wdt0 {
263 status = "okay";
264 timeout-sec = <60>;
265 };
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