1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
14
15 / {
16 compatible = "rockchip,rk3328";
17
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 gpio0 = &gpio0;
24 gpio1 = &gpio1;
25 gpio2 = &gpio2;
26 gpio3 = &gpio3;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 serial2 = &uart2;
30 i2c0 = &i2c0;
31 i2c1 = &i2c1;
32 i2c2 = &i2c2;
33 i2c3 = &i2c3;
34 };
35
36 cpus {
37 #address-cells = <2>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a53";
43 reg = <0x0 0x0>;
44 clocks = <&cru ARMCLK>;
45 #cooling-cells = <2>;
46 cpu-idle-states = <&CPU_SLEEP>;
47 dynamic-power-coefficient = <120>;
48 enable-method = "psci";
49 operating-points-v2 = <&cpu0_opp_table>;
50 i-cache-size = <0x8000>;
51 i-cache-line-size = <64>;
52 i-cache-sets = <256>;
53 d-cache-size = <0x8000>;
54 d-cache-line-size = <64>;
55 d-cache-sets = <128>;
56 next-level-cache = <&l2_cache>;
57 };
58
59 cpu1: cpu@1 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x0 0x1>;
63 clocks = <&cru ARMCLK>;
64 #cooling-cells = <2>;
65 cpu-idle-states = <&CPU_SLEEP>;
66 dynamic-power-coefficient = <120>;
67 enable-method = "psci";
68 operating-points-v2 = <&cpu0_opp_table>;
69 i-cache-size = <0x8000>;
70 i-cache-line-size = <64>;
71 i-cache-sets = <256>;
72 d-cache-size = <0x8000>;
73 d-cache-line-size = <64>;
74 d-cache-sets = <128>;
75 next-level-cache = <&l2_cache>;
76 };
77
78 cpu2: cpu@2 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a53";
81 reg = <0x0 0x2>;
82 clocks = <&cru ARMCLK>;
83 #cooling-cells = <2>;
84 cpu-idle-states = <&CPU_SLEEP>;
85 dynamic-power-coefficient = <120>;
86 enable-method = "psci";
87 operating-points-v2 = <&cpu0_opp_table>;
88 i-cache-size = <0x8000>;
89 i-cache-line-size = <64>;
90 i-cache-sets = <256>;
91 d-cache-size = <0x8000>;
92 d-cache-line-size = <64>;
93 d-cache-sets = <128>;
94 next-level-cache = <&l2_cache>;
95 };
96
97 cpu3: cpu@3 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a53";
100 reg = <0x0 0x3>;
101 clocks = <&cru ARMCLK>;
102 #cooling-cells = <2>;
103 cpu-idle-states = <&CPU_SLEEP>;
104 dynamic-power-coefficient = <120>;
105 enable-method = "psci";
106 operating-points-v2 = <&cpu0_opp_table>;
107 i-cache-size = <0x8000>;
108 i-cache-line-size = <64>;
109 i-cache-sets = <256>;
110 d-cache-size = <0x8000>;
111 d-cache-line-size = <64>;
112 d-cache-sets = <128>;
113 next-level-cache = <&l2_cache>;
114 };
115
116 idle-states {
117 entry-method = "psci";
118
119 CPU_SLEEP: cpu-sleep {
120 compatible = "arm,idle-state";
121 local-timer-stop;
122 arm,psci-suspend-param = <0x0010000>;
123 entry-latency-us = <120>;
124 exit-latency-us = <250>;
125 min-residency-us = <900>;
126 };
127 };
128
129 l2_cache: l2-cache {
130 compatible = "cache";
131 cache-level = <2>;
132 cache-unified;
133 cache-size = <0x40000>;
134 cache-line-size = <64>;
135 cache-sets = <256>;
136 };
137 };
138
139 cpu0_opp_table: opp-table-0 {
140 compatible = "operating-points-v2";
141 opp-shared;
142
143 opp-408000000 {
144 opp-hz = /bits/ 64 <408000000>;
145 opp-microvolt = <950000>;
146 clock-latency-ns = <40000>;
147 opp-suspend;
148 };
149 opp-600000000 {
150 opp-hz = /bits/ 64 <600000000>;
151 opp-microvolt = <950000>;
152 clock-latency-ns = <40000>;
153 };
154 opp-816000000 {
155 opp-hz = /bits/ 64 <816000000>;
156 opp-microvolt = <1000000>;
157 clock-latency-ns = <40000>;
158 };
159 opp-1008000000 {
160 opp-hz = /bits/ 64 <1008000000>;
161 opp-microvolt = <1100000>;
162 clock-latency-ns = <40000>;
163 };
164 opp-1200000000 {
165 opp-hz = /bits/ 64 <1200000000>;
166 opp-microvolt = <1225000>;
167 clock-latency-ns = <40000>;
168 };
169 opp-1296000000 {
170 opp-hz = /bits/ 64 <1296000000>;
171 opp-microvolt = <1300000>;
172 clock-latency-ns = <40000>;
173 };
174 };
175
176 analog_sound: analog-sound {
177 compatible = "simple-audio-card";
178 simple-audio-card,format = "i2s";
179 simple-audio-card,mclk-fs = <256>;
180 simple-audio-card,name = "Analog";
181 status = "disabled";
182
183 simple-audio-card,cpu {
184 sound-dai = <&i2s1>;
185 };
186
187 simple-audio-card,codec {
188 sound-dai = <&codec>;
189 };
190 };
191
192 arm-pmu {
193 compatible = "arm,cortex-a53-pmu";
194 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
198 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
199 };
200
201 display_subsystem: display-subsystem {
202 compatible = "rockchip,display-subsystem";
203 ports = <&vop_out>;
204 };
205
206 hdmi_sound: hdmi-sound {
207 compatible = "simple-audio-card";
208 simple-audio-card,format = "i2s";
209 simple-audio-card,mclk-fs = <128>;
210 simple-audio-card,name = "HDMI";
211 status = "disabled";
212
213 simple-audio-card,cpu {
214 sound-dai = <&i2s0>;
215 };
216
217 simple-audio-card,codec {
218 sound-dai = <&hdmi>;
219 };
220 };
221
222 psci {
223 compatible = "arm,psci-1.0", "arm,psci-0.2";
224 method = "smc";
225 };
226
227 timer {
228 compatible = "arm,armv8-timer";
229 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
230 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
231 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
232 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
233 };
234
235 xin24m: xin24m {
236 compatible = "fixed-clock";
237 #clock-cells = <0>;
238 clock-frequency = <24000000>;
239 clock-output-names = "xin24m";
240 };
241
242 i2s0: i2s@ff000000 {
243 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
244 reg = <0x0 0xff000000 0x0 0x1000>;
245 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
247 clock-names = "i2s_clk", "i2s_hclk";
248 dmas = <&dmac 11>, <&dmac 12>;
249 dma-names = "tx", "rx";
250 #sound-dai-cells = <0>;
251 status = "disabled";
252 };
253
254 i2s1: i2s@ff010000 {
255 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
256 reg = <0x0 0xff010000 0x0 0x1000>;
257 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
259 clock-names = "i2s_clk", "i2s_hclk";
260 dmas = <&dmac 14>, <&dmac 15>;
261 dma-names = "tx", "rx";
262 #sound-dai-cells = <0>;
263 status = "disabled";
264 };
265
266 i2s2: i2s@ff020000 {
267 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
268 reg = <0x0 0xff020000 0x0 0x1000>;
269 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
271 clock-names = "i2s_clk", "i2s_hclk";
272 dmas = <&dmac 0>, <&dmac 1>;
273 dma-names = "tx", "rx";
274 #sound-dai-cells = <0>;
275 status = "disabled";
276 };
277
278 spdif: spdif@ff030000 {
279 compatible = "rockchip,rk3328-spdif";
280 reg = <0x0 0xff030000 0x0 0x1000>;
281 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
283 clock-names = "mclk", "hclk";
284 dmas = <&dmac 10>;
285 dma-names = "tx";
286 pinctrl-names = "default";
287 pinctrl-0 = <&spdifm2_tx>;
288 #sound-dai-cells = <0>;
289 status = "disabled";
290 };
291
292 pdm: pdm@ff040000 {
293 compatible = "rockchip,pdm";
294 reg = <0x0 0xff040000 0x0 0x1000>;
295 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
296 clock-names = "pdm_clk", "pdm_hclk";
297 dmas = <&dmac 16>;
298 dma-names = "rx";
299 pinctrl-names = "default", "sleep";
300 pinctrl-0 = <&pdmm0_clk
301 &pdmm0_sdi0
302 &pdmm0_sdi1
303 &pdmm0_sdi2
304 &pdmm0_sdi3>;
305 pinctrl-1 = <&pdmm0_clk_sleep
306 &pdmm0_sdi0_sleep
307 &pdmm0_sdi1_sleep
308 &pdmm0_sdi2_sleep
309 &pdmm0_sdi3_sleep>;
310 status = "disabled";
311 };
312
313 grf: syscon@ff100000 {
314 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
315 reg = <0x0 0xff100000 0x0 0x1000>;
316
317 io_domains: io-domains {
318 compatible = "rockchip,rk3328-io-voltage-domain";
319 status = "disabled";
320 };
321
322 grf_gpio: gpio {
323 compatible = "rockchip,rk3328-grf-gpio";
324 gpio-controller;
325 #gpio-cells = <2>;
326 };
327
328 power: power-controller {
329 compatible = "rockchip,rk3328-power-controller";
330 #power-domain-cells = <1>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333
334 power-domain@RK3328_PD_HEVC {
335 reg = <RK3328_PD_HEVC>;
336 #power-domain-cells = <0>;
337 };
338 power-domain@RK3328_PD_VIDEO {
339 reg = <RK3328_PD_VIDEO>;
340 clocks = <&cru ACLK_RKVDEC>,
341 <&cru HCLK_RKVDEC>,
342 <&cru SCLK_VDEC_CABAC>,
343 <&cru SCLK_VDEC_CORE>;
344 #power-domain-cells = <0>;
345 };
346 power-domain@RK3328_PD_VPU {
347 reg = <RK3328_PD_VPU>;
348 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
349 #power-domain-cells = <0>;
350 };
351 };
352
353 reboot-mode {
354 compatible = "syscon-reboot-mode";
355 offset = <0x5c8>;
356 mode-normal = <BOOT_NORMAL>;
357 mode-recovery = <BOOT_RECOVERY>;
358 mode-bootloader = <BOOT_FASTBOOT>;
359 mode-loader = <BOOT_BL_DOWNLOAD>;
360 };
361 };
362
363 uart0: serial@ff110000 {
364 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
365 reg = <0x0 0xff110000 0x0 0x100>;
366 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
368 clock-names = "baudclk", "apb_pclk";
369 dmas = <&dmac 2>, <&dmac 3>;
370 dma-names = "tx", "rx";
371 pinctrl-names = "default";
372 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
373 reg-io-width = <4>;
374 reg-shift = <2>;
375 status = "disabled";
376 };
377
378 uart1: serial@ff120000 {
379 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
380 reg = <0x0 0xff120000 0x0 0x100>;
381 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
383 clock-names = "baudclk", "apb_pclk";
384 dmas = <&dmac 4>, <&dmac 5>;
385 dma-names = "tx", "rx";
386 pinctrl-names = "default";
387 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
388 reg-io-width = <4>;
389 reg-shift = <2>;
390 status = "disabled";
391 };
392
393 uart2: serial@ff130000 {
394 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
395 reg = <0x0 0xff130000 0x0 0x100>;
396 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
398 clock-names = "baudclk", "apb_pclk";
399 dmas = <&dmac 6>, <&dmac 7>;
400 dma-names = "tx", "rx";
401 pinctrl-names = "default";
402 pinctrl-0 = <&uart2m1_xfer>;
403 reg-io-width = <4>;
404 reg-shift = <2>;
405 status = "disabled";
406 };
407
408 i2c0: i2c@ff150000 {
409 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
410 reg = <0x0 0xff150000 0x0 0x1000>;
411 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
412 #address-cells = <1>;
413 #size-cells = <0>;
414 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
415 clock-names = "i2c", "pclk";
416 pinctrl-names = "default";
417 pinctrl-0 = <&i2c0_xfer>;
418 status = "disabled";
419 };
420
421 i2c1: i2c@ff160000 {
422 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
423 reg = <0x0 0xff160000 0x0 0x1000>;
424 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
425 #address-cells = <1>;
426 #size-cells = <0>;
427 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
428 clock-names = "i2c", "pclk";
429 pinctrl-names = "default";
430 pinctrl-0 = <&i2c1_xfer>;
431 status = "disabled";
432 };
433
434 i2c2: i2c@ff170000 {
435 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
436 reg = <0x0 0xff170000 0x0 0x1000>;
437 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
438 #address-cells = <1>;
439 #size-cells = <0>;
440 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
441 clock-names = "i2c", "pclk";
442 pinctrl-names = "default";
443 pinctrl-0 = <&i2c2_xfer>;
444 status = "disabled";
445 };
446
447 i2c3: i2c@ff180000 {
448 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
449 reg = <0x0 0xff180000 0x0 0x1000>;
450 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
451 #address-cells = <1>;
452 #size-cells = <0>;
453 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
454 clock-names = "i2c", "pclk";
455 pinctrl-names = "default";
456 pinctrl-0 = <&i2c3_xfer>;
457 status = "disabled";
458 };
459
460 spi0: spi@ff190000 {
461 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
462 reg = <0x0 0xff190000 0x0 0x1000>;
463 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
467 clock-names = "spiclk", "apb_pclk";
468 dmas = <&dmac 8>, <&dmac 9>;
469 dma-names = "tx", "rx";
470 pinctrl-names = "default";
471 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
472 status = "disabled";
473 };
474
475 wdt: watchdog@ff1a0000 {
476 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
477 reg = <0x0 0xff1a0000 0x0 0x100>;
478 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cru PCLK_WDT>;
480 };
481
482 pwm0: pwm@ff1b0000 {
483 compatible = "rockchip,rk3328-pwm";
484 reg = <0x0 0xff1b0000 0x0 0x10>;
485 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
486 clock-names = "pwm", "pclk";
487 pinctrl-names = "default";
488 pinctrl-0 = <&pwm0_pin>;
489 #pwm-cells = <3>;
490 status = "disabled";
491 };
492
493 pwm1: pwm@ff1b0010 {
494 compatible = "rockchip,rk3328-pwm";
495 reg = <0x0 0xff1b0010 0x0 0x10>;
496 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
497 clock-names = "pwm", "pclk";
498 pinctrl-names = "default";
499 pinctrl-0 = <&pwm1_pin>;
500 #pwm-cells = <3>;
501 status = "disabled";
502 };
503
504 pwm2: pwm@ff1b0020 {
505 compatible = "rockchip,rk3328-pwm";
506 reg = <0x0 0xff1b0020 0x0 0x10>;
507 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
508 clock-names = "pwm", "pclk";
509 pinctrl-names = "default";
510 pinctrl-0 = <&pwm2_pin>;
511 #pwm-cells = <3>;
512 status = "disabled";
513 };
514
515 pwm3: pwm@ff1b0030 {
516 compatible = "rockchip,rk3328-pwm";
517 reg = <0x0 0xff1b0030 0x0 0x10>;
518 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
519 clock-names = "pwm", "pclk";
520 pinctrl-names = "default";
521 pinctrl-0 = <&pwmir_pin>;
522 #pwm-cells = <3>;
523 status = "disabled";
524 };
525
526 dmac: dma-controller@ff1f0000 {
527 compatible = "arm,pl330", "arm,primecell";
528 reg = <0x0 0xff1f0000 0x0 0x4000>;
529 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
531 arm,pl330-periph-burst;
532 clocks = <&cru ACLK_DMAC>;
533 clock-names = "apb_pclk";
534 #dma-cells = <1>;
535 };
536
537 thermal-zones {
538 soc_thermal: soc-thermal {
539 polling-delay-passive = <20>;
540 polling-delay = <1000>;
541 sustainable-power = <1000>;
542
543 thermal-sensors = <&tsadc 0>;
544
545 trips {
546 threshold: trip-point0 {
547 temperature = <70000>;
548 hysteresis = <2000>;
549 type = "passive";
550 };
551 target: trip-point1 {
552 temperature = <85000>;
553 hysteresis = <2000>;
554 type = "passive";
555 };
556 soc_crit: soc-crit {
557 temperature = <95000>;
558 hysteresis = <2000>;
559 type = "critical";
560 };
561 };
562
563 cooling-maps {
564 map0 {
565 trip = <&target>;
566 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
567 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
568 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
569 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
570 contribution = <4096>;
571 };
572 };
573 };
574
575 };
576
577 tsadc: tsadc@ff250000 {
578 compatible = "rockchip,rk3328-tsadc";
579 reg = <0x0 0xff250000 0x0 0x100>;
580 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
581 assigned-clocks = <&cru SCLK_TSADC>;
582 assigned-clock-rates = <50000>;
583 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
584 clock-names = "tsadc", "apb_pclk";
585 pinctrl-names = "init", "default", "sleep";
586 pinctrl-0 = <&otp_pin>;
587 pinctrl-1 = <&otp_out>;
588 pinctrl-2 = <&otp_pin>;
589 resets = <&cru SRST_TSADC>;
590 reset-names = "tsadc-apb";
591 rockchip,grf = <&grf>;
592 rockchip,hw-tshut-temp = <100000>;
593 #thermal-sensor-cells = <1>;
594 status = "disabled";
595 };
596
597 efuse: efuse@ff260000 {
598 compatible = "rockchip,rk3328-efuse";
599 reg = <0x0 0xff260000 0x0 0x50>;
600 #address-cells = <1>;
601 #size-cells = <1>;
602 clocks = <&cru SCLK_EFUSE>;
603 clock-names = "pclk_efuse";
604 rockchip,efuse-size = <0x20>;
605
606 /* Data cells */
607 efuse_id: id@7 {
608 reg = <0x07 0x10>;
609 };
610 cpu_leakage: cpu-leakage@17 {
611 reg = <0x17 0x1>;
612 };
613 logic_leakage: logic-leakage@19 {
614 reg = <0x19 0x1>;
615 };
616 efuse_cpu_version: cpu-version@1a {
617 reg = <0x1a 0x1>;
618 bits = <3 3>;
619 };
620 };
621
622 saradc: adc@ff280000 {
623 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
624 reg = <0x0 0xff280000 0x0 0x100>;
625 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
626 #io-channel-cells = <1>;
627 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
628 clock-names = "saradc", "apb_pclk";
629 resets = <&cru SRST_SARADC_P>;
630 reset-names = "saradc-apb";
631 status = "disabled";
632 };
633
634 gpu: gpu@ff300000 {
635 compatible = "rockchip,rk3328-mali", "arm,mali-450";
636 reg = <0x0 0xff300000 0x0 0x30000>;
637 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
644 interrupt-names = "gp",
645 "gpmmu",
646 "pp",
647 "pp0",
648 "ppmmu0",
649 "pp1",
650 "ppmmu1";
651 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
652 clock-names = "bus", "core";
653 resets = <&cru SRST_GPU_A>;
654 };
655
656 h265e_mmu: iommu@ff330200 {
657 compatible = "rockchip,iommu";
658 reg = <0x0 0xff330200 0 0x100>;
659 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
661 clock-names = "aclk", "iface";
662 #iommu-cells = <0>;
663 status = "disabled";
664 };
665
666 vepu_mmu: iommu@ff340800 {
667 compatible = "rockchip,iommu";
668 reg = <0x0 0xff340800 0x0 0x40>;
669 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
671 clock-names = "aclk", "iface";
672 #iommu-cells = <0>;
673 status = "disabled";
674 };
675
676 vpu: video-codec@ff350000 {
677 compatible = "rockchip,rk3328-vpu";
678 reg = <0x0 0xff350000 0x0 0x800>;
679 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
680 interrupt-names = "vdpu";
681 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
682 clock-names = "aclk", "hclk";
683 iommus = <&vpu_mmu>;
684 power-domains = <&power RK3328_PD_VPU>;
685 };
686
687 vpu_mmu: iommu@ff350800 {
688 compatible = "rockchip,iommu";
689 reg = <0x0 0xff350800 0x0 0x40>;
690 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
692 clock-names = "aclk", "iface";
693 #iommu-cells = <0>;
694 power-domains = <&power RK3328_PD_VPU>;
695 };
696
697 vdec: video-codec@ff360000 {
698 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
699 reg = <0x0 0xff360000 0x0 0x480>;
700 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
702 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
703 clock-names = "axi", "ahb", "cabac", "core";
704 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
705 <&cru SCLK_VDEC_CORE>;
706 assigned-clock-rates = <400000000>, <400000000>, <300000000>;
707 iommus = <&vdec_mmu>;
708 power-domains = <&power RK3328_PD_VIDEO>;
709 };
710
711 vdec_mmu: iommu@ff360480 {
712 compatible = "rockchip,iommu";
713 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
714 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
716 clock-names = "aclk", "iface";
717 #iommu-cells = <0>;
718 power-domains = <&power RK3328_PD_VIDEO>;
719 };
720
721 vop: vop@ff370000 {
722 compatible = "rockchip,rk3328-vop";
723 reg = <0x0 0xff370000 0x0 0x3efc>;
724 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
726 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
727 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
728 reset-names = "axi", "ahb", "dclk";
729 iommus = <&vop_mmu>;
730 status = "disabled";
731
732 vop_out: port {
733 #address-cells = <1>;
734 #size-cells = <0>;
735
736 vop_out_hdmi: endpoint@0 {
737 reg = <0>;
738 remote-endpoint = <&hdmi_in_vop>;
739 };
740 };
741 };
742
743 vop_mmu: iommu@ff373f00 {
744 compatible = "rockchip,iommu";
745 reg = <0x0 0xff373f00 0x0 0x100>;
746 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
748 clock-names = "aclk", "iface";
749 #iommu-cells = <0>;
750 status = "disabled";
751 };
752
753 hdmi: hdmi@ff3c0000 {
754 compatible = "rockchip,rk3328-dw-hdmi";
755 reg = <0x0 0xff3c0000 0x0 0x20000>;
756 reg-io-width = <4>;
757 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&cru PCLK_HDMI>,
760 <&cru SCLK_HDMI_SFC>,
761 <&cru SCLK_RTC32K>;
762 clock-names = "iahb",
763 "isfr",
764 "cec";
765 phys = <&hdmiphy>;
766 phy-names = "hdmi";
767 pinctrl-names = "default";
768 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
769 rockchip,grf = <&grf>;
770 #sound-dai-cells = <0>;
771 status = "disabled";
772
773 ports {
774 #address-cells = <1>;
775 #size-cells = <0>;
776
777 hdmi_in: port@0 {
778 reg = <0>;
779
780 hdmi_in_vop: endpoint {
781 remote-endpoint = <&vop_out_hdmi>;
782 };
783 };
784
785 hdmi_out: port@1 {
786 reg = <1>;
787 };
788 };
789 };
790
791 codec: codec@ff410000 {
792 compatible = "rockchip,rk3328-codec";
793 reg = <0x0 0xff410000 0x0 0x1000>;
794 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
795 clock-names = "pclk", "mclk";
796 rockchip,grf = <&grf>;
797 #sound-dai-cells = <0>;
798 status = "disabled";
799 };
800
801 hdmiphy: phy@ff430000 {
802 compatible = "rockchip,rk3328-hdmi-phy";
803 reg = <0x0 0xff430000 0x0 0x10000>;
804 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
806 clock-names = "sysclk", "refoclk", "refpclk";
807 clock-output-names = "hdmi_phy";
808 #clock-cells = <0>;
809 nvmem-cells = <&efuse_cpu_version>;
810 nvmem-cell-names = "cpu-version";
811 #phy-cells = <0>;
812 status = "disabled";
813 };
814
815 cru: clock-controller@ff440000 {
816 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
817 reg = <0x0 0xff440000 0x0 0x1000>;
818 rockchip,grf = <&grf>;
819 #clock-cells = <1>;
820 #reset-cells = <1>;
821 assigned-clocks =
822 /*
823 * CPLL should run at 1200, but that is to high for
824 * the initial dividers of most of its children.
825 * We need set cpll child clk div first,
826 * and then set the cpll frequency.
827 */
828 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
829 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
830 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
831 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
832 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
833 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
834 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
835 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
836 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
837 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
838 <&cru SCLK_WIFI>, <&cru ARMCLK>,
839 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
840 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
841 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
842 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
843 <&cru SCLK_RTC32K>;
844 assigned-clock-parents =
845 <&cru HDMIPHY>, <&cru PLL_APLL>,
846 <&cru PLL_GPLL>, <&xin24m>,
847 <&xin24m>, <&xin24m>;
848 assigned-clock-rates =
849 <0>, <61440000>,
850 <0>, <24000000>,
851 <24000000>, <24000000>,
852 <15000000>, <15000000>,
853 <300000000>, <100000000>,
854 <400000000>, <100000000>,
855 <50000000>, <100000000>,
856 <100000000>, <100000000>,
857 <50000000>, <50000000>,
858 <50000000>, <50000000>,
859 <24000000>, <600000000>,
860 <491520000>, <1200000000>,
861 <150000000>, <75000000>,
862 <75000000>, <150000000>,
863 <75000000>, <75000000>,
864 <32768>;
865 };
866
867 usb2phy_grf: syscon@ff450000 {
868 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
869 "simple-mfd";
870 reg = <0x0 0xff450000 0x0 0x10000>;
871 #address-cells = <1>;
872 #size-cells = <1>;
873
874 u2phy: usb2phy@100 {
875 compatible = "rockchip,rk3328-usb2phy";
876 reg = <0x100 0x10>;
877 clocks = <&xin24m>;
878 clock-names = "phyclk";
879 clock-output-names = "usb480m_phy";
880 #clock-cells = <0>;
881 assigned-clocks = <&cru USB480M>;
882 assigned-clock-parents = <&u2phy>;
883 status = "disabled";
884
885 u2phy_otg: otg-port {
886 #phy-cells = <0>;
887 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
889 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
890 interrupt-names = "otg-bvalid", "otg-id",
891 "linestate";
892 status = "disabled";
893 };
894
895 u2phy_host: host-port {
896 #phy-cells = <0>;
897 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
898 interrupt-names = "linestate";
899 status = "disabled";
900 };
901 };
902 };
903
904 sdmmc: mmc@ff500000 {
905 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
906 reg = <0x0 0xff500000 0x0 0x4000>;
907 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
908 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
909 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
910 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
911 fifo-depth = <0x100>;
912 max-frequency = <150000000>;
913 status = "disabled";
914 };
915
916 sdio: mmc@ff510000 {
917 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
918 reg = <0x0 0xff510000 0x0 0x4000>;
919 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
921 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
922 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
923 fifo-depth = <0x100>;
924 max-frequency = <150000000>;
925 status = "disabled";
926 };
927
928 emmc: mmc@ff520000 {
929 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
930 reg = <0x0 0xff520000 0x0 0x4000>;
931 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
933 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
934 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
935 fifo-depth = <0x100>;
936 max-frequency = <150000000>;
937 status = "disabled";
938 };
939
940 gmac2io: ethernet@ff540000 {
941 compatible = "rockchip,rk3328-gmac";
942 reg = <0x0 0xff540000 0x0 0x10000>;
943 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
944 interrupt-names = "macirq";
945 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
946 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
947 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
948 <&cru PCLK_MAC2IO>;
949 clock-names = "stmmaceth", "mac_clk_rx",
950 "mac_clk_tx", "clk_mac_ref",
951 "clk_mac_refout", "aclk_mac",
952 "pclk_mac";
953 resets = <&cru SRST_GMAC2IO_A>;
954 reset-names = "stmmaceth";
955 rockchip,grf = <&grf>;
956 tx-fifo-depth = <2048>;
957 rx-fifo-depth = <4096>;
958 snps,txpbl = <0x4>;
959 status = "disabled";
960 };
961
962 gmac2phy: ethernet@ff550000 {
963 compatible = "rockchip,rk3328-gmac";
964 reg = <0x0 0xff550000 0x0 0x10000>;
965 rockchip,grf = <&grf>;
966 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
967 interrupt-names = "macirq";
968 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
969 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
970 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
971 <&cru SCLK_MAC2PHY_OUT>;
972 clock-names = "stmmaceth", "mac_clk_rx",
973 "mac_clk_tx", "clk_mac_ref",
974 "aclk_mac", "pclk_mac",
975 "clk_macphy";
976 resets = <&cru SRST_GMAC2PHY_A>;
977 reset-names = "stmmaceth";
978 phy-mode = "rmii";
979 phy-handle = <&phy>;
980 tx-fifo-depth = <2048>;
981 rx-fifo-depth = <4096>;
982 snps,txpbl = <0x4>;
983 clock_in_out = "output";
984 status = "disabled";
985
986 mdio {
987 compatible = "snps,dwmac-mdio";
988 #address-cells = <1>;
989 #size-cells = <0>;
990
991 phy: ethernet-phy@0 {
992 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
993 reg = <0>;
994 clocks = <&cru SCLK_MAC2PHY_OUT>;
995 resets = <&cru SRST_MACPHY>;
996 pinctrl-names = "default";
997 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
998 phy-is-integrated;
999 };
1000 };
1001 };
1002
1003 usb20_otg: usb@ff580000 {
1004 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
1005 "snps,dwc2";
1006 reg = <0x0 0xff580000 0x0 0x40000>;
1007 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&cru HCLK_OTG>;
1009 clock-names = "otg";
1010 dr_mode = "otg";
1011 g-np-tx-fifo-size = <16>;
1012 g-rx-fifo-size = <280>;
1013 g-tx-fifo-size = <256 128 128 64 32 16>;
1014 phys = <&u2phy_otg>;
1015 phy-names = "usb2-phy";
1016 status = "disabled";
1017 };
1018
1019 usb_host0_ehci: usb@ff5c0000 {
1020 compatible = "generic-ehci";
1021 reg = <0x0 0xff5c0000 0x0 0x10000>;
1022 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&cru HCLK_HOST0>, <&u2phy>;
1024 phys = <&u2phy_host>;
1025 phy-names = "usb";
1026 status = "disabled";
1027 };
1028
1029 usb_host0_ohci: usb@ff5d0000 {
1030 compatible = "generic-ohci";
1031 reg = <0x0 0xff5d0000 0x0 0x10000>;
1032 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1033 clocks = <&cru HCLK_HOST0>, <&u2phy>;
1034 phys = <&u2phy_host>;
1035 phy-names = "usb";
1036 status = "disabled";
1037 };
1038
1039 usbdrd3: usb@ff600000 {
1040 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1041 reg = <0x0 0xff600000 0x0 0x100000>;
1042 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1044 <&cru ACLK_USB3OTG>;
1045 clock-names = "ref_clk", "suspend_clk",
1046 "bus_clk";
1047 dr_mode = "otg";
1048 phy_type = "utmi_wide";
1049 snps,dis-del-phy-power-chg-quirk;
1050 snps,dis_enblslpm_quirk;
1051 snps,dis-tx-ipgap-linecheck-quirk;
1052 snps,dis-u2-freeclk-exists-quirk;
1053 snps,dis_u2_susphy_quirk;
1054 snps,dis_u3_susphy_quirk;
1055 status = "disabled";
1056 };
1057
1058 gic: interrupt-controller@ff811000 {
1059 compatible = "arm,gic-400";
1060 #interrupt-cells = <3>;
1061 #address-cells = <0>;
1062 interrupt-controller;
1063 reg = <0x0 0xff811000 0 0x1000>,
1064 <0x0 0xff812000 0 0x2000>,
1065 <0x0 0xff814000 0 0x2000>,
1066 <0x0 0xff816000 0 0x2000>;
1067 interrupts = <GIC_PPI 9
1068 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1069 };
1070
1071 crypto: crypto@ff060000 {
1072 compatible = "rockchip,rk3328-crypto";
1073 reg = <0x0 0xff060000 0x0 0x4000>;
1074 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1075 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
1076 <&cru SCLK_CRYPTO>;
1077 clock-names = "hclk_master", "hclk_slave", "sclk";
1078 resets = <&cru SRST_CRYPTO>;
1079 reset-names = "crypto-rst";
1080 };
1081
1082 pinctrl: pinctrl {
1083 compatible = "rockchip,rk3328-pinctrl";
1084 rockchip,grf = <&grf>;
1085 #address-cells = <2>;
1086 #size-cells = <2>;
1087 ranges;
1088
1089 gpio0: gpio@ff210000 {
1090 compatible = "rockchip,gpio-bank";
1091 reg = <0x0 0xff210000 0x0 0x100>;
1092 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&cru PCLK_GPIO0>;
1094
1095 gpio-controller;
1096 #gpio-cells = <2>;
1097
1098 interrupt-controller;
1099 #interrupt-cells = <2>;
1100 };
1101
1102 gpio1: gpio@ff220000 {
1103 compatible = "rockchip,gpio-bank";
1104 reg = <0x0 0xff220000 0x0 0x100>;
1105 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&cru PCLK_GPIO1>;
1107
1108 gpio-controller;
1109 #gpio-cells = <2>;
1110
1111 interrupt-controller;
1112 #interrupt-cells = <2>;
1113 };
1114
1115 gpio2: gpio@ff230000 {
1116 compatible = "rockchip,gpio-bank";
1117 reg = <0x0 0xff230000 0x0 0x100>;
1118 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1119 clocks = <&cru PCLK_GPIO2>;
1120
1121 gpio-controller;
1122 #gpio-cells = <2>;
1123
1124 interrupt-controller;
1125 #interrupt-cells = <2>;
1126 };
1127
1128 gpio3: gpio@ff240000 {
1129 compatible = "rockchip,gpio-bank";
1130 reg = <0x0 0xff240000 0x0 0x100>;
1131 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1132 clocks = <&cru PCLK_GPIO3>;
1133
1134 gpio-controller;
1135 #gpio-cells = <2>;
1136
1137 interrupt-controller;
1138 #interrupt-cells = <2>;
1139 };
1140
1141 pcfg_pull_up: pcfg-pull-up {
1142 bias-pull-up;
1143 };
1144
1145 pcfg_pull_down: pcfg-pull-down {
1146 bias-pull-down;
1147 };
1148
1149 pcfg_pull_none: pcfg-pull-none {
1150 bias-disable;
1151 };
1152
1153 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1154 bias-disable;
1155 drive-strength = <2>;
1156 };
1157
1158 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1159 bias-pull-up;
1160 drive-strength = <2>;
1161 };
1162
1163 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1164 bias-pull-up;
1165 drive-strength = <4>;
1166 };
1167
1168 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1169 bias-disable;
1170 drive-strength = <4>;
1171 };
1172
1173 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1174 bias-pull-down;
1175 drive-strength = <4>;
1176 };
1177
1178 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1179 bias-disable;
1180 drive-strength = <8>;
1181 };
1182
1183 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1184 bias-pull-up;
1185 drive-strength = <8>;
1186 };
1187
1188 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1189 bias-disable;
1190 drive-strength = <12>;
1191 };
1192
1193 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1194 bias-pull-up;
1195 drive-strength = <12>;
1196 };
1197
1198 pcfg_output_high: pcfg-output-high {
1199 output-high;
1200 };
1201
1202 pcfg_output_low: pcfg-output-low {
1203 output-low;
1204 };
1205
1206 pcfg_input_high: pcfg-input-high {
1207 bias-pull-up;
1208 input-enable;
1209 };
1210
1211 pcfg_input: pcfg-input {
1212 input-enable;
1213 };
1214
1215 i2c0 {
1216 i2c0_xfer: i2c0-xfer {
1217 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1218 <2 RK_PD1 1 &pcfg_pull_none>;
1219 };
1220 };
1221
1222 i2c1 {
1223 i2c1_xfer: i2c1-xfer {
1224 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1225 <2 RK_PA5 2 &pcfg_pull_none>;
1226 };
1227 };
1228
1229 i2c2 {
1230 i2c2_xfer: i2c2-xfer {
1231 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1232 <2 RK_PB6 1 &pcfg_pull_none>;
1233 };
1234 };
1235
1236 i2c3 {
1237 i2c3_xfer: i2c3-xfer {
1238 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1239 <0 RK_PA6 2 &pcfg_pull_none>;
1240 };
1241 i2c3_pins: i2c3-pins {
1242 rockchip,pins =
1243 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1244 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1245 };
1246 };
1247
1248 hdmi_i2c {
1249 hdmii2c_xfer: hdmii2c-xfer {
1250 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1251 <0 RK_PA6 1 &pcfg_pull_none>;
1252 };
1253 };
1254
1255 pdm-0 {
1256 pdmm0_clk: pdmm0-clk {
1257 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1258 };
1259
1260 pdmm0_fsync: pdmm0-fsync {
1261 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1262 };
1263
1264 pdmm0_sdi0: pdmm0-sdi0 {
1265 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1266 };
1267
1268 pdmm0_sdi1: pdmm0-sdi1 {
1269 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1270 };
1271
1272 pdmm0_sdi2: pdmm0-sdi2 {
1273 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1274 };
1275
1276 pdmm0_sdi3: pdmm0-sdi3 {
1277 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1278 };
1279
1280 pdmm0_clk_sleep: pdmm0-clk-sleep {
1281 rockchip,pins =
1282 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1283 };
1284
1285 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1286 rockchip,pins =
1287 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1288 };
1289
1290 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1291 rockchip,pins =
1292 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1293 };
1294
1295 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1296 rockchip,pins =
1297 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1298 };
1299
1300 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1301 rockchip,pins =
1302 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1303 };
1304
1305 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1306 rockchip,pins =
1307 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1308 };
1309 };
1310
1311 tsadc {
1312 otp_pin: otp-pin {
1313 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1314 };
1315
1316 otp_out: otp-out {
1317 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1318 };
1319 };
1320
1321 uart0 {
1322 uart0_xfer: uart0-xfer {
1323 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1324 <1 RK_PB0 1 &pcfg_pull_up>;
1325 };
1326
1327 uart0_cts: uart0-cts {
1328 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1329 };
1330
1331 uart0_rts: uart0-rts {
1332 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1333 };
1334
1335 uart0_rts_pin: uart0-rts-pin {
1336 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1337 };
1338 };
1339
1340 uart1 {
1341 uart1_xfer: uart1-xfer {
1342 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1343 <3 RK_PA6 4 &pcfg_pull_up>;
1344 };
1345
1346 uart1_cts: uart1-cts {
1347 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1348 };
1349
1350 uart1_rts: uart1-rts {
1351 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1352 };
1353
1354 uart1_rts_pin: uart1-rts-pin {
1355 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1356 };
1357 };
1358
1359 uart2-0 {
1360 uart2m0_xfer: uart2m0-xfer {
1361 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1362 <1 RK_PA1 2 &pcfg_pull_up>;
1363 };
1364 };
1365
1366 uart2-1 {
1367 uart2m1_xfer: uart2m1-xfer {
1368 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1369 <2 RK_PA1 1 &pcfg_pull_up>;
1370 };
1371 };
1372
1373 spi0-0 {
1374 spi0m0_clk: spi0m0-clk {
1375 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1376 };
1377
1378 spi0m0_cs0: spi0m0-cs0 {
1379 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1380 };
1381
1382 spi0m0_tx: spi0m0-tx {
1383 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1384 };
1385
1386 spi0m0_rx: spi0m0-rx {
1387 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1388 };
1389
1390 spi0m0_cs1: spi0m0-cs1 {
1391 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1392 };
1393 };
1394
1395 spi0-1 {
1396 spi0m1_clk: spi0m1-clk {
1397 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1398 };
1399
1400 spi0m1_cs0: spi0m1-cs0 {
1401 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1402 };
1403
1404 spi0m1_tx: spi0m1-tx {
1405 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1406 };
1407
1408 spi0m1_rx: spi0m1-rx {
1409 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1410 };
1411
1412 spi0m1_cs1: spi0m1-cs1 {
1413 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1414 };
1415 };
1416
1417 spi0-2 {
1418 spi0m2_clk: spi0m2-clk {
1419 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1420 };
1421
1422 spi0m2_cs0: spi0m2-cs0 {
1423 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1424 };
1425
1426 spi0m2_tx: spi0m2-tx {
1427 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1428 };
1429
1430 spi0m2_rx: spi0m2-rx {
1431 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1432 };
1433 };
1434
1435 i2s1 {
1436 i2s1_mclk: i2s1-mclk {
1437 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1438 };
1439
1440 i2s1_sclk: i2s1-sclk {
1441 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1442 };
1443
1444 i2s1_lrckrx: i2s1-lrckrx {
1445 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1446 };
1447
1448 i2s1_lrcktx: i2s1-lrcktx {
1449 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1450 };
1451
1452 i2s1_sdi: i2s1-sdi {
1453 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1454 };
1455
1456 i2s1_sdo: i2s1-sdo {
1457 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1458 };
1459
1460 i2s1_sdio1: i2s1-sdio1 {
1461 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1462 };
1463
1464 i2s1_sdio2: i2s1-sdio2 {
1465 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1466 };
1467
1468 i2s1_sdio3: i2s1-sdio3 {
1469 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1470 };
1471
1472 i2s1_sleep: i2s1-sleep {
1473 rockchip,pins =
1474 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1475 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1476 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1477 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1478 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1479 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1480 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1481 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1482 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1483 };
1484 };
1485
1486 i2s2-0 {
1487 i2s2m0_mclk: i2s2m0-mclk {
1488 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1489 };
1490
1491 i2s2m0_sclk: i2s2m0-sclk {
1492 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1493 };
1494
1495 i2s2m0_lrckrx: i2s2m0-lrckrx {
1496 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1497 };
1498
1499 i2s2m0_lrcktx: i2s2m0-lrcktx {
1500 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1501 };
1502
1503 i2s2m0_sdi: i2s2m0-sdi {
1504 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1505 };
1506
1507 i2s2m0_sdo: i2s2m0-sdo {
1508 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1509 };
1510
1511 i2s2m0_sleep: i2s2m0-sleep {
1512 rockchip,pins =
1513 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1514 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1515 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1516 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1517 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1518 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1519 };
1520 };
1521
1522 i2s2-1 {
1523 i2s2m1_mclk: i2s2m1-mclk {
1524 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1525 };
1526
1527 i2s2m1_sclk: i2s2m1-sclk {
1528 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1529 };
1530
1531 i2s2m1_lrckrx: i2sm1-lrckrx {
1532 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1533 };
1534
1535 i2s2m1_lrcktx: i2s2m1-lrcktx {
1536 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1537 };
1538
1539 i2s2m1_sdi: i2s2m1-sdi {
1540 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1541 };
1542
1543 i2s2m1_sdo: i2s2m1-sdo {
1544 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1545 };
1546
1547 i2s2m1_sleep: i2s2m1-sleep {
1548 rockchip,pins =
1549 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1550 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1551 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1552 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1553 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1554 };
1555 };
1556
1557 spdif-0 {
1558 spdifm0_tx: spdifm0-tx {
1559 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1560 };
1561 };
1562
1563 spdif-1 {
1564 spdifm1_tx: spdifm1-tx {
1565 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1566 };
1567 };
1568
1569 spdif-2 {
1570 spdifm2_tx: spdifm2-tx {
1571 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1572 };
1573 };
1574
1575 sdmmc0-0 {
1576 sdmmc0m0_pwren: sdmmc0m0-pwren {
1577 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1578 };
1579
1580 sdmmc0m0_pin: sdmmc0m0-pin {
1581 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1582 };
1583 };
1584
1585 sdmmc0-1 {
1586 sdmmc0m1_pwren: sdmmc0m1-pwren {
1587 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1588 };
1589
1590 sdmmc0m1_pin: sdmmc0m1-pin {
1591 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1592 };
1593 };
1594
1595 sdmmc0 {
1596 sdmmc0_clk: sdmmc0-clk {
1597 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1598 };
1599
1600 sdmmc0_cmd: sdmmc0-cmd {
1601 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1602 };
1603
1604 sdmmc0_dectn: sdmmc0-dectn {
1605 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1606 };
1607
1608 sdmmc0_wrprt: sdmmc0-wrprt {
1609 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1610 };
1611
1612 sdmmc0_bus1: sdmmc0-bus1 {
1613 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1614 };
1615
1616 sdmmc0_bus4: sdmmc0-bus4 {
1617 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1618 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1619 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1620 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1621 };
1622
1623 sdmmc0_pins: sdmmc0-pins {
1624 rockchip,pins =
1625 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1626 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1627 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1628 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1629 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1630 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1631 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1632 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1633 };
1634 };
1635
1636 sdmmc0ext {
1637 sdmmc0ext_clk: sdmmc0ext-clk {
1638 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1639 };
1640
1641 sdmmc0ext_cmd: sdmmc0ext-cmd {
1642 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1643 };
1644
1645 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1646 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1647 };
1648
1649 sdmmc0ext_dectn: sdmmc0ext-dectn {
1650 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1651 };
1652
1653 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1654 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1655 };
1656
1657 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1658 rockchip,pins =
1659 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1660 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1661 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1662 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1663 };
1664
1665 sdmmc0ext_pins: sdmmc0ext-pins {
1666 rockchip,pins =
1667 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1668 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1669 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1670 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1671 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1672 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1673 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1674 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1675 };
1676 };
1677
1678 sdmmc1 {
1679 sdmmc1_clk: sdmmc1-clk {
1680 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1681 };
1682
1683 sdmmc1_cmd: sdmmc1-cmd {
1684 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1685 };
1686
1687 sdmmc1_pwren: sdmmc1-pwren {
1688 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1689 };
1690
1691 sdmmc1_wrprt: sdmmc1-wrprt {
1692 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1693 };
1694
1695 sdmmc1_dectn: sdmmc1-dectn {
1696 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1697 };
1698
1699 sdmmc1_bus1: sdmmc1-bus1 {
1700 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1701 };
1702
1703 sdmmc1_bus4: sdmmc1-bus4 {
1704 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1705 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1706 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1707 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1708 };
1709
1710 sdmmc1_pins: sdmmc1-pins {
1711 rockchip,pins =
1712 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1713 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1714 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1715 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1716 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1717 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1718 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1719 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1720 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1721 };
1722 };
1723
1724 emmc {
1725 emmc_clk: emmc-clk {
1726 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1727 };
1728
1729 emmc_cmd: emmc-cmd {
1730 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1731 };
1732
1733 emmc_pwren: emmc-pwren {
1734 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1735 };
1736
1737 emmc_rstnout: emmc-rstnout {
1738 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1739 };
1740
1741 emmc_bus1: emmc-bus1 {
1742 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1743 };
1744
1745 emmc_bus4: emmc-bus4 {
1746 rockchip,pins =
1747 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1748 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1749 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1750 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1751 };
1752
1753 emmc_bus8: emmc-bus8 {
1754 rockchip,pins =
1755 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1756 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1757 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1758 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1759 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1760 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1761 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1762 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1763 };
1764 };
1765
1766 pwm0 {
1767 pwm0_pin: pwm0-pin {
1768 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1769 };
1770 };
1771
1772 pwm1 {
1773 pwm1_pin: pwm1-pin {
1774 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1775 };
1776 };
1777
1778 pwm2 {
1779 pwm2_pin: pwm2-pin {
1780 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1781 };
1782 };
1783
1784 pwmir {
1785 pwmir_pin: pwmir-pin {
1786 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1787 };
1788 };
1789
1790 gmac-1 {
1791 rgmiim1_pins: rgmiim1-pins {
1792 rockchip,pins =
1793 /* mac_txclk */
1794 <1 RK_PB4 2 &pcfg_pull_none_8ma>,
1795 /* mac_rxclk */
1796 <1 RK_PB5 2 &pcfg_pull_none_4ma>,
1797 /* mac_mdio */
1798 <1 RK_PC3 2 &pcfg_pull_none_4ma>,
1799 /* mac_txen */
1800 <1 RK_PD1 2 &pcfg_pull_none_8ma>,
1801 /* mac_clk */
1802 <1 RK_PC5 2 &pcfg_pull_none_4ma>,
1803 /* mac_rxdv */
1804 <1 RK_PC6 2 &pcfg_pull_none_4ma>,
1805 /* mac_mdc */
1806 <1 RK_PC7 2 &pcfg_pull_none_4ma>,
1807 /* mac_rxd1 */
1808 <1 RK_PB2 2 &pcfg_pull_none_4ma>,
1809 /* mac_rxd0 */
1810 <1 RK_PB3 2 &pcfg_pull_none_4ma>,
1811 /* mac_txd1 */
1812 <1 RK_PB0 2 &pcfg_pull_none_8ma>,
1813 /* mac_txd0 */
1814 <1 RK_PB1 2 &pcfg_pull_none_8ma>,
1815 /* mac_rxd3 */
1816 <1 RK_PB6 2 &pcfg_pull_none_4ma>,
1817 /* mac_rxd2 */
1818 <1 RK_PB7 2 &pcfg_pull_none_4ma>,
1819 /* mac_txd3 */
1820 <1 RK_PC0 2 &pcfg_pull_none_8ma>,
1821 /* mac_txd2 */
1822 <1 RK_PC1 2 &pcfg_pull_none_8ma>,
1823
1824 /* mac_txclk */
1825 <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1826 /* mac_txen */
1827 <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1828 /* mac_clk */
1829 <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1830 /* mac_txd1 */
1831 <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1832 /* mac_txd0 */
1833 <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1834 /* mac_txd3 */
1835 <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1836 /* mac_txd2 */
1837 <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1838 };
1839
1840 rmiim1_pins: rmiim1-pins {
1841 rockchip,pins =
1842 /* mac_mdio */
1843 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1844 /* mac_txen */
1845 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1846 /* mac_clk */
1847 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1848 /* mac_rxer */
1849 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1850 /* mac_rxdv */
1851 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1852 /* mac_mdc */
1853 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1854 /* mac_rxd1 */
1855 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1856 /* mac_rxd0 */
1857 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1858 /* mac_txd1 */
1859 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1860 /* mac_txd0 */
1861 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1862
1863 /* mac_mdio */
1864 <0 RK_PB3 1 &pcfg_pull_none>,
1865 /* mac_txen */
1866 <0 RK_PB4 1 &pcfg_pull_none>,
1867 /* mac_clk */
1868 <0 RK_PD0 1 &pcfg_pull_none>,
1869 /* mac_mdc */
1870 <0 RK_PC3 1 &pcfg_pull_none>,
1871 /* mac_txd1 */
1872 <0 RK_PC0 1 &pcfg_pull_none>,
1873 /* mac_txd0 */
1874 <0 RK_PC1 1 &pcfg_pull_none>;
1875 };
1876 };
1877
1878 gmac2phy {
1879 fephyled_speed10: fephyled-speed10 {
1880 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1881 };
1882
1883 fephyled_duplex: fephyled-duplex {
1884 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1885 };
1886
1887 fephyled_rxm1: fephyled-rxm1 {
1888 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1889 };
1890
1891 fephyled_txm1: fephyled-txm1 {
1892 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1893 };
1894
1895 fephyled_linkm1: fephyled-linkm1 {
1896 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1897 };
1898 };
1899
1900 tsadc_pin {
1901 tsadc_int: tsadc-int {
1902 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1903 };
1904 tsadc_pin: tsadc-pin {
1905 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1906 };
1907 };
1908
1909 hdmi_pin {
1910 hdmi_cec: hdmi-cec {
1911 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1912 };
1913
1914 hdmi_hpd: hdmi-hpd {
1915 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1916 };
1917 };
1918
1919 cif-0 {
1920 dvp_d2d9_m0:dvp-d2d9-m0 {
1921 rockchip,pins =
1922 /* cif_d0 */
1923 <3 RK_PA4 2 &pcfg_pull_none>,
1924 /* cif_d1 */
1925 <3 RK_PA5 2 &pcfg_pull_none>,
1926 /* cif_d2 */
1927 <3 RK_PA6 2 &pcfg_pull_none>,
1928 /* cif_d3 */
1929 <3 RK_PA7 2 &pcfg_pull_none>,
1930 /* cif_d4 */
1931 <3 RK_PB0 2 &pcfg_pull_none>,
1932 /* cif_d5m0 */
1933 <3 RK_PB1 2 &pcfg_pull_none>,
1934 /* cif_d6m0 */
1935 <3 RK_PB2 2 &pcfg_pull_none>,
1936 /* cif_d7m0 */
1937 <3 RK_PB3 2 &pcfg_pull_none>,
1938 /* cif_href */
1939 <3 RK_PA1 2 &pcfg_pull_none>,
1940 /* cif_vsync */
1941 <3 RK_PA0 2 &pcfg_pull_none>,
1942 /* cif_clkoutm0 */
1943 <3 RK_PA3 2 &pcfg_pull_none>,
1944 /* cif_clkin */
1945 <3 RK_PA2 2 &pcfg_pull_none>;
1946 };
1947 };
1948
1949 cif-1 {
1950 dvp_d2d9_m1:dvp-d2d9-m1 {
1951 rockchip,pins =
1952 /* cif_d0 */
1953 <3 RK_PA4 2 &pcfg_pull_none>,
1954 /* cif_d1 */
1955 <3 RK_PA5 2 &pcfg_pull_none>,
1956 /* cif_d2 */
1957 <3 RK_PA6 2 &pcfg_pull_none>,
1958 /* cif_d3 */
1959 <3 RK_PA7 2 &pcfg_pull_none>,
1960 /* cif_d4 */
1961 <3 RK_PB0 2 &pcfg_pull_none>,
1962 /* cif_d5m1 */
1963 <2 RK_PC0 4 &pcfg_pull_none>,
1964 /* cif_d6m1 */
1965 <2 RK_PC1 4 &pcfg_pull_none>,
1966 /* cif_d7m1 */
1967 <2 RK_PC2 4 &pcfg_pull_none>,
1968 /* cif_href */
1969 <3 RK_PA1 2 &pcfg_pull_none>,
1970 /* cif_vsync */
1971 <3 RK_PA0 2 &pcfg_pull_none>,
1972 /* cif_clkoutm1 */
1973 <2 RK_PB7 4 &pcfg_pull_none>,
1974 /* cif_clkin */
1975 <3 RK_PA2 2 &pcfg_pull_none>;
1976 };
1977 };
1978 };
1979 };
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