1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 */
5
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
14
15 / {
16 compatible = "rockchip,rk3368";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 gpio2 = &gpio2;
25 gpio3 = &gpio3;
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 i2c2 = &i2c2;
29 i2c3 = &i2c3;
30 i2c4 = &i2c4;
31 i2c5 = &i2c5;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 spi0 = &spi0;
38 spi1 = &spi1;
39 spi2 = &spi2;
40 };
41
42 cpus {
43 #address-cells = <0x2>;
44 #size-cells = <0x0>;
45
46 cpu-map {
47 cluster0 {
48 core0 {
49 cpu = <&cpu_b0>;
50 };
51 core1 {
52 cpu = <&cpu_b1>;
53 };
54 core2 {
55 cpu = <&cpu_b2>;
56 };
57 core3 {
58 cpu = <&cpu_b3>;
59 };
60 };
61
62 cluster1 {
63 core0 {
64 cpu = <&cpu_l0>;
65 };
66 core1 {
67 cpu = <&cpu_l1>;
68 };
69 core2 {
70 cpu = <&cpu_l2>;
71 };
72 core3 {
73 cpu = <&cpu_l3>;
74 };
75 };
76 };
77
78 cpu_l0: cpu@0 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a53";
81 reg = <0x0 0x0>;
82 enable-method = "psci";
83 #cooling-cells = <2>; /* min followed by max */
84 };
85
86 cpu_l1: cpu@1 {
87 device_type = "cpu";
88 compatible = "arm,cortex-a53";
89 reg = <0x0 0x1>;
90 enable-method = "psci";
91 #cooling-cells = <2>; /* min followed by max */
92 };
93
94 cpu_l2: cpu@2 {
95 device_type = "cpu";
96 compatible = "arm,cortex-a53";
97 reg = <0x0 0x2>;
98 enable-method = "psci";
99 #cooling-cells = <2>; /* min followed by max */
100 };
101
102 cpu_l3: cpu@3 {
103 device_type = "cpu";
104 compatible = "arm,cortex-a53";
105 reg = <0x0 0x3>;
106 enable-method = "psci";
107 #cooling-cells = <2>; /* min followed by max */
108 };
109
110 cpu_b0: cpu@100 {
111 device_type = "cpu";
112 compatible = "arm,cortex-a53";
113 reg = <0x0 0x100>;
114 enable-method = "psci";
115 #cooling-cells = <2>; /* min followed by max */
116 };
117
118 cpu_b1: cpu@101 {
119 device_type = "cpu";
120 compatible = "arm,cortex-a53";
121 reg = <0x0 0x101>;
122 enable-method = "psci";
123 #cooling-cells = <2>; /* min followed by max */
124 };
125
126 cpu_b2: cpu@102 {
127 device_type = "cpu";
128 compatible = "arm,cortex-a53";
129 reg = <0x0 0x102>;
130 enable-method = "psci";
131 #cooling-cells = <2>; /* min followed by max */
132 };
133
134 cpu_b3: cpu@103 {
135 device_type = "cpu";
136 compatible = "arm,cortex-a53";
137 reg = <0x0 0x103>;
138 enable-method = "psci";
139 #cooling-cells = <2>; /* min followed by max */
140 };
141 };
142
143 arm-pmu {
144 compatible = "arm,cortex-a53-pmu";
145 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
153 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
154 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
155 <&cpu_b2>, <&cpu_b3>;
156 };
157
158 psci {
159 compatible = "arm,psci-0.2";
160 method = "smc";
161 };
162
163 timer {
164 compatible = "arm,armv8-timer";
165 interrupts = <GIC_PPI 13
166 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
167 <GIC_PPI 14
168 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
169 <GIC_PPI 11
170 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
171 <GIC_PPI 10
172 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
173 };
174
175 xin24m: oscillator {
176 compatible = "fixed-clock";
177 clock-frequency = <24000000>;
178 clock-output-names = "xin24m";
179 #clock-cells = <0>;
180 };
181
182 sdmmc: mmc@ff0c0000 {
183 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
184 reg = <0x0 0xff0c0000 0x0 0x4000>;
185 max-frequency = <150000000>;
186 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
187 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
188 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
189 fifo-depth = <0x100>;
190 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
191 resets = <&cru SRST_MMC0>;
192 reset-names = "reset";
193 status = "disabled";
194 };
195
196 sdio0: mmc@ff0d0000 {
197 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
198 reg = <0x0 0xff0d0000 0x0 0x4000>;
199 max-frequency = <150000000>;
200 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
201 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
202 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
203 fifo-depth = <0x100>;
204 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
205 resets = <&cru SRST_SDIO0>;
206 reset-names = "reset";
207 status = "disabled";
208 };
209
210 emmc: mmc@ff0f0000 {
211 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
212 reg = <0x0 0xff0f0000 0x0 0x4000>;
213 max-frequency = <150000000>;
214 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
215 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
216 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
217 fifo-depth = <0x100>;
218 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
219 resets = <&cru SRST_EMMC>;
220 reset-names = "reset";
221 status = "disabled";
222 };
223
224 saradc: saradc@ff100000 {
225 compatible = "rockchip,saradc";
226 reg = <0x0 0xff100000 0x0 0x100>;
227 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
228 #io-channel-cells = <1>;
229 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
230 clock-names = "saradc", "apb_pclk";
231 resets = <&cru SRST_SARADC>;
232 reset-names = "saradc-apb";
233 status = "disabled";
234 };
235
236 spi0: spi@ff110000 {
237 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
238 reg = <0x0 0xff110000 0x0 0x1000>;
239 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
240 clock-names = "spiclk", "apb_pclk";
241 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 status = "disabled";
247 };
248
249 spi1: spi@ff120000 {
250 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
251 reg = <0x0 0xff120000 0x0 0x1000>;
252 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
253 clock-names = "spiclk", "apb_pclk";
254 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
257 #address-cells = <1>;
258 #size-cells = <0>;
259 status = "disabled";
260 };
261
262 spi2: spi@ff130000 {
263 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
264 reg = <0x0 0xff130000 0x0 0x1000>;
265 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
266 clock-names = "spiclk", "apb_pclk";
267 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
270 #address-cells = <1>;
271 #size-cells = <0>;
272 status = "disabled";
273 };
274
275 i2c2: i2c@ff140000 {
276 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
277 reg = <0x0 0xff140000 0x0 0x1000>;
278 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281 clock-names = "i2c";
282 clocks = <&cru PCLK_I2C2>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&i2c2_xfer>;
285 status = "disabled";
286 };
287
288 i2c3: i2c@ff150000 {
289 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
290 reg = <0x0 0xff150000 0x0 0x1000>;
291 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 clock-names = "i2c";
295 clocks = <&cru PCLK_I2C3>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&i2c3_xfer>;
298 status = "disabled";
299 };
300
301 i2c4: i2c@ff160000 {
302 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
303 reg = <0x0 0xff160000 0x0 0x1000>;
304 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
305 #address-cells = <1>;
306 #size-cells = <0>;
307 clock-names = "i2c";
308 clocks = <&cru PCLK_I2C4>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&i2c4_xfer>;
311 status = "disabled";
312 };
313
314 i2c5: i2c@ff170000 {
315 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
316 reg = <0x0 0xff170000 0x0 0x1000>;
317 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
318 #address-cells = <1>;
319 #size-cells = <0>;
320 clock-names = "i2c";
321 clocks = <&cru PCLK_I2C5>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&i2c5_xfer>;
324 status = "disabled";
325 };
326
327 uart0: serial@ff180000 {
328 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
329 reg = <0x0 0xff180000 0x0 0x100>;
330 clock-frequency = <24000000>;
331 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
332 clock-names = "baudclk", "apb_pclk";
333 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
334 reg-shift = <2>;
335 reg-io-width = <4>;
336 status = "disabled";
337 };
338
339 uart1: serial@ff190000 {
340 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
341 reg = <0x0 0xff190000 0x0 0x100>;
342 clock-frequency = <24000000>;
343 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
344 clock-names = "baudclk", "apb_pclk";
345 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
346 reg-shift = <2>;
347 reg-io-width = <4>;
348 status = "disabled";
349 };
350
351 uart3: serial@ff1b0000 {
352 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
353 reg = <0x0 0xff1b0000 0x0 0x100>;
354 clock-frequency = <24000000>;
355 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
356 clock-names = "baudclk", "apb_pclk";
357 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
358 reg-shift = <2>;
359 reg-io-width = <4>;
360 status = "disabled";
361 };
362
363 uart4: serial@ff1c0000 {
364 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
365 reg = <0x0 0xff1c0000 0x0 0x100>;
366 clock-frequency = <24000000>;
367 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
368 clock-names = "baudclk", "apb_pclk";
369 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
370 reg-shift = <2>;
371 reg-io-width = <4>;
372 status = "disabled";
373 };
374
375 dmac_peri: dma-controller@ff250000 {
376 compatible = "arm,pl330", "arm,primecell";
377 reg = <0x0 0xff250000 0x0 0x4000>;
378 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
380 #dma-cells = <1>;
381 arm,pl330-broken-no-flushp;
382 arm,pl330-periph-burst;
383 clocks = <&cru ACLK_DMAC_PERI>;
384 clock-names = "apb_pclk";
385 };
386
387 thermal-zones {
388 cpu_thermal: cpu-thermal {
389 polling-delay-passive = <100>; /* milliseconds */
390 polling-delay = <5000>; /* milliseconds */
391
392 thermal-sensors = <&tsadc 0>;
393
394 trips {
395 cpu_alert0: cpu_alert0 {
396 temperature = <75000>; /* millicelsius */
397 hysteresis = <2000>; /* millicelsius */
398 type = "passive";
399 };
400 cpu_alert1: cpu_alert1 {
401 temperature = <80000>; /* millicelsius */
402 hysteresis = <2000>; /* millicelsius */
403 type = "passive";
404 };
405 cpu_crit: cpu_crit {
406 temperature = <95000>; /* millicelsius */
407 hysteresis = <2000>; /* millicelsius */
408 type = "critical";
409 };
410 };
411
412 cooling-maps {
413 map0 {
414 trip = <&cpu_alert0>;
415 cooling-device =
416 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
417 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
418 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
419 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
420 };
421 map1 {
422 trip = <&cpu_alert1>;
423 cooling-device =
424 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
425 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
426 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
427 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
428 };
429 };
430 };
431
432 gpu_thermal: gpu-thermal {
433 polling-delay-passive = <100>; /* milliseconds */
434 polling-delay = <5000>; /* milliseconds */
435
436 thermal-sensors = <&tsadc 1>;
437
438 trips {
439 gpu_alert0: gpu_alert0 {
440 temperature = <80000>; /* millicelsius */
441 hysteresis = <2000>; /* millicelsius */
442 type = "passive";
443 };
444 gpu_crit: gpu_crit {
445 temperature = <115000>; /* millicelsius */
446 hysteresis = <2000>; /* millicelsius */
447 type = "critical";
448 };
449 };
450
451 cooling-maps {
452 map0 {
453 trip = <&gpu_alert0>;
454 cooling-device =
455 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
456 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
457 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
458 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
459 };
460 };
461 };
462 };
463
464 tsadc: tsadc@ff280000 {
465 compatible = "rockchip,rk3368-tsadc";
466 reg = <0x0 0xff280000 0x0 0x100>;
467 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
469 clock-names = "tsadc", "apb_pclk";
470 resets = <&cru SRST_TSADC>;
471 reset-names = "tsadc-apb";
472 pinctrl-names = "init", "default", "sleep";
473 pinctrl-0 = <&otp_pin>;
474 pinctrl-1 = <&otp_out>;
475 pinctrl-2 = <&otp_pin>;
476 #thermal-sensor-cells = <1>;
477 rockchip,hw-tshut-temp = <95000>;
478 status = "disabled";
479 };
480
481 gmac: ethernet@ff290000 {
482 compatible = "rockchip,rk3368-gmac";
483 reg = <0x0 0xff290000 0x0 0x10000>;
484 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
485 interrupt-names = "macirq";
486 rockchip,grf = <&grf>;
487 clocks = <&cru SCLK_MAC>,
488 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
489 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
490 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
491 clock-names = "stmmaceth",
492 "mac_clk_rx", "mac_clk_tx",
493 "clk_mac_ref", "clk_mac_refout",
494 "aclk_mac", "pclk_mac";
495 status = "disabled";
496 };
497
498 usb_host0_ehci: usb@ff500000 {
499 compatible = "generic-ehci";
500 reg = <0x0 0xff500000 0x0 0x100>;
501 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&cru HCLK_HOST0>;
503 status = "disabled";
504 };
505
506 usb_otg: usb@ff580000 {
507 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
508 "snps,dwc2";
509 reg = <0x0 0xff580000 0x0 0x40000>;
510 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cru HCLK_OTG0>;
512 clock-names = "otg";
513 dr_mode = "otg";
514 g-np-tx-fifo-size = <16>;
515 g-rx-fifo-size = <275>;
516 g-tx-fifo-size = <256 128 128 64 64 32>;
517 status = "disabled";
518 };
519
520 dmac_bus: dma-controller@ff600000 {
521 compatible = "arm,pl330", "arm,primecell";
522 reg = <0x0 0xff600000 0x0 0x4000>;
523 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
525 #dma-cells = <1>;
526 arm,pl330-broken-no-flushp;
527 arm,pl330-periph-burst;
528 clocks = <&cru ACLK_DMAC_BUS>;
529 clock-names = "apb_pclk";
530 };
531
532 i2c0: i2c@ff650000 {
533 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
534 reg = <0x0 0xff650000 0x0 0x1000>;
535 clocks = <&cru PCLK_I2C0>;
536 clock-names = "i2c";
537 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&i2c0_xfer>;
540 #address-cells = <1>;
541 #size-cells = <0>;
542 status = "disabled";
543 };
544
545 i2c1: i2c@ff660000 {
546 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
547 reg = <0x0 0xff660000 0x0 0x1000>;
548 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
549 #address-cells = <1>;
550 #size-cells = <0>;
551 clock-names = "i2c";
552 clocks = <&cru PCLK_I2C1>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c1_xfer>;
555 status = "disabled";
556 };
557
558 pwm0: pwm@ff680000 {
559 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
560 reg = <0x0 0xff680000 0x0 0x10>;
561 #pwm-cells = <3>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&pwm0_pin>;
564 clocks = <&cru PCLK_PWM1>;
565 status = "disabled";
566 };
567
568 pwm1: pwm@ff680010 {
569 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
570 reg = <0x0 0xff680010 0x0 0x10>;
571 #pwm-cells = <3>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&pwm1_pin>;
574 clocks = <&cru PCLK_PWM1>;
575 status = "disabled";
576 };
577
578 pwm2: pwm@ff680020 {
579 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
580 reg = <0x0 0xff680020 0x0 0x10>;
581 #pwm-cells = <3>;
582 clocks = <&cru PCLK_PWM1>;
583 status = "disabled";
584 };
585
586 pwm3: pwm@ff680030 {
587 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
588 reg = <0x0 0xff680030 0x0 0x10>;
589 #pwm-cells = <3>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&pwm3_pin>;
592 clocks = <&cru PCLK_PWM1>;
593 status = "disabled";
594 };
595
596 uart2: serial@ff690000 {
597 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
598 reg = <0x0 0xff690000 0x0 0x100>;
599 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
600 clock-names = "baudclk", "apb_pclk";
601 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&uart2_xfer>;
604 reg-shift = <2>;
605 reg-io-width = <4>;
606 status = "disabled";
607 };
608
609 mbox: mbox@ff6b0000 {
610 compatible = "rockchip,rk3368-mailbox";
611 reg = <0x0 0xff6b0000 0x0 0x1000>;
612 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&cru PCLK_MAILBOX>;
617 clock-names = "pclk_mailbox";
618 #mbox-cells = <1>;
619 status = "disabled";
620 };
621
622 pmu: power-management@ff730000 {
623 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
624 reg = <0x0 0xff730000 0x0 0x1000>;
625
626 power: power-controller {
627 compatible = "rockchip,rk3368-power-controller";
628 #power-domain-cells = <1>;
629 #address-cells = <1>;
630 #size-cells = <0>;
631
632 /*
633 * Note: Although SCLK_* are the working clocks
634 * of device without including on the NOC, needed for
635 * synchronous reset.
636 *
637 * The clocks on the which NOC:
638 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
639 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
640 * ACLK_RGA is on ACLK_RGA_NIU.
641 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
642 *
643 * Which clock are device clocks:
644 * clocks devices
645 * *_IEP IEP:Image Enhancement Processor
646 * *_ISP ISP:Image Signal Processing
647 * *_VIP VIP:Video Input Processor
648 * *_VOP* VOP:Visual Output Processor
649 * *_RGA RGA
650 * *_EDP* EDP
651 * *_DPHY* LVDS
652 * *_HDMI HDMI
653 * *_MIPI_* MIPI
654 */
655 power-domain@RK3368_PD_VIO {
656 reg = <RK3368_PD_VIO>;
657 clocks = <&cru ACLK_IEP>,
658 <&cru ACLK_ISP>,
659 <&cru ACLK_VIP>,
660 <&cru ACLK_RGA>,
661 <&cru ACLK_VOP>,
662 <&cru ACLK_VOP_IEP>,
663 <&cru DCLK_VOP>,
664 <&cru HCLK_IEP>,
665 <&cru HCLK_ISP>,
666 <&cru HCLK_RGA>,
667 <&cru HCLK_VIP>,
668 <&cru HCLK_VOP>,
669 <&cru HCLK_VIO_HDCPMMU>,
670 <&cru PCLK_EDP_CTRL>,
671 <&cru PCLK_HDMI_CTRL>,
672 <&cru PCLK_HDCP>,
673 <&cru PCLK_ISP>,
674 <&cru PCLK_VIP>,
675 <&cru PCLK_DPHYRX>,
676 <&cru PCLK_DPHYTX0>,
677 <&cru PCLK_MIPI_CSI>,
678 <&cru PCLK_MIPI_DSI0>,
679 <&cru SCLK_VOP0_PWM>,
680 <&cru SCLK_EDP_24M>,
681 <&cru SCLK_EDP>,
682 <&cru SCLK_HDCP>,
683 <&cru SCLK_ISP>,
684 <&cru SCLK_RGA>,
685 <&cru SCLK_HDMI_CEC>,
686 <&cru SCLK_HDMI_HDCP>;
687 pm_qos = <&qos_iep>,
688 <&qos_isp_r0>,
689 <&qos_isp_r1>,
690 <&qos_isp_w0>,
691 <&qos_isp_w1>,
692 <&qos_vip>,
693 <&qos_vop>,
694 <&qos_rga_r>,
695 <&qos_rga_w>;
696 #power-domain-cells = <0>;
697 };
698
699 /*
700 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
701 * (video endecoder & decoder) clocks that on the
702 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
703 */
704 power-domain@RK3368_PD_VIDEO {
705 reg = <RK3368_PD_VIDEO>;
706 clocks = <&cru ACLK_VIDEO>,
707 <&cru HCLK_VIDEO>,
708 <&cru SCLK_HEVC_CABAC>,
709 <&cru SCLK_HEVC_CORE>;
710 pm_qos = <&qos_hevc_r>,
711 <&qos_vpu_r>,
712 <&qos_vpu_w>;
713 #power-domain-cells = <0>;
714 };
715
716 /*
717 * Note: ACLK_GPU is the GPU clock,
718 * and on the ACLK_GPU_NIU (NOC).
719 */
720 power-domain@RK3368_PD_GPU_1 {
721 reg = <RK3368_PD_GPU_1>;
722 clocks = <&cru ACLK_GPU_CFG>,
723 <&cru ACLK_GPU_MEM>,
724 <&cru SCLK_GPU_CORE>;
725 pm_qos = <&qos_gpu>;
726 #power-domain-cells = <0>;
727 };
728 };
729 };
730
731 pmugrf: syscon@ff738000 {
732 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
733 reg = <0x0 0xff738000 0x0 0x1000>;
734
735 pmu_io_domains: io-domains {
736 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
737 status = "disabled";
738 };
739
740 reboot-mode {
741 compatible = "syscon-reboot-mode";
742 offset = <0x200>;
743 mode-normal = <BOOT_NORMAL>;
744 mode-recovery = <BOOT_RECOVERY>;
745 mode-bootloader = <BOOT_FASTBOOT>;
746 mode-loader = <BOOT_BL_DOWNLOAD>;
747 };
748 };
749
750 cru: clock-controller@ff760000 {
751 compatible = "rockchip,rk3368-cru";
752 reg = <0x0 0xff760000 0x0 0x1000>;
753 clocks = <&xin24m>;
754 clock-names = "xin24m";
755 rockchip,grf = <&grf>;
756 #clock-cells = <1>;
757 #reset-cells = <1>;
758 };
759
760 grf: syscon@ff770000 {
761 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
762 reg = <0x0 0xff770000 0x0 0x1000>;
763
764 io_domains: io-domains {
765 compatible = "rockchip,rk3368-io-voltage-domain";
766 status = "disabled";
767 };
768 };
769
770 wdt: watchdog@ff800000 {
771 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
772 reg = <0x0 0xff800000 0x0 0x100>;
773 clocks = <&cru PCLK_WDT>;
774 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
775 status = "disabled";
776 };
777
778 timer0: timer@ff810000 {
779 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
780 reg = <0x0 0xff810000 0x0 0x20>;
781 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
783 clock-names = "pclk", "timer";
784 };
785
786 spdif: spdif@ff880000 {
787 compatible = "rockchip,rk3368-spdif";
788 reg = <0x0 0xff880000 0x0 0x1000>;
789 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
791 clock-names = "mclk", "hclk";
792 dmas = <&dmac_bus 3>;
793 dma-names = "tx";
794 pinctrl-names = "default";
795 pinctrl-0 = <&spdif_tx>;
796 #sound-dai-cells = <0>;
797 status = "disabled";
798 };
799
800 i2s_2ch: i2s-2ch@ff890000 {
801 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
802 reg = <0x0 0xff890000 0x0 0x1000>;
803 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
804 clock-names = "i2s_clk", "i2s_hclk";
805 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
806 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
807 dma-names = "tx", "rx";
808 #sound-dai-cells = <0>;
809 status = "disabled";
810 };
811
812 i2s_8ch: i2s-8ch@ff898000 {
813 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
814 reg = <0x0 0xff898000 0x0 0x1000>;
815 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
816 clock-names = "i2s_clk", "i2s_hclk";
817 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
818 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
819 dma-names = "tx", "rx";
820 pinctrl-names = "default";
821 pinctrl-0 = <&i2s_8ch_bus>;
822 #sound-dai-cells = <0>;
823 status = "disabled";
824 };
825
826 iep_mmu: iommu@ff900800 {
827 compatible = "rockchip,iommu";
828 reg = <0x0 0xff900800 0x0 0x100>;
829 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
831 clock-names = "aclk", "iface";
832 power-domains = <&power RK3368_PD_VIO>;
833 #iommu-cells = <0>;
834 status = "disabled";
835 };
836
837 isp_mmu: iommu@ff914000 {
838 compatible = "rockchip,iommu";
839 reg = <0x0 0xff914000 0x0 0x100>,
840 <0x0 0xff915000 0x0 0x100>;
841 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
843 clock-names = "aclk", "iface";
844 #iommu-cells = <0>;
845 power-domains = <&power RK3368_PD_VIO>;
846 rockchip,disable-mmu-reset;
847 status = "disabled";
848 };
849
850 vop_mmu: iommu@ff930300 {
851 compatible = "rockchip,iommu";
852 reg = <0x0 0xff930300 0x0 0x100>;
853 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
855 clock-names = "aclk", "iface";
856 power-domains = <&power RK3368_PD_VIO>;
857 #iommu-cells = <0>;
858 status = "disabled";
859 };
860
861 hevc_mmu: iommu@ff9a0440 {
862 compatible = "rockchip,iommu";
863 reg = <0x0 0xff9a0440 0x0 0x40>,
864 <0x0 0xff9a0480 0x0 0x40>;
865 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
867 clock-names = "aclk", "iface";
868 #iommu-cells = <0>;
869 status = "disabled";
870 };
871
872 vpu_mmu: iommu@ff9a0800 {
873 compatible = "rockchip,iommu";
874 reg = <0x0 0xff9a0800 0x0 0x100>;
875 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
876 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
877 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
878 clock-names = "aclk", "iface";
879 #iommu-cells = <0>;
880 status = "disabled";
881 };
882
883 qos_iep: qos@ffad0000 {
884 compatible = "rockchip,rk3368-qos", "syscon";
885 reg = <0x0 0xffad0000 0x0 0x20>;
886 };
887
888 qos_isp_r0: qos@ffad0080 {
889 compatible = "rockchip,rk3368-qos", "syscon";
890 reg = <0x0 0xffad0080 0x0 0x20>;
891 };
892
893 qos_isp_r1: qos@ffad0100 {
894 compatible = "rockchip,rk3368-qos", "syscon";
895 reg = <0x0 0xffad0100 0x0 0x20>;
896 };
897
898 qos_isp_w0: qos@ffad0180 {
899 compatible = "rockchip,rk3368-qos", "syscon";
900 reg = <0x0 0xffad0180 0x0 0x20>;
901 };
902
903 qos_isp_w1: qos@ffad0200 {
904 compatible = "rockchip,rk3368-qos", "syscon";
905 reg = <0x0 0xffad0200 0x0 0x20>;
906 };
907
908 qos_vip: qos@ffad0280 {
909 compatible = "rockchip,rk3368-qos", "syscon";
910 reg = <0x0 0xffad0280 0x0 0x20>;
911 };
912
913 qos_vop: qos@ffad0300 {
914 compatible = "rockchip,rk3368-qos", "syscon";
915 reg = <0x0 0xffad0300 0x0 0x20>;
916 };
917
918 qos_rga_r: qos@ffad0380 {
919 compatible = "rockchip,rk3368-qos", "syscon";
920 reg = <0x0 0xffad0380 0x0 0x20>;
921 };
922
923 qos_rga_w: qos@ffad0400 {
924 compatible = "rockchip,rk3368-qos", "syscon";
925 reg = <0x0 0xffad0400 0x0 0x20>;
926 };
927
928 qos_hevc_r: qos@ffae0000 {
929 compatible = "rockchip,rk3368-qos", "syscon";
930 reg = <0x0 0xffae0000 0x0 0x20>;
931 };
932
933 qos_vpu_r: qos@ffae0100 {
934 compatible = "rockchip,rk3368-qos", "syscon";
935 reg = <0x0 0xffae0100 0x0 0x20>;
936 };
937
938 qos_vpu_w: qos@ffae0180 {
939 compatible = "rockchip,rk3368-qos", "syscon";
940 reg = <0x0 0xffae0180 0x0 0x20>;
941 };
942
943 qos_gpu: qos@ffaf0000 {
944 compatible = "rockchip,rk3368-qos", "syscon";
945 reg = <0x0 0xffaf0000 0x0 0x20>;
946 };
947
948 efuse256: efuse@ffb00000 {
949 compatible = "rockchip,rk3368-efuse";
950 reg = <0x0 0xffb00000 0x0 0x20>;
951 #address-cells = <1>;
952 #size-cells = <1>;
953 clocks = <&cru PCLK_EFUSE256>;
954 clock-names = "pclk_efuse";
955
956 cpu_leakage: cpu-leakage@17 {
957 reg = <0x17 0x1>;
958 };
959 temp_adjust: temp-adjust@1f {
960 reg = <0x1f 0x1>;
961 };
962 };
963
964 gic: interrupt-controller@ffb71000 {
965 compatible = "arm,gic-400";
966 interrupt-controller;
967 #interrupt-cells = <3>;
968 #address-cells = <0>;
969
970 reg = <0x0 0xffb71000 0x0 0x1000>,
971 <0x0 0xffb72000 0x0 0x2000>,
972 <0x0 0xffb74000 0x0 0x2000>,
973 <0x0 0xffb76000 0x0 0x2000>;
974 interrupts = <GIC_PPI 9
975 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
976 };
977
978 pinctrl: pinctrl {
979 compatible = "rockchip,rk3368-pinctrl";
980 rockchip,grf = <&grf>;
981 rockchip,pmu = <&pmugrf>;
982 #address-cells = <0x2>;
983 #size-cells = <0x2>;
984 ranges;
985
986 gpio0: gpio@ff750000 {
987 compatible = "rockchip,gpio-bank";
988 reg = <0x0 0xff750000 0x0 0x100>;
989 clocks = <&cru PCLK_GPIO0>;
990 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
991
992 gpio-controller;
993 #gpio-cells = <0x2>;
994
995 interrupt-controller;
996 #interrupt-cells = <0x2>;
997 };
998
999 gpio1: gpio@ff780000 {
1000 compatible = "rockchip,gpio-bank";
1001 reg = <0x0 0xff780000 0x0 0x100>;
1002 clocks = <&cru PCLK_GPIO1>;
1003 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1004
1005 gpio-controller;
1006 #gpio-cells = <0x2>;
1007
1008 interrupt-controller;
1009 #interrupt-cells = <0x2>;
1010 };
1011
1012 gpio2: gpio@ff790000 {
1013 compatible = "rockchip,gpio-bank";
1014 reg = <0x0 0xff790000 0x0 0x100>;
1015 clocks = <&cru PCLK_GPIO2>;
1016 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1017
1018 gpio-controller;
1019 #gpio-cells = <0x2>;
1020
1021 interrupt-controller;
1022 #interrupt-cells = <0x2>;
1023 };
1024
1025 gpio3: gpio@ff7a0000 {
1026 compatible = "rockchip,gpio-bank";
1027 reg = <0x0 0xff7a0000 0x0 0x100>;
1028 clocks = <&cru PCLK_GPIO3>;
1029 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1030
1031 gpio-controller;
1032 #gpio-cells = <0x2>;
1033
1034 interrupt-controller;
1035 #interrupt-cells = <0x2>;
1036 };
1037
1038 pcfg_pull_up: pcfg-pull-up {
1039 bias-pull-up;
1040 };
1041
1042 pcfg_pull_down: pcfg-pull-down {
1043 bias-pull-down;
1044 };
1045
1046 pcfg_pull_none: pcfg-pull-none {
1047 bias-disable;
1048 };
1049
1050 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1051 bias-disable;
1052 drive-strength = <12>;
1053 };
1054
1055 emmc {
1056 emmc_clk: emmc-clk {
1057 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
1058 };
1059
1060 emmc_cmd: emmc-cmd {
1061 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
1062 };
1063
1064 emmc_pwr: emmc-pwr {
1065 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
1066 };
1067
1068 emmc_bus1: emmc-bus1 {
1069 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
1070 };
1071
1072 emmc_bus4: emmc-bus4 {
1073 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1074 <1 RK_PC3 2 &pcfg_pull_up>,
1075 <1 RK_PC4 2 &pcfg_pull_up>,
1076 <1 RK_PC5 2 &pcfg_pull_up>;
1077 };
1078
1079 emmc_bus8: emmc-bus8 {
1080 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1081 <1 RK_PC3 2 &pcfg_pull_up>,
1082 <1 RK_PC4 2 &pcfg_pull_up>,
1083 <1 RK_PC5 2 &pcfg_pull_up>,
1084 <1 RK_PC6 2 &pcfg_pull_up>,
1085 <1 RK_PC7 2 &pcfg_pull_up>,
1086 <1 RK_PD0 2 &pcfg_pull_up>,
1087 <1 RK_PD1 2 &pcfg_pull_up>;
1088 };
1089 };
1090
1091 gmac {
1092 rgmii_pins: rgmii-pins {
1093 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1094 <3 RK_PD0 1 &pcfg_pull_none>,
1095 <3 RK_PC3 1 &pcfg_pull_none>,
1096 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1097 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1098 <3 RK_PB2 1 &pcfg_pull_none_12ma>,
1099 <3 RK_PB6 1 &pcfg_pull_none_12ma>,
1100 <3 RK_PD4 1 &pcfg_pull_none_12ma>,
1101 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1102 <3 RK_PB7 1 &pcfg_pull_none>,
1103 <3 RK_PC0 1 &pcfg_pull_none>,
1104 <3 RK_PC1 1 &pcfg_pull_none>,
1105 <3 RK_PC2 1 &pcfg_pull_none>,
1106 <3 RK_PD1 1 &pcfg_pull_none>,
1107 <3 RK_PC4 1 &pcfg_pull_none>;
1108 };
1109
1110 rmii_pins: rmii-pins {
1111 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1112 <3 RK_PD0 1 &pcfg_pull_none>,
1113 <3 RK_PC3 1 &pcfg_pull_none>,
1114 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1115 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1116 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1117 <3 RK_PB7 1 &pcfg_pull_none>,
1118 <3 RK_PC0 1 &pcfg_pull_none>,
1119 <3 RK_PC4 1 &pcfg_pull_none>,
1120 <3 RK_PC5 1 &pcfg_pull_none>;
1121 };
1122 };
1123
1124 i2c0 {
1125 i2c0_xfer: i2c0-xfer {
1126 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1127 <0 RK_PA7 1 &pcfg_pull_none>;
1128 };
1129 };
1130
1131 i2c1 {
1132 i2c1_xfer: i2c1-xfer {
1133 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
1134 <2 RK_PC6 1 &pcfg_pull_none>;
1135 };
1136 };
1137
1138 i2c2 {
1139 i2c2_xfer: i2c2-xfer {
1140 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
1141 <3 RK_PD7 2 &pcfg_pull_none>;
1142 };
1143 };
1144
1145 i2c3 {
1146 i2c3_xfer: i2c3-xfer {
1147 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
1148 <1 RK_PC1 1 &pcfg_pull_none>;
1149 };
1150 };
1151
1152 i2c4 {
1153 i2c4_xfer: i2c4-xfer {
1154 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
1155 <3 RK_PD1 2 &pcfg_pull_none>;
1156 };
1157 };
1158
1159 i2c5 {
1160 i2c5_xfer: i2c5-xfer {
1161 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
1162 <3 RK_PD3 2 &pcfg_pull_none>;
1163 };
1164 };
1165
1166 i2s {
1167 i2s_8ch_bus: i2s-8ch-bus {
1168 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1169 <2 RK_PB5 1 &pcfg_pull_none>,
1170 <2 RK_PB6 1 &pcfg_pull_none>,
1171 <2 RK_PB7 1 &pcfg_pull_none>,
1172 <2 RK_PC0 1 &pcfg_pull_none>,
1173 <2 RK_PC1 1 &pcfg_pull_none>,
1174 <2 RK_PC2 1 &pcfg_pull_none>,
1175 <2 RK_PC3 1 &pcfg_pull_none>,
1176 <2 RK_PC4 1 &pcfg_pull_none>;
1177 };
1178 };
1179
1180 pwm0 {
1181 pwm0_pin: pwm0-pin {
1182 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
1183 };
1184 };
1185
1186 pwm1 {
1187 pwm1_pin: pwm1-pin {
1188 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1189 };
1190 };
1191
1192 pwm3 {
1193 pwm3_pin: pwm3-pin {
1194 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
1195 };
1196 };
1197
1198 sdio0 {
1199 sdio0_bus1: sdio0-bus1 {
1200 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
1201 };
1202
1203 sdio0_bus4: sdio0-bus4 {
1204 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
1205 <2 RK_PD5 1 &pcfg_pull_up>,
1206 <2 RK_PD6 1 &pcfg_pull_up>,
1207 <2 RK_PD7 1 &pcfg_pull_up>;
1208 };
1209
1210 sdio0_cmd: sdio0-cmd {
1211 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
1212 };
1213
1214 sdio0_clk: sdio0-clk {
1215 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
1216 };
1217
1218 sdio0_cd: sdio0-cd {
1219 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
1220 };
1221
1222 sdio0_wp: sdio0-wp {
1223 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
1224 };
1225
1226 sdio0_pwr: sdio0-pwr {
1227 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
1228 };
1229
1230 sdio0_bkpwr: sdio0-bkpwr {
1231 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
1232 };
1233
1234 sdio0_int: sdio0-int {
1235 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
1236 };
1237 };
1238
1239 sdmmc {
1240 sdmmc_clk: sdmmc-clk {
1241 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1242 };
1243
1244 sdmmc_cmd: sdmmc-cmd {
1245 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1246 };
1247
1248 sdmmc_cd: sdmmc-cd {
1249 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1250 };
1251
1252 sdmmc_bus1: sdmmc-bus1 {
1253 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
1254 };
1255
1256 sdmmc_bus4: sdmmc-bus4 {
1257 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
1258 <2 RK_PA6 1 &pcfg_pull_up>,
1259 <2 RK_PA7 1 &pcfg_pull_up>,
1260 <2 RK_PB0 1 &pcfg_pull_up>;
1261 };
1262 };
1263
1264 spdif {
1265 spdif_tx: spdif-tx {
1266 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1267 };
1268 };
1269
1270 spi0 {
1271 spi0_clk: spi0-clk {
1272 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
1273 };
1274 spi0_cs0: spi0-cs0 {
1275 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
1276 };
1277 spi0_cs1: spi0-cs1 {
1278 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
1279 };
1280 spi0_tx: spi0-tx {
1281 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
1282 };
1283 spi0_rx: spi0-rx {
1284 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
1285 };
1286 };
1287
1288 spi1 {
1289 spi1_clk: spi1-clk {
1290 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
1291 };
1292 spi1_cs0: spi1-cs0 {
1293 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
1294 };
1295 spi1_cs1: spi1-cs1 {
1296 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
1297 };
1298 spi1_rx: spi1-rx {
1299 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
1300 };
1301 spi1_tx: spi1-tx {
1302 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
1303 };
1304 };
1305
1306 spi2 {
1307 spi2_clk: spi2-clk {
1308 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1309 };
1310 spi2_cs0: spi2-cs0 {
1311 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1312 };
1313 spi2_rx: spi2-rx {
1314 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1315 };
1316 spi2_tx: spi2-tx {
1317 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1318 };
1319 };
1320
1321 tsadc {
1322 otp_pin: otp-pin {
1323 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1324 };
1325
1326 otp_out: otp-out {
1327 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1328 };
1329 };
1330
1331 uart0 {
1332 uart0_xfer: uart0-xfer {
1333 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
1334 <2 RK_PD1 1 &pcfg_pull_none>;
1335 };
1336
1337 uart0_cts: uart0-cts {
1338 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
1339 };
1340
1341 uart0_rts: uart0-rts {
1342 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
1343 };
1344 };
1345
1346 uart1 {
1347 uart1_xfer: uart1-xfer {
1348 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1349 <0 RK_PC5 3 &pcfg_pull_none>;
1350 };
1351
1352 uart1_cts: uart1-cts {
1353 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1354 };
1355
1356 uart1_rts: uart1-rts {
1357 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1358 };
1359 };
1360
1361 uart2 {
1362 uart2_xfer: uart2-xfer {
1363 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
1364 <2 RK_PA5 2 &pcfg_pull_none>;
1365 };
1366 /* no rts / cts for uart2 */
1367 };
1368
1369 uart3 {
1370 uart3_xfer: uart3-xfer {
1371 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
1372 <3 RK_PD6 3 &pcfg_pull_none>;
1373 };
1374
1375 uart3_cts: uart3-cts {
1376 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
1377 };
1378
1379 uart3_rts: uart3-rts {
1380 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
1381 };
1382 };
1383
1384 uart4 {
1385 uart4_xfer: uart4-xfer {
1386 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1387 <0 RK_PD2 3 &pcfg_pull_none>;
1388 };
1389
1390 uart4_cts: uart4-cts {
1391 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1392 };
1393
1394 uart4_rts: uart4-rts {
1395 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
1396 };
1397 };
1398 };
1399 };
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