1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
4 * Copyright (c) 2019 Markus Reichl <m.reichl@fivetechno.de>
5 */
6
7 /dts-v1/;
8 #include "rk3399-roc-pc.dtsi"
9
10 / {
11 model = "Firefly ROC-RK3399-PC Mezzanine Board";
12 compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
13
14 aliases {
15 mmc2 = &sdio0;
16 };
17
18 /* MP8009 PoE PD */
19 poe_12v: poe-12v {
20 compatible = "regulator-fixed";
21 regulator-name = "poe_12v";
22 regulator-always-on;
23 regulator-boot-on;
24 regulator-min-microvolt = <12000000>;
25 regulator-max-microvolt = <12000000>;
26 };
27
28 vcc3v3_ngff: vcc3v3-ngff {
29 compatible = "regulator-fixed";
30 regulator-name = "vcc3v3_ngff";
31 enable-active-high;
32 gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
33 pinctrl-names = "default";
34 pinctrl-0 = <&vcc3v3_ngff_en>;
35 regulator-always-on;
36 regulator-boot-on;
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 vin-supply = <&sys_12v>;
40 };
41
42 vcc3v3_pcie: vcc3v3-pcie {
43 compatible = "regulator-fixed";
44 regulator-name = "vcc3v3_pcie";
45 enable-active-high;
46 gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&vcc3v3_pcie_en>;
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
51 vin-supply = <&sys_12v>;
52 };
53 };
54
55 &sys_12v {
56 vin-supply = <&poe_12v>;
57 };
58
59 &pcie_phy {
60 status = "okay";
61 };
62
63 &pcie0 {
64 ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
65 num-lanes = <4>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&pcie_perst>;
68 vpcie3v3-supply = <&vcc3v3_pcie>;
69 vpcie1v8-supply = <&vcc1v8_pmu>;
70 vpcie0v9-supply = <&vcca_0v9>;
71 status = "okay";
72 };
73
74 &pinctrl {
75 ngff {
76 vcc3v3_ngff_en: vcc3v3-ngff-en {
77 rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
78 };
79 };
80
81 pcie {
82 vcc3v3_pcie_en: vcc3v3-pcie-en {
83 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
84 };
85
86 pcie_perst: pcie-perst {
87 rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
88 };
89 };
90 };
91
92 &sdio0 {
93 bus-width = <4>;
94 cap-sd-highspeed;
95 cap-sdio-irq;
96 keep-power-in-suspend;
97 mmc-pwrseq = <&sdio_pwrseq>;
98 non-removable;
99 pinctrl-names = "default";
100 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
101 sd-uhs-sdr104;
102 vmmc-supply = <&vcc3v3_ngff>;
103 vqmmc-supply = <&vcc_1v8>;
104 status = "okay";
105 };
106
107 &uart0 {
108 pinctrl-names = "default";
109 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
110 status = "okay";
111 };
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