1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Author: Frank Wunderlich <frank-w@public-files.de>
4 *
5 */
6
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,vop2.h>
12 #include "rk3568.dtsi"
13
14 / {
15 model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
16 compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568";
17
18 aliases {
19 ethernet0 = &gmac0;
20 ethernet1 = &gmac1;
21 mmc0 = &sdmmc0;
22 mmc1 = &sdhci;
23 };
24
25 chosen: chosen {
26 stdout-path = "serial2:1500000n8";
27 };
28
29 leds {
30 compatible = "gpio-leds";
31 pinctrl-names = "default";
32 pinctrl-0 = <&blue_led_pin &green_led_pin>;
33
34 blue_led: led-0 {
35 color = <LED_COLOR_ID_BLUE>;
36 default-state = "off";
37 function = LED_FUNCTION_STATUS;
38 gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
39 };
40
41 green_led: led-1 {
42 color = <LED_COLOR_ID_GREEN>;
43 default-state = "on";
44 function = LED_FUNCTION_POWER;
45 gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
46 };
47 };
48
49 dc_12v: dc-12v-regulator {
50 compatible = "regulator-fixed";
51 regulator-name = "dc_12v";
52 regulator-always-on;
53 regulator-boot-on;
54 regulator-min-microvolt = <12000000>;
55 regulator-max-microvolt = <12000000>;
56 };
57
58 hdmi-con {
59 compatible = "hdmi-connector";
60 type = "a";
61
62 port {
63 hdmi_con_in: endpoint {
64 remote-endpoint = <&hdmi_out_con>;
65 };
66 };
67 };
68
69 ir-receiver {
70 compatible = "gpio-ir-receiver";
71 gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&ir_receiver_pin>;
74 };
75
76 vcc3v3_sys: vcc3v3-sys-regulator {
77 compatible = "regulator-fixed";
78 regulator-name = "vcc3v3_sys";
79 regulator-always-on;
80 regulator-boot-on;
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 vin-supply = <&dc_12v>;
84 };
85
86 vcc5v0_sys: vcc5v0-sys-regulator {
87 compatible = "regulator-fixed";
88 regulator-name = "vcc5v0_sys";
89 regulator-always-on;
90 regulator-boot-on;
91 regulator-min-microvolt = <5000000>;
92 regulator-max-microvolt = <5000000>;
93 vin-supply = <&dc_12v>;
94 };
95
96 pcie30_avdd0v9: pcie30-avdd0v9-regulator {
97 compatible = "regulator-fixed";
98 regulator-name = "pcie30_avdd0v9";
99 regulator-always-on;
100 regulator-boot-on;
101 regulator-min-microvolt = <900000>;
102 regulator-max-microvolt = <900000>;
103 vin-supply = <&vcc3v3_sys>;
104 };
105
106 pcie30_avdd1v8: pcie30-avdd1v8-regulator {
107 compatible = "regulator-fixed";
108 regulator-name = "pcie30_avdd1v8";
109 regulator-always-on;
110 regulator-boot-on;
111 regulator-min-microvolt = <1800000>;
112 regulator-max-microvolt = <1800000>;
113 vin-supply = <&vcc3v3_sys>;
114 };
115
116 /* pi6c pcie clock generator feeds both ports */
117 vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
118 compatible = "regulator-fixed";
119 regulator-name = "vcc3v3_pcie";
120 regulator-min-microvolt = <3300000>;
121 regulator-max-microvolt = <3300000>;
122 enable-active-high;
123 gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
124 startup-delay-us = <200000>;
125 vin-supply = <&vcc5v0_sys>;
126 };
127
128 /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
129 vcc3v3_minipcie: vcc3v3-minipcie-regulator {
130 compatible = "regulator-fixed";
131 regulator-name = "vcc3v3_minipcie";
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 enable-active-high;
135 gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&minipcie_enable_h>;
138 startup-delay-us = <50000>;
139 vin-supply = <&vcc3v3_pi6c_05>;
140 };
141
142 /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
143 vcc3v3_ngff: vcc3v3-ngff-regulator {
144 compatible = "regulator-fixed";
145 regulator-name = "vcc3v3_ngff";
146 regulator-min-microvolt = <3300000>;
147 regulator-max-microvolt = <3300000>;
148 enable-active-high;
149 gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&ngffpcie_enable_h>;
152 startup-delay-us = <50000>;
153 vin-supply = <&vcc3v3_pi6c_05>;
154 };
155
156 vcc5v0_usb: vcc5v0-usb-regulator {
157 compatible = "regulator-fixed";
158 regulator-name = "vcc5v0_usb";
159 regulator-always-on;
160 regulator-boot-on;
161 regulator-min-microvolt = <5000000>;
162 regulator-max-microvolt = <5000000>;
163 vin-supply = <&dc_12v>;
164 };
165
166 vcc5v0_usb_host: vcc5v0-usb-host-regulator {
167 compatible = "regulator-fixed";
168 enable-active-high;
169 gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&vcc5v0_usb_host_en>;
172 regulator-name = "vcc5v0_usb_host";
173 regulator-min-microvolt = <5000000>;
174 regulator-max-microvolt = <5000000>;
175 vin-supply = <&vcc5v0_usb>;
176 };
177
178 vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
179 compatible = "regulator-fixed";
180 enable-active-high;
181 gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&vcc5v0_usb_otg_en>;
184 regulator-name = "vcc5v0_usb_otg";
185 regulator-min-microvolt = <5000000>;
186 regulator-max-microvolt = <5000000>;
187 vin-supply = <&vcc5v0_usb>;
188 };
189 };
190
191 &combphy0 {
192 /* used for USB3 */
193 status = "okay";
194 };
195
196 &combphy1 {
197 /* used for USB3 */
198 status = "okay";
199 };
200
201 &combphy2 {
202 /* used for SATA */
203 status = "okay";
204 };
205
206 &gmac0 {
207 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
208 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
209 clock_in_out = "input";
210 phy-mode = "rgmii";
211 pinctrl-names = "default";
212 pinctrl-0 = <&gmac0_miim
213 &gmac0_tx_bus2
214 &gmac0_rx_bus2
215 &gmac0_rgmii_clk
216 &gmac0_rgmii_bus>;
217 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
218 snps,reset-active-low;
219 /* Reset time is 20ms, 100ms for rtl8211f */
220 snps,reset-delays-us = <0 20000 100000>;
221 tx_delay = <0x4f>;
222 rx_delay = <0x0f>;
223 status = "okay";
224
225 fixed-link {
226 speed = <1000>;
227 full-duplex;
228 pause;
229 };
230 };
231
232 &gmac1 {
233 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
234 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
235 clock_in_out = "output";
236 phy-handle = <&rgmii_phy1>;
237 phy-mode = "rgmii";
238 pinctrl-names = "default";
239 pinctrl-0 = <&gmac1m1_miim
240 &gmac1m1_tx_bus2
241 &gmac1m1_rx_bus2
242 &gmac1m1_rgmii_clk
243 &gmac1m1_rgmii_bus>;
244
245 snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
246 snps,reset-active-low;
247 /* Reset time is 20ms, 100ms for rtl8211f */
248 snps,reset-delays-us = <0 20000 100000>;
249
250 tx_delay = <0x3c>;
251 rx_delay = <0x2f>;
252
253 status = "okay";
254 };
255
256 &gpu {
257 mali-supply = <&vdd_gpu>;
258 status = "okay";
259 };
260
261 &hdmi {
262 avdd-0v9-supply = <&vdda0v9_image>;
263 avdd-1v8-supply = <&vcca1v8_image>;
264 status = "okay";
265 };
266
267 &hdmi_in {
268 hdmi_in_vp0: endpoint {
269 remote-endpoint = <&vp0_out_hdmi>;
270 };
271 };
272
273 &hdmi_out {
274 hdmi_out_con: endpoint {
275 remote-endpoint = <&hdmi_con_in>;
276 };
277 };
278
279 &hdmi_sound {
280 status = "okay";
281 };
282
283 &i2c0 {
284 status = "okay";
285
286 rk809: pmic@20 {
287 compatible = "rockchip,rk809";
288 reg = <0x20>;
289 interrupt-parent = <&gpio0>;
290 interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
291 #clock-cells = <1>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pmic_int>;
294 rockchip,system-power-controller;
295 vcc1-supply = <&vcc3v3_sys>;
296 vcc2-supply = <&vcc3v3_sys>;
297 vcc3-supply = <&vcc3v3_sys>;
298 vcc4-supply = <&vcc3v3_sys>;
299 vcc5-supply = <&vcc3v3_sys>;
300 vcc6-supply = <&vcc3v3_sys>;
301 vcc7-supply = <&vcc3v3_sys>;
302 vcc8-supply = <&vcc3v3_sys>;
303 vcc9-supply = <&vcc3v3_sys>;
304 wakeup-source;
305
306 regulators {
307 vdd_logic: DCDC_REG1 {
308 regulator-name = "vdd_logic";
309 regulator-always-on;
310 regulator-boot-on;
311 regulator-initial-mode = <0x2>;
312 regulator-min-microvolt = <500000>;
313 regulator-max-microvolt = <1350000>;
314 regulator-ramp-delay = <6001>;
315
316 regulator-state-mem {
317 regulator-off-in-suspend;
318 };
319 };
320
321 vdd_gpu: DCDC_REG2 {
322 regulator-name = "vdd_gpu";
323 regulator-always-on;
324 regulator-initial-mode = <0x2>;
325 regulator-min-microvolt = <500000>;
326 regulator-max-microvolt = <1350000>;
327 regulator-ramp-delay = <6001>;
328
329 regulator-state-mem {
330 regulator-off-in-suspend;
331 };
332 };
333
334 vcc_ddr: DCDC_REG3 {
335 regulator-name = "vcc_ddr";
336 regulator-always-on;
337 regulator-boot-on;
338 regulator-initial-mode = <0x2>;
339
340 regulator-state-mem {
341 regulator-on-in-suspend;
342 };
343 };
344
345 vdd_npu: DCDC_REG4 {
346 regulator-name = "vdd_npu";
347 regulator-initial-mode = <0x2>;
348 regulator-min-microvolt = <500000>;
349 regulator-max-microvolt = <1350000>;
350 regulator-ramp-delay = <6001>;
351
352 regulator-state-mem {
353 regulator-off-in-suspend;
354 };
355 };
356
357 vcc_1v8: DCDC_REG5 {
358 regulator-name = "vcc_1v8";
359 regulator-always-on;
360 regulator-boot-on;
361 regulator-min-microvolt = <1800000>;
362 regulator-max-microvolt = <1800000>;
363
364 regulator-state-mem {
365 regulator-off-in-suspend;
366 };
367 };
368
369 vdda0v9_image: LDO_REG1 {
370 regulator-name = "vdda0v9_image";
371 regulator-always-on;
372 regulator-min-microvolt = <900000>;
373 regulator-max-microvolt = <900000>;
374
375 regulator-state-mem {
376 regulator-off-in-suspend;
377 };
378 };
379
380 vdda_0v9: LDO_REG2 {
381 regulator-name = "vdda_0v9";
382 regulator-always-on;
383 regulator-boot-on;
384 regulator-min-microvolt = <900000>;
385 regulator-max-microvolt = <900000>;
386
387 regulator-state-mem {
388 regulator-off-in-suspend;
389 };
390 };
391
392 vdda0v9_pmu: LDO_REG3 {
393 regulator-name = "vdda0v9_pmu";
394 regulator-always-on;
395 regulator-boot-on;
396 regulator-min-microvolt = <900000>;
397 regulator-max-microvolt = <900000>;
398
399 regulator-state-mem {
400 regulator-on-in-suspend;
401 regulator-suspend-microvolt = <900000>;
402 };
403 };
404
405 vccio_acodec: LDO_REG4 {
406 regulator-name = "vccio_acodec";
407 regulator-always-on;
408 regulator-boot-on;
409 regulator-min-microvolt = <3300000>;
410 regulator-max-microvolt = <3300000>;
411
412 regulator-state-mem {
413 regulator-off-in-suspend;
414 };
415 };
416
417 vccio_sd: LDO_REG5 {
418 regulator-name = "vccio_sd";
419 regulator-always-on;
420 regulator-boot-on;
421 regulator-min-microvolt = <1800000>;
422 regulator-max-microvolt = <3300000>;
423
424 regulator-state-mem {
425 regulator-off-in-suspend;
426 };
427 };
428
429 vcc3v3_pmu: LDO_REG6 {
430 regulator-name = "vcc3v3_pmu";
431 regulator-always-on;
432 regulator-boot-on;
433 regulator-min-microvolt = <3300000>;
434 regulator-max-microvolt = <3300000>;
435
436 regulator-state-mem {
437 regulator-on-in-suspend;
438 regulator-suspend-microvolt = <3300000>;
439 };
440 };
441
442 vcca_1v8: LDO_REG7 {
443 regulator-name = "vcca_1v8";
444 regulator-always-on;
445 regulator-boot-on;
446 regulator-min-microvolt = <1800000>;
447 regulator-max-microvolt = <1800000>;
448
449 regulator-state-mem {
450 regulator-off-in-suspend;
451 };
452 };
453
454 vcca1v8_pmu: LDO_REG8 {
455 regulator-name = "vcca1v8_pmu";
456 regulator-always-on;
457 regulator-boot-on;
458 regulator-min-microvolt = <1800000>;
459 regulator-max-microvolt = <1800000>;
460
461 regulator-state-mem {
462 regulator-on-in-suspend;
463 regulator-suspend-microvolt = <1800000>;
464 };
465 };
466
467 vcca1v8_image: LDO_REG9 {
468 regulator-name = "vcca1v8_image";
469 regulator-always-on;
470 regulator-min-microvolt = <1800000>;
471 regulator-max-microvolt = <1800000>;
472
473 regulator-state-mem {
474 regulator-off-in-suspend;
475 };
476 };
477
478 vcc_3v3: SWITCH_REG1 {
479 regulator-name = "vcc_3v3";
480 regulator-always-on;
481 regulator-boot-on;
482
483 regulator-state-mem {
484 regulator-off-in-suspend;
485 };
486 };
487
488 vcc3v3_sd: SWITCH_REG2 {
489 regulator-name = "vcc3v3_sd";
490 regulator-always-on;
491
492 regulator-state-mem {
493 regulator-off-in-suspend;
494 };
495 };
496 };
497 };
498 };
499
500 &i2c3 {
501 status = "okay";
502
503 hym8563: rtc@51 {
504 compatible = "haoyu,hym8563";
505 reg = <0x51>;
506 interrupt-parent = <&gpio0>;
507 interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
508 #clock-cells = <0>;
509 clock-output-names = "rtcic_32kout";
510 pinctrl-names = "default";
511 pinctrl-0 = <&hym8563_int>;
512 wakeup-source;
513 };
514 };
515
516 &i2c5 {
517 /* pin 3 (SDA) + 4 (SCL) of header con2 */
518 status = "disabled";
519 };
520
521 &i2s0_8ch {
522 /* hdmi sound */
523 status = "okay";
524 };
525
526 &mdio0 {
527 #address-cells = <1>;
528 #size-cells = <0>;
529
530 switch@1f {
531 compatible = "mediatek,mt7531";
532 reg = <0x1f>;
533
534 ports {
535 #address-cells = <1>;
536 #size-cells = <0>;
537
538 port@1 {
539 reg = <1>;
540 label = "lan0";
541 };
542
543 port@2 {
544 reg = <2>;
545 label = "lan1";
546 };
547
548 port@3 {
549 reg = <3>;
550 label = "lan2";
551 };
552
553 port@4 {
554 reg = <4>;
555 label = "lan3";
556 };
557
558 port@5 {
559 reg = <5>;
560 label = "cpu";
561 ethernet = <&gmac0>;
562 phy-mode = "rgmii";
563
564 fixed-link {
565 speed = <1000>;
566 full-duplex;
567 pause;
568 };
569 };
570 };
571 };
572 };
573
574 &mdio1 {
575 rgmii_phy1: ethernet-phy@0 {
576 compatible = "ethernet-phy-ieee802.3-c22";
577 reg = <0x0>;
578 };
579 };
580
581 &pcie30phy {
582 data-lanes = <1 2>;
583 phy-supply = <&vcc3v3_pi6c_05>;
584 status = "okay";
585 };
586
587 &pcie3x1 {
588 /* M.2 slot */
589 num-lanes = <1>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&ngffpcie_reset_h>;
592 reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
593 vpcie3v3-supply = <&vcc3v3_ngff>;
594 status = "okay";
595 };
596
597 &pcie3x2 {
598 /* mPCIe slot */
599 num-lanes = <1>;
600 pinctrl-names = "default";
601 pinctrl-0 = <&minipcie_reset_h>;
602 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
603 vpcie3v3-supply = <&vcc3v3_minipcie>;
604 status = "okay";
605 };
606
607 &pinctrl {
608 leds {
609 blue_led_pin: blue-led-pin {
610 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
611 };
612 green_led_pin: green-led-pin {
613 rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
614 };
615 };
616
617 hym8563 {
618 hym8563_int: hym8563-int {
619 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
620 };
621 };
622
623 ir-receiver {
624 ir_receiver_pin: ir-receiver-pin {
625 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
626 };
627 };
628
629 pcie {
630 minipcie_enable_h: minipcie-enable-h {
631 rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
632 };
633
634 ngffpcie_enable_h: ngffpcie-enable-h {
635 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
636 };
637
638 minipcie_reset_h: minipcie-reset-h {
639 rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
640 };
641
642 ngffpcie_reset_h: ngffpcie-reset-h {
643 rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
644 };
645 };
646
647 pmic {
648 pmic_int: pmic_int {
649 rockchip,pins =
650 <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
651 };
652 };
653
654 usb {
655 vcc5v0_usb_host_en: vcc5v0_usb_host_en {
656 rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
657 };
658
659 vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
660 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
661 };
662 };
663 };
664
665 &pmu_io_domains {
666 pmuio1-supply = <&vcc3v3_pmu>;
667 pmuio2-supply = <&vcc3v3_pmu>;
668 vccio1-supply = <&vccio_acodec>;
669 vccio3-supply = <&vccio_sd>;
670 vccio4-supply = <&vcc_3v3>;
671 vccio5-supply = <&vcc_3v3>;
672 vccio6-supply = <&vcc_1v8>;
673 vccio7-supply = <&vcc_3v3>;
674 status = "okay";
675 };
676
677 &pwm8 {
678 /* fan 5v - gnd - pwm */
679 status = "okay";
680 };
681
682 &pwm10 {
683 /* pin 7 of header con2 */
684 status = "disabled";
685 };
686
687 &pwm11 {
688 /* pin 15 of header con2 */
689 status = "disabled";
690 };
691
692 &pwm12 {
693 /* pin 21 of header con2 */
694 /* shared with uart9 + spi3 */
695 pinctrl-0 = <&pwm12m1_pins>;
696 status = "disabled";
697 };
698
699 &pwm13 {
700 /* pin 24 of header con2 */
701 /* shared with uart9 */
702 pinctrl-0 = <&pwm13m1_pins>;
703 status = "disabled";
704 };
705
706 &pwm14 {
707 /* pin 23 of header con2 */
708 /* shared with spi3 */
709 pinctrl-0 = <&pwm14m1_pins>;
710 status = "disabled";
711 };
712
713 &pwm15 {
714 /* pin 19 of header con2 */
715 /* shared with spi3 */
716 pinctrl-0 = <&pwm15m1_pins>;
717 status = "disabled";
718 };
719
720 &saradc {
721 vref-supply = <&vcca_1v8>;
722 status = "okay";
723 };
724
725 &sata2 {
726 status = "okay";
727 };
728
729 &sdhci {
730 bus-width = <8>;
731 max-frequency = <200000000>;
732 non-removable;
733 pinctrl-names = "default";
734 pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
735 status = "okay";
736 };
737
738 &sdmmc0 {
739 bus-width = <4>;
740 cap-sd-highspeed;
741 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
742 disable-wp;
743 pinctrl-names = "default";
744 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
745 sd-uhs-sdr104;
746 vmmc-supply = <&vcc3v3_sd>;
747 vqmmc-supply = <&vccio_sd>;
748 status = "okay";
749 };
750
751 &spi3 {
752 /* pin 19 (MO) + 21 (MI) + 23 (CK) of header con2 */
753 /* shared with pwm12/14/15 and uart9 */
754 pinctrl-0 = <&spi3m1_pins>;
755 status = "disabled";
756 };
757
758 &tsadc {
759 rockchip,hw-tshut-mode = <1>;
760 rockchip,hw-tshut-polarity = <0>;
761 status = "okay";
762 };
763
764 &uart0 {
765 /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */
766 status = "disabled";
767 };
768
769 &uart2 {
770 /* debug-uart */
771 status = "okay";
772 };
773
774 &uart7 {
775 /* pin 11 (TX) + 13 (RX) of header con2 */
776 pinctrl-0 = <&uart7m1_xfer>;
777 status = "disabled";
778 };
779
780 &uart9 {
781 /* pin 21 (TX) + 24 (RX) of header con2 */
782 /* shared with pwm13 and pwm12/spi3 */
783 pinctrl-0 = <&uart9m1_xfer>;
784 status = "disabled";
785 };
786
787 &usb_host0_ehci {
788 status = "okay";
789 };
790
791 &usb_host0_ohci {
792 status = "okay";
793 };
794
795 &usb_host0_xhci {
796 dr_mode = "host";
797 status = "okay";
798 };
799
800 &usb_host1_ehci {
801 status = "okay";
802 };
803
804 &usb_host1_ohci {
805 status = "okay";
806 };
807
808 &usb_host1_xhci {
809 status = "okay";
810 };
811
812 &usb2phy0 {
813 status = "okay";
814 };
815
816 &usb2phy0_host {
817 phy-supply = <&vcc5v0_usb_host>;
818 status = "okay";
819 };
820
821 &usb2phy0_otg {
822 phy-supply = <&vcc5v0_usb_otg>;
823 status = "okay";
824 };
825
826 &usb2phy1 {
827 /* USB for PCIe/M2 */
828 status = "okay";
829 };
830
831 &usb2phy1_host {
832 status = "okay";
833 };
834
835 &usb2phy1_otg {
836 status = "okay";
837 };
838
839 &vop {
840 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
841 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
842 status = "okay";
843 };
844
845 &vop_mmu {
846 status = "okay";
847 };
848
849 &vp0 {
850 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
851 reg = <ROCKCHIP_VOP2_EP_HDMI0>;
852 remote-endpoint = <&hdmi_in_vp0>;
853 };
854 };
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