1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 * Copyright (c) 2024 Uwe Kleine-König
5 */
6
7 /dts-v1/;
8
9 #include <dt-bindings/gpio/gpio.h>
10 #include "rk3568.dtsi"
11
12 / {
13 model = "Qnap TS-433-4G NAS System 4-Bay";
14 compatible = "qnap,ts433", "rockchip,rk3568";
15 };
16
17 &gmac0 {
18 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
19 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
20 assigned-clock-rates = <0>, <125000000>;
21 clock_in_out = "output";
22 phy-handle = <&rgmii_phy0>;
23 phy-mode = "rgmii";
24 pinctrl-names = "default";
25 pinctrl-0 = <&gmac0_miim
26 &gmac0_tx_bus2
27 &gmac0_rx_bus2
28 &gmac0_rgmii_clk
29 &gmac0_rgmii_bus>;
30 rx_delay = <0x2f>;
31 tx_delay = <0x3c>;
32 status = "okay";
33 };
34
35 &i2c0 {
36 pmic@20 {
37 compatible = "rockchip,rk809";
38 reg = <0x20>;
39 interrupt-parent = <&gpio0>;
40 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
41 };
42 };
43
44 &i2c1 {
45 status = "okay";
46
47 rtc@51 {
48 compatible = "microcrystal,rv8263";
49 reg = <0x51>;
50 wakeup-source;
51 };
52 };
53
54 &mdio0 {
55 rgmii_phy0: ethernet-phy@0 {
56 compatible = "ethernet-phy-ieee802.3-c22";
57 reg = <0x0>;
58 };
59 };
60
61 &pcie30phy {
62 status = "okay";
63 };
64
65 &pcie3x1 {
66 /* The downstream dts has: rockchip,bifurcation, XXX: find out what this is about */
67 reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
68 status = "okay";
69 };
70
71 &sdhci {
72 bus-width = <8>;
73 max-frequency = <200000000>;
74 non-removable;
75 status = "okay";
76 };
77
78 /*
79 * Pins available on CN3 connector at TTL voltage level (3V3).
80 * ,_ _.
81 * |1234| 1=TX 2=VCC
82 * `----' 3=RX 4=GND
83 */
84 &uart2 {
85 status = "okay";
86 };
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