1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */
5
6 #include "rk3588-base.dtsi"
7 #include "rk3588-extra-pinctrl.dtsi"
8
9 / {
10 usb_host1_xhci: usb@fc400000 {
11 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
12 reg = <0x0 0xfc400000 0x0 0x400000>;
13 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
14 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
15 <&cru ACLK_USB3OTG1>;
16 clock-names = "ref_clk", "suspend_clk", "bus_clk";
17 dr_mode = "otg";
18 phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
19 phy-names = "usb2-phy", "usb3-phy";
20 phy_type = "utmi_wide";
21 power-domains = <&power RK3588_PD_USB>;
22 resets = <&cru SRST_A_USB3OTG1>;
23 snps,dis_enblslpm_quirk;
24 snps,dis-u2-freeclk-exists-quirk;
25 snps,dis-del-phy-power-chg-quirk;
26 snps,dis-tx-ipgap-linecheck-quirk;
27 status = "disabled";
28 };
29
30 pcie30_phy_grf: syscon@fd5b8000 {
31 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
32 reg = <0x0 0xfd5b8000 0x0 0x10000>;
33 };
34
35 pipe_phy1_grf: syscon@fd5c0000 {
36 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
37 reg = <0x0 0xfd5c0000 0x0 0x100>;
38 };
39
40 usbdpphy1_grf: syscon@fd5cc000 {
41 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
42 reg = <0x0 0xfd5cc000 0x0 0x4000>;
43 };
44
45 usb2phy1_grf: syscon@fd5d4000 {
46 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
47 reg = <0x0 0xfd5d4000 0x0 0x4000>;
48 #address-cells = <1>;
49 #size-cells = <1>;
50
51 u2phy1: usb2phy@4000 {
52 compatible = "rockchip,rk3588-usb2phy";
53 reg = <0x4000 0x10>;
54 #clock-cells = <0>;
55 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
56 clock-names = "phyclk";
57 clock-output-names = "usb480m_phy1";
58 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
59 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
60 reset-names = "phy", "apb";
61 status = "disabled";
62
63 u2phy1_otg: otg-port {
64 #phy-cells = <0>;
65 status = "disabled";
66 };
67 };
68 };
69
70 i2s8_8ch: i2s@fddc8000 {
71 compatible = "rockchip,rk3588-i2s-tdm";
72 reg = <0x0 0xfddc8000 0x0 0x1000>;
73 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
74 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
75 clock-names = "mclk_tx", "mclk_rx", "hclk";
76 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
77 assigned-clock-parents = <&cru PLL_AUPLL>;
78 dmas = <&dmac2 22>;
79 dma-names = "tx";
80 power-domains = <&power RK3588_PD_VO0>;
81 resets = <&cru SRST_M_I2S8_8CH_TX>;
82 reset-names = "tx-m";
83 #sound-dai-cells = <0>;
84 status = "disabled";
85 };
86
87 i2s6_8ch: i2s@fddf4000 {
88 compatible = "rockchip,rk3588-i2s-tdm";
89 reg = <0x0 0xfddf4000 0x0 0x1000>;
90 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
91 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
92 clock-names = "mclk_tx", "mclk_rx", "hclk";
93 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
94 assigned-clock-parents = <&cru PLL_AUPLL>;
95 dmas = <&dmac2 4>;
96 dma-names = "tx";
97 power-domains = <&power RK3588_PD_VO1>;
98 resets = <&cru SRST_M_I2S6_8CH_TX>;
99 reset-names = "tx-m";
100 #sound-dai-cells = <0>;
101 status = "disabled";
102 };
103
104 i2s7_8ch: i2s@fddf8000 {
105 compatible = "rockchip,rk3588-i2s-tdm";
106 reg = <0x0 0xfddf8000 0x0 0x1000>;
107 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
108 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
109 clock-names = "mclk_tx", "mclk_rx", "hclk";
110 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
111 assigned-clock-parents = <&cru PLL_AUPLL>;
112 dmas = <&dmac2 21>;
113 dma-names = "rx";
114 power-domains = <&power RK3588_PD_VO1>;
115 resets = <&cru SRST_M_I2S7_8CH_RX>;
116 reset-names = "rx-m";
117 #sound-dai-cells = <0>;
118 status = "disabled";
119 };
120
121 i2s10_8ch: i2s@fde00000 {
122 compatible = "rockchip,rk3588-i2s-tdm";
123 reg = <0x0 0xfde00000 0x0 0x1000>;
124 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
125 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
126 clock-names = "mclk_tx", "mclk_rx", "hclk";
127 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
128 assigned-clock-parents = <&cru PLL_AUPLL>;
129 dmas = <&dmac2 24>;
130 dma-names = "rx";
131 power-domains = <&power RK3588_PD_VO1>;
132 resets = <&cru SRST_M_I2S10_8CH_RX>;
133 reset-names = "rx-m";
134 #sound-dai-cells = <0>;
135 status = "disabled";
136 };
137
138 pcie3x4: pcie@fe150000 {
139 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
140 #address-cells = <3>;
141 #size-cells = <2>;
142 bus-range = <0x00 0x0f>;
143 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
144 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
145 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
146 clock-names = "aclk_mst", "aclk_slv",
147 "aclk_dbi", "pclk",
148 "aux", "pipe";
149 device_type = "pci";
150 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
151 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
152 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
153 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
154 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
155 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
156 #interrupt-cells = <1>;
157 interrupt-map-mask = <0 0 0 7>;
158 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
159 <0 0 0 2 &pcie3x4_intc 1>,
160 <0 0 0 3 &pcie3x4_intc 2>,
161 <0 0 0 4 &pcie3x4_intc 3>;
162 linux,pci-domain = <0>;
163 max-link-speed = <3>;
164 msi-map = <0x0000 &its1 0x0000 0x1000>;
165 num-lanes = <4>;
166 phys = <&pcie30phy>;
167 phy-names = "pcie-phy";
168 power-domains = <&power RK3588_PD_PCIE>;
169 ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
170 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
171 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
172 reg = <0xa 0x40000000 0x0 0x00400000>,
173 <0x0 0xfe150000 0x0 0x00010000>,
174 <0x0 0xf0000000 0x0 0x00100000>;
175 reg-names = "dbi", "apb", "config";
176 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
177 reset-names = "pwr", "pipe";
178 status = "disabled";
179
180 pcie3x4_intc: legacy-interrupt-controller {
181 interrupt-controller;
182 #address-cells = <0>;
183 #interrupt-cells = <1>;
184 interrupt-parent = <&gic>;
185 interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
186 };
187 };
188
189 pcie3x4_ep: pcie-ep@fe150000 {
190 compatible = "rockchip,rk3588-pcie-ep";
191 reg = <0xa 0x40000000 0x0 0x00100000>,
192 <0xa 0x40100000 0x0 0x00100000>,
193 <0x0 0xfe150000 0x0 0x00010000>,
194 <0x9 0x00000000 0x0 0x40000000>,
195 <0xa 0x40300000 0x0 0x00100000>;
196 reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
197 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
198 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
199 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
200 clock-names = "aclk_mst", "aclk_slv",
201 "aclk_dbi", "pclk",
202 "aux", "pipe";
203 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
204 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
205 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
206 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
207 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
208 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,
209 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>,
210 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
211 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
212 interrupt-names = "sys", "pmc", "msg", "legacy", "err",
213 "dma0", "dma1", "dma2", "dma3";
214 max-link-speed = <3>;
215 num-lanes = <4>;
216 phys = <&pcie30phy>;
217 phy-names = "pcie-phy";
218 power-domains = <&power RK3588_PD_PCIE>;
219 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
220 reset-names = "pwr", "pipe";
221 status = "disabled";
222 };
223
224 pcie3x2: pcie@fe160000 {
225 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
226 #address-cells = <3>;
227 #size-cells = <2>;
228 bus-range = <0x10 0x1f>;
229 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
230 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
231 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
232 clock-names = "aclk_mst", "aclk_slv",
233 "aclk_dbi", "pclk",
234 "aux", "pipe";
235 device_type = "pci";
236 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
237 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
238 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
239 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
240 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
241 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
242 #interrupt-cells = <1>;
243 interrupt-map-mask = <0 0 0 7>;
244 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
245 <0 0 0 2 &pcie3x2_intc 1>,
246 <0 0 0 3 &pcie3x2_intc 2>,
247 <0 0 0 4 &pcie3x2_intc 3>;
248 linux,pci-domain = <1>;
249 max-link-speed = <3>;
250 msi-map = <0x1000 &its1 0x1000 0x1000>;
251 num-lanes = <2>;
252 phys = <&pcie30phy>;
253 phy-names = "pcie-phy";
254 power-domains = <&power RK3588_PD_PCIE>;
255 ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
256 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
257 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
258 reg = <0xa 0x40400000 0x0 0x00400000>,
259 <0x0 0xfe160000 0x0 0x00010000>,
260 <0x0 0xf1000000 0x0 0x00100000>;
261 reg-names = "dbi", "apb", "config";
262 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
263 reset-names = "pwr", "pipe";
264 status = "disabled";
265
266 pcie3x2_intc: legacy-interrupt-controller {
267 interrupt-controller;
268 #address-cells = <0>;
269 #interrupt-cells = <1>;
270 interrupt-parent = <&gic>;
271 interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
272 };
273 };
274
275 pcie2x1l0: pcie@fe170000 {
276 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
277 bus-range = <0x20 0x2f>;
278 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
279 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
280 <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
281 clock-names = "aclk_mst", "aclk_slv",
282 "aclk_dbi", "pclk",
283 "aux", "pipe";
284 device_type = "pci";
285 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
286 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
287 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
288 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
289 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
290 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
291 #interrupt-cells = <1>;
292 interrupt-map-mask = <0 0 0 7>;
293 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
294 <0 0 0 2 &pcie2x1l0_intc 1>,
295 <0 0 0 3 &pcie2x1l0_intc 2>,
296 <0 0 0 4 &pcie2x1l0_intc 3>;
297 linux,pci-domain = <2>;
298 max-link-speed = <2>;
299 msi-map = <0x2000 &its0 0x2000 0x1000>;
300 num-lanes = <1>;
301 phys = <&combphy1_ps PHY_TYPE_PCIE>;
302 phy-names = "pcie-phy";
303 power-domains = <&power RK3588_PD_PCIE>;
304 ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
305 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
306 <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
307 reg = <0xa 0x40800000 0x0 0x00400000>,
308 <0x0 0xfe170000 0x0 0x00010000>,
309 <0x0 0xf2000000 0x0 0x00100000>;
310 reg-names = "dbi", "apb", "config";
311 resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
312 reset-names = "pwr", "pipe";
313 #address-cells = <3>;
314 #size-cells = <2>;
315 status = "disabled";
316
317 pcie2x1l0_intc: legacy-interrupt-controller {
318 interrupt-controller;
319 #address-cells = <0>;
320 #interrupt-cells = <1>;
321 interrupt-parent = <&gic>;
322 interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
323 };
324 };
325
326 gmac0: ethernet@fe1b0000 {
327 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
328 reg = <0x0 0xfe1b0000 0x0 0x10000>;
329 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
330 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
331 interrupt-names = "macirq", "eth_wake_irq";
332 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
333 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
334 <&cru CLK_GMAC0_PTP_REF>;
335 clock-names = "stmmaceth", "clk_mac_ref",
336 "pclk_mac", "aclk_mac",
337 "ptp_ref";
338 power-domains = <&power RK3588_PD_GMAC>;
339 resets = <&cru SRST_A_GMAC0>;
340 reset-names = "stmmaceth";
341 rockchip,grf = <&sys_grf>;
342 rockchip,php-grf = <&php_grf>;
343 snps,axi-config = <&gmac0_stmmac_axi_setup>;
344 snps,mixed-burst;
345 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
346 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
347 snps,tso;
348 status = "disabled";
349
350 mdio0: mdio {
351 compatible = "snps,dwmac-mdio";
352 #address-cells = <0x1>;
353 #size-cells = <0x0>;
354 };
355
356 gmac0_stmmac_axi_setup: stmmac-axi-config {
357 snps,blen = <0 0 0 0 16 8 4>;
358 snps,wr_osr_lmt = <4>;
359 snps,rd_osr_lmt = <8>;
360 };
361
362 gmac0_mtl_rx_setup: rx-queues-config {
363 snps,rx-queues-to-use = <2>;
364 queue0 {};
365 queue1 {};
366 };
367
368 gmac0_mtl_tx_setup: tx-queues-config {
369 snps,tx-queues-to-use = <2>;
370 queue0 {};
371 queue1 {};
372 };
373 };
374
375 sata1: sata@fe220000 {
376 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
377 reg = <0 0xfe220000 0 0x1000>;
378 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
379 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
380 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
381 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
382 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
383 ports-implemented = <0x1>;
384 #address-cells = <1>;
385 #size-cells = <0>;
386 status = "disabled";
387
388 sata-port@0 {
389 reg = <0>;
390 hba-port-cap = <HBA_PORT_FBSCP>;
391 phys = <&combphy1_ps PHY_TYPE_SATA>;
392 phy-names = "sata-phy";
393 snps,rx-ts-max = <32>;
394 snps,tx-ts-max = <32>;
395 };
396 };
397
398 usbdp_phy1: phy@fed90000 {
399 compatible = "rockchip,rk3588-usbdp-phy";
400 reg = <0x0 0xfed90000 0x0 0x10000>;
401 #phy-cells = <1>;
402 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
403 <&cru CLK_USBDP_PHY1_IMMORTAL>,
404 <&cru PCLK_USBDPPHY1>,
405 <&u2phy1>;
406 clock-names = "refclk", "immortal", "pclk", "utmi";
407 resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
408 <&cru SRST_USBDP_COMBO_PHY1_CMN>,
409 <&cru SRST_USBDP_COMBO_PHY1_LANE>,
410 <&cru SRST_USBDP_COMBO_PHY1_PCS>,
411 <&cru SRST_P_USBDPPHY1>;
412 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
413 rockchip,u2phy-grf = <&usb2phy1_grf>;
414 rockchip,usb-grf = <&usb_grf>;
415 rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
416 rockchip,vo-grf = <&vo0_grf>;
417 status = "disabled";
418 };
419
420 combphy1_ps: phy@fee10000 {
421 compatible = "rockchip,rk3588-naneng-combphy";
422 reg = <0x0 0xfee10000 0x0 0x100>;
423 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
424 <&cru PCLK_PHP_ROOT>;
425 clock-names = "ref", "apb", "pipe";
426 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
427 assigned-clock-rates = <100000000>;
428 #phy-cells = <1>;
429 resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
430 reset-names = "phy", "apb";
431 rockchip,pipe-grf = <&php_grf>;
432 rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
433 status = "disabled";
434 };
435
436 pcie30phy: phy@fee80000 {
437 compatible = "rockchip,rk3588-pcie3-phy";
438 reg = <0x0 0xfee80000 0x0 0x20000>;
439 #phy-cells = <0>;
440 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
441 clock-names = "pclk";
442 resets = <&cru SRST_PCIE30_PHY>;
443 reset-names = "phy";
444 rockchip,pipe-grf = <&php_grf>;
445 rockchip,phy-grf = <&pcie30_phy_grf>;
446 status = "disabled";
447 };
448 };
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