1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Device Tree Source for UniPhier LD20 SoC
4 //
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
12
13 / {
14 compatible = "socionext,uniphier-ld20";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
18
19 cpus {
20 #address-cells = <2>;
21 #size-cells = <0>;
22
23 cpu-map {
24 cluster0 {
25 core0 {
26 cpu = <&cpu0>;
27 };
28 core1 {
29 cpu = <&cpu1>;
30 };
31 };
32
33 cluster1 {
34 core0 {
35 cpu = <&cpu2>;
36 };
37 core1 {
38 cpu = <&cpu3>;
39 };
40 };
41 };
42
43 cpu0: cpu@0 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a72";
46 reg = <0 0x000>;
47 clocks = <&sys_clk 32>;
48 enable-method = "psci";
49 next-level-cache = <&a72_l2>;
50 operating-points-v2 = <&cluster0_opp>;
51 #cooling-cells = <2>;
52 };
53
54 cpu1: cpu@1 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a72";
57 reg = <0 0x001>;
58 clocks = <&sys_clk 32>;
59 enable-method = "psci";
60 next-level-cache = <&a72_l2>;
61 operating-points-v2 = <&cluster0_opp>;
62 #cooling-cells = <2>;
63 };
64
65 cpu2: cpu@100 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a53";
68 reg = <0 0x100>;
69 clocks = <&sys_clk 33>;
70 enable-method = "psci";
71 next-level-cache = <&a53_l2>;
72 operating-points-v2 = <&cluster1_opp>;
73 #cooling-cells = <2>;
74 };
75
76 cpu3: cpu@101 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a53";
79 reg = <0 0x101>;
80 clocks = <&sys_clk 33>;
81 enable-method = "psci";
82 next-level-cache = <&a53_l2>;
83 operating-points-v2 = <&cluster1_opp>;
84 #cooling-cells = <2>;
85 };
86
87 a72_l2: l2-cache0 {
88 compatible = "cache";
89 cache-level = <2>;
90 cache-unified;
91 };
92
93 a53_l2: l2-cache1 {
94 compatible = "cache";
95 cache-level = <2>;
96 cache-unified;
97 };
98 };
99
100 cluster0_opp: opp-table-0 {
101 compatible = "operating-points-v2";
102 opp-shared;
103
104 opp-250000000 {
105 opp-hz = /bits/ 64 <250000000>;
106 clock-latency-ns = <300>;
107 };
108 opp-275000000 {
109 opp-hz = /bits/ 64 <275000000>;
110 clock-latency-ns = <300>;
111 };
112 opp-500000000 {
113 opp-hz = /bits/ 64 <500000000>;
114 clock-latency-ns = <300>;
115 };
116 opp-550000000 {
117 opp-hz = /bits/ 64 <550000000>;
118 clock-latency-ns = <300>;
119 };
120 opp-666667000 {
121 opp-hz = /bits/ 64 <666667000>;
122 clock-latency-ns = <300>;
123 };
124 opp-733334000 {
125 opp-hz = /bits/ 64 <733334000>;
126 clock-latency-ns = <300>;
127 };
128 opp-1000000000 {
129 opp-hz = /bits/ 64 <1000000000>;
130 clock-latency-ns = <300>;
131 };
132 opp-1100000000 {
133 opp-hz = /bits/ 64 <1100000000>;
134 clock-latency-ns = <300>;
135 };
136 };
137
138 cluster1_opp: opp-table-1 {
139 compatible = "operating-points-v2";
140 opp-shared;
141
142 opp-250000000 {
143 opp-hz = /bits/ 64 <250000000>;
144 clock-latency-ns = <300>;
145 };
146 opp-275000000 {
147 opp-hz = /bits/ 64 <275000000>;
148 clock-latency-ns = <300>;
149 };
150 opp-500000000 {
151 opp-hz = /bits/ 64 <500000000>;
152 clock-latency-ns = <300>;
153 };
154 opp-550000000 {
155 opp-hz = /bits/ 64 <550000000>;
156 clock-latency-ns = <300>;
157 };
158 opp-666667000 {
159 opp-hz = /bits/ 64 <666667000>;
160 clock-latency-ns = <300>;
161 };
162 opp-733334000 {
163 opp-hz = /bits/ 64 <733334000>;
164 clock-latency-ns = <300>;
165 };
166 opp-1000000000 {
167 opp-hz = /bits/ 64 <1000000000>;
168 clock-latency-ns = <300>;
169 };
170 opp-1100000000 {
171 opp-hz = /bits/ 64 <1100000000>;
172 clock-latency-ns = <300>;
173 };
174 };
175
176 psci {
177 compatible = "arm,psci-1.0";
178 method = "smc";
179 };
180
181 clocks {
182 refclk: ref {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency = <25000000>;
186 };
187 };
188
189 emmc_pwrseq: emmc-pwrseq {
190 compatible = "mmc-pwrseq-emmc";
191 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
192 };
193
194 timer {
195 compatible = "arm,armv8-timer";
196 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
200 };
201
202 thermal-zones {
203 cpu-thermal {
204 polling-delay-passive = <250>; /* 250ms */
205 polling-delay = <1000>; /* 1000ms */
206 thermal-sensors = <&pvtctl>;
207
208 trips {
209 cpu_crit: cpu-crit {
210 temperature = <110000>; /* 110C */
211 hysteresis = <2000>;
212 type = "critical";
213 };
214 cpu_alert: cpu-alert {
215 temperature = <100000>; /* 100C */
216 hysteresis = <2000>;
217 type = "passive";
218 };
219 };
220
221 cooling-maps {
222 map0 {
223 trip = <&cpu_alert>;
224 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
226 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
227 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
228 };
229 };
230 };
231 };
232
233 reserved-memory {
234 #address-cells = <2>;
235 #size-cells = <2>;
236 ranges;
237
238 secure-memory@81000000 {
239 reg = <0x0 0x81000000 0x0 0x01000000>;
240 no-map;
241 };
242 };
243
244 soc@0 {
245 compatible = "simple-bus";
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges = <0 0 0 0xffffffff>;
249
250 spi0: spi@54006000 {
251 compatible = "socionext,uniphier-scssi";
252 status = "disabled";
253 reg = <0x54006000 0x100>;
254 #address-cells = <1>;
255 #size-cells = <0>;
256 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_spi0>;
259 clocks = <&peri_clk 11>;
260 resets = <&peri_rst 11>;
261 };
262
263 spi1: spi@54006100 {
264 compatible = "socionext,uniphier-scssi";
265 status = "disabled";
266 reg = <0x54006100 0x100>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_spi1>;
272 clocks = <&peri_clk 12>;
273 resets = <&peri_rst 12>;
274 };
275
276 spi2: spi@54006200 {
277 compatible = "socionext,uniphier-scssi";
278 status = "disabled";
279 reg = <0x54006200 0x100>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_spi2>;
285 clocks = <&peri_clk 13>;
286 resets = <&peri_rst 13>;
287 };
288
289 spi3: spi@54006300 {
290 compatible = "socionext,uniphier-scssi";
291 status = "disabled";
292 reg = <0x54006300 0x100>;
293 #address-cells = <1>;
294 #size-cells = <0>;
295 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_spi3>;
298 clocks = <&peri_clk 14>;
299 resets = <&peri_rst 14>;
300 };
301
302 serial0: serial@54006800 {
303 compatible = "socionext,uniphier-uart";
304 status = "disabled";
305 reg = <0x54006800 0x40>;
306 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_uart0>;
309 clocks = <&peri_clk 0>;
310 resets = <&peri_rst 0>;
311 };
312
313 serial1: serial@54006900 {
314 compatible = "socionext,uniphier-uart";
315 status = "disabled";
316 reg = <0x54006900 0x40>;
317 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_uart1>;
320 clocks = <&peri_clk 1>;
321 resets = <&peri_rst 1>;
322 };
323
324 serial2: serial@54006a00 {
325 compatible = "socionext,uniphier-uart";
326 status = "disabled";
327 reg = <0x54006a00 0x40>;
328 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_uart2>;
331 clocks = <&peri_clk 2>;
332 resets = <&peri_rst 2>;
333 };
334
335 serial3: serial@54006b00 {
336 compatible = "socionext,uniphier-uart";
337 status = "disabled";
338 reg = <0x54006b00 0x40>;
339 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_uart3>;
342 clocks = <&peri_clk 3>;
343 resets = <&peri_rst 3>;
344 };
345
346 gpio: gpio@55000000 {
347 compatible = "socionext,uniphier-gpio";
348 reg = <0x55000000 0x200>;
349 interrupt-parent = <&aidet>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
352 gpio-controller;
353 #gpio-cells = <2>;
354 gpio-ranges = <&pinctrl 0 0 0>,
355 <&pinctrl 96 0 0>,
356 <&pinctrl 160 0 0>;
357 gpio-ranges-group-names = "gpio_range0",
358 "gpio_range1",
359 "gpio_range2";
360 ngpios = <205>;
361 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
362 <21 217 3>;
363 };
364
365 audio@56000000 {
366 compatible = "socionext,uniphier-ld20-aio";
367 reg = <0x56000000 0x80000>;
368 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_aout1>,
371 <&pinctrl_aoutiec1>;
372 clock-names = "aio";
373 clocks = <&sys_clk 40>;
374 reset-names = "aio";
375 resets = <&sys_rst 40>;
376 #sound-dai-cells = <1>;
377 socionext,syscon = <&soc_glue>;
378
379 i2s_port0: port@0 {
380 i2s_hdmi: endpoint {
381 };
382 };
383
384 i2s_port1: port@1 {
385 i2s_pcmin2: endpoint {
386 };
387 };
388
389 i2s_port2: port@2 {
390 i2s_line: endpoint {
391 dai-format = "i2s";
392 remote-endpoint = <&evea_line>;
393 };
394 };
395
396 i2s_port3: port@3 {
397 i2s_hpcmout1: endpoint {
398 };
399 };
400
401 i2s_port4: port@4 {
402 i2s_hp: endpoint {
403 dai-format = "i2s";
404 remote-endpoint = <&evea_hp>;
405 };
406 };
407
408 spdif_port0: port@5 {
409 spdif_hiecout1: endpoint {
410 };
411 };
412
413 src_port0: port@6 {
414 i2s_epcmout2: endpoint {
415 };
416 };
417
418 src_port1: port@7 {
419 i2s_epcmout3: endpoint {
420 };
421 };
422
423 comp_spdif_port0: port@8 {
424 comp_spdif_hiecout1: endpoint {
425 };
426 };
427 };
428
429 codec@57900000 {
430 compatible = "socionext,uniphier-evea";
431 reg = <0x57900000 0x1000>;
432 clock-names = "evea", "exiv";
433 clocks = <&sys_clk 41>, <&sys_clk 42>;
434 reset-names = "evea", "exiv", "adamv";
435 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
436 #sound-dai-cells = <1>;
437
438 port@0 {
439 evea_line: endpoint {
440 remote-endpoint = <&i2s_line>;
441 };
442 };
443
444 port@1 {
445 evea_hp: endpoint {
446 remote-endpoint = <&i2s_hp>;
447 };
448 };
449 };
450
451 syscon@57920000 {
452 compatible = "socionext,uniphier-ld20-adamv",
453 "simple-mfd", "syscon";
454 reg = <0x57920000 0x1000>;
455
456 adamv_rst: reset-controller {
457 compatible = "socionext,uniphier-ld20-adamv-reset";
458 #reset-cells = <1>;
459 };
460 };
461
462 i2c0: i2c@58780000 {
463 compatible = "socionext,uniphier-fi2c";
464 status = "disabled";
465 reg = <0x58780000 0x80>;
466 #address-cells = <1>;
467 #size-cells = <0>;
468 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_i2c0>;
471 clocks = <&peri_clk 4>;
472 resets = <&peri_rst 4>;
473 clock-frequency = <100000>;
474 };
475
476 i2c1: i2c@58781000 {
477 compatible = "socionext,uniphier-fi2c";
478 status = "disabled";
479 reg = <0x58781000 0x80>;
480 #address-cells = <1>;
481 #size-cells = <0>;
482 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_i2c1>;
485 clocks = <&peri_clk 5>;
486 resets = <&peri_rst 5>;
487 clock-frequency = <100000>;
488 };
489
490 i2c2: i2c@58782000 {
491 compatible = "socionext,uniphier-fi2c";
492 reg = <0x58782000 0x80>;
493 #address-cells = <1>;
494 #size-cells = <0>;
495 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&peri_clk 6>;
497 resets = <&peri_rst 6>;
498 clock-frequency = <400000>;
499 };
500
501 i2c3: i2c@58783000 {
502 compatible = "socionext,uniphier-fi2c";
503 status = "disabled";
504 reg = <0x58783000 0x80>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_i2c3>;
510 clocks = <&peri_clk 7>;
511 resets = <&peri_rst 7>;
512 clock-frequency = <100000>;
513 };
514
515 i2c4: i2c@58784000 {
516 compatible = "socionext,uniphier-fi2c";
517 status = "disabled";
518 reg = <0x58784000 0x80>;
519 #address-cells = <1>;
520 #size-cells = <0>;
521 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&pinctrl_i2c4>;
524 clocks = <&peri_clk 8>;
525 resets = <&peri_rst 8>;
526 clock-frequency = <100000>;
527 };
528
529 i2c5: i2c@58785000 {
530 compatible = "socionext,uniphier-fi2c";
531 reg = <0x58785000 0x80>;
532 #address-cells = <1>;
533 #size-cells = <0>;
534 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&peri_clk 9>;
536 resets = <&peri_rst 9>;
537 clock-frequency = <400000>;
538 };
539
540 system_bus: system-bus@58c00000 {
541 compatible = "socionext,uniphier-system-bus";
542 status = "disabled";
543 reg = <0x58c00000 0x400>;
544 #address-cells = <2>;
545 #size-cells = <1>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&pinctrl_system_bus>;
548 };
549
550 smpctrl@59801000 {
551 compatible = "socionext,uniphier-smpctrl";
552 reg = <0x59801000 0x400>;
553 };
554
555 sdctrl: syscon@59810000 {
556 compatible = "socionext,uniphier-ld20-sdctrl",
557 "simple-mfd", "syscon";
558 reg = <0x59810000 0x400>;
559
560 sd_clk: clock-controller {
561 compatible = "socionext,uniphier-ld20-sd-clock";
562 #clock-cells = <1>;
563 };
564
565 sd_rst: reset-controller {
566 compatible = "socionext,uniphier-ld20-sd-reset";
567 #reset-cells = <1>;
568 };
569 };
570
571 syscon@59820000 {
572 compatible = "socionext,uniphier-ld20-perictrl",
573 "simple-mfd", "syscon";
574 reg = <0x59820000 0x200>;
575
576 peri_clk: clock-controller {
577 compatible = "socionext,uniphier-ld20-peri-clock";
578 #clock-cells = <1>;
579 };
580
581 peri_rst: reset-controller {
582 compatible = "socionext,uniphier-ld20-peri-reset";
583 #reset-cells = <1>;
584 };
585 };
586
587 emmc: mmc@5a000000 {
588 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
589 reg = <0x5a000000 0x400>;
590 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&pinctrl_emmc>;
593 clocks = <&sys_clk 4>;
594 resets = <&sys_rst 4>;
595 bus-width = <8>;
596 mmc-ddr-1_8v;
597 mmc-hs200-1_8v;
598 mmc-pwrseq = <&emmc_pwrseq>;
599 cdns,phy-input-delay-legacy = <9>;
600 cdns,phy-input-delay-mmc-highspeed = <2>;
601 cdns,phy-input-delay-mmc-ddr = <3>;
602 cdns,phy-dll-delay-sdclk = <21>;
603 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
604 };
605
606 sd: mmc@5a400000 {
607 compatible = "socionext,uniphier-sd-v3.1.1";
608 status = "disabled";
609 reg = <0x5a400000 0x800>;
610 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
611 pinctrl-names = "default";
612 pinctrl-0 = <&pinctrl_sd>;
613 clocks = <&sd_clk 0>;
614 reset-names = "host";
615 resets = <&sd_rst 0>;
616 bus-width = <4>;
617 cap-sd-highspeed;
618 socionext,syscon-uhs-mode = <&sdctrl 0>;
619 };
620
621 soc_glue: syscon@5f800000 {
622 compatible = "socionext,uniphier-ld20-soc-glue",
623 "simple-mfd", "syscon";
624 reg = <0x5f800000 0x2000>;
625
626 pinctrl: pinctrl {
627 compatible = "socionext,uniphier-ld20-pinctrl";
628 };
629 };
630
631 syscon@5f900000 {
632 compatible = "socionext,uniphier-ld20-soc-glue-debug",
633 "simple-mfd", "syscon";
634 reg = <0x5f900000 0x2000>;
635 #address-cells = <1>;
636 #size-cells = <1>;
637 ranges = <0 0x5f900000 0x2000>;
638
639 efuse@100 {
640 compatible = "socionext,uniphier-efuse";
641 reg = <0x100 0x28>;
642 };
643
644 efuse@200 {
645 compatible = "socionext,uniphier-efuse";
646 reg = <0x200 0x68>;
647 #address-cells = <1>;
648 #size-cells = <1>;
649
650 /* USB cells */
651 usb_rterm0: trim@54,4 {
652 reg = <0x54 1>;
653 bits = <4 2>;
654 };
655 usb_rterm1: trim@55,4 {
656 reg = <0x55 1>;
657 bits = <4 2>;
658 };
659 usb_rterm2: trim@58,4 {
660 reg = <0x58 1>;
661 bits = <4 2>;
662 };
663 usb_rterm3: trim@59,4 {
664 reg = <0x59 1>;
665 bits = <4 2>;
666 };
667 usb_sel_t0: trim@54,0 {
668 reg = <0x54 1>;
669 bits = <0 4>;
670 };
671 usb_sel_t1: trim@55,0 {
672 reg = <0x55 1>;
673 bits = <0 4>;
674 };
675 usb_sel_t2: trim@58,0 {
676 reg = <0x58 1>;
677 bits = <0 4>;
678 };
679 usb_sel_t3: trim@59,0 {
680 reg = <0x59 1>;
681 bits = <0 4>;
682 };
683 usb_hs_i0: trim@56,0 {
684 reg = <0x56 1>;
685 bits = <0 4>;
686 };
687 usb_hs_i2: trim@5a,0 {
688 reg = <0x5a 1>;
689 bits = <0 4>;
690 };
691 };
692 };
693
694 xdmac: dma-controller@5fc10000 {
695 compatible = "socionext,uniphier-xdmac";
696 reg = <0x5fc10000 0x5300>;
697 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
698 dma-channels = <16>;
699 #dma-cells = <2>;
700 };
701
702 aidet: interrupt-controller@5fc20000 {
703 compatible = "socionext,uniphier-ld20-aidet";
704 reg = <0x5fc20000 0x200>;
705 interrupt-controller;
706 #interrupt-cells = <2>;
707 };
708
709 gic: interrupt-controller@5fe00000 {
710 compatible = "arm,gic-v3";
711 reg = <0x5fe00000 0x10000>, /* GICD */
712 <0x5fe80000 0x80000>; /* GICR */
713 interrupt-controller;
714 #interrupt-cells = <3>;
715 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
716 };
717
718 syscon@61840000 {
719 compatible = "socionext,uniphier-ld20-sysctrl",
720 "simple-mfd", "syscon";
721 reg = <0x61840000 0x10000>;
722
723 sys_clk: clock-controller {
724 compatible = "socionext,uniphier-ld20-clock";
725 #clock-cells = <1>;
726 };
727
728 sys_rst: reset-controller {
729 compatible = "socionext,uniphier-ld20-reset";
730 #reset-cells = <1>;
731 };
732
733 watchdog {
734 compatible = "socionext,uniphier-wdt";
735 };
736
737 pvtctl: thermal-sensor {
738 compatible = "socionext,uniphier-ld20-thermal";
739 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
740 #thermal-sensor-cells = <0>;
741 socionext,tmod-calibration = <0x0f22 0x68ee>;
742 };
743 };
744
745 eth: ethernet@65000000 {
746 compatible = "socionext,uniphier-ld20-ave4";
747 status = "disabled";
748 reg = <0x65000000 0x8500>;
749 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
750 pinctrl-names = "default";
751 pinctrl-0 = <&pinctrl_ether_rgmii>;
752 clock-names = "ether";
753 clocks = <&sys_clk 6>;
754 reset-names = "ether";
755 resets = <&sys_rst 6>;
756 phy-mode = "rgmii-id";
757 local-mac-address = [00 00 00 00 00 00];
758 socionext,syscon-phy-mode = <&soc_glue 0>;
759
760 mdio: mdio {
761 #address-cells = <1>;
762 #size-cells = <0>;
763 };
764 };
765
766 usb: usb@65a00000 {
767 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
768 status = "disabled";
769 reg = <0x65a00000 0xcd00>;
770 interrupt-names = "host";
771 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
772 pinctrl-names = "default";
773 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
774 <&pinctrl_usb2>, <&pinctrl_usb3>;
775 clock-names = "ref", "bus_early", "suspend";
776 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
777 resets = <&usb_rst 15>;
778 phys = <&usb_hsphy0>, <&usb_hsphy1>,
779 <&usb_hsphy2>, <&usb_hsphy3>,
780 <&usb_ssphy0>, <&usb_ssphy1>;
781 dr_mode = "host";
782 };
783
784 usb-controller@65b00000 {
785 compatible = "socionext,uniphier-ld20-dwc3-glue",
786 "simple-mfd";
787 reg = <0x65b00000 0x400>;
788 #address-cells = <1>;
789 #size-cells = <1>;
790 ranges = <0 0x65b00000 0x400>;
791
792 usb_rst: reset-controller@0 {
793 compatible = "socionext,uniphier-ld20-usb3-reset";
794 reg = <0x0 0x4>;
795 #reset-cells = <1>;
796 clock-names = "link";
797 clocks = <&sys_clk 14>;
798 reset-names = "link";
799 resets = <&sys_rst 14>;
800 };
801
802 usb_vbus0: regulator@100 {
803 compatible = "socionext,uniphier-ld20-usb3-regulator";
804 reg = <0x100 0x10>;
805 clock-names = "link";
806 clocks = <&sys_clk 14>;
807 reset-names = "link";
808 resets = <&sys_rst 14>;
809 };
810
811 usb_vbus1: regulator@110 {
812 compatible = "socionext,uniphier-ld20-usb3-regulator";
813 reg = <0x110 0x10>;
814 clock-names = "link";
815 clocks = <&sys_clk 14>;
816 reset-names = "link";
817 resets = <&sys_rst 14>;
818 };
819
820 usb_vbus2: regulator@120 {
821 compatible = "socionext,uniphier-ld20-usb3-regulator";
822 reg = <0x120 0x10>;
823 clock-names = "link";
824 clocks = <&sys_clk 14>;
825 reset-names = "link";
826 resets = <&sys_rst 14>;
827 };
828
829 usb_vbus3: regulator@130 {
830 compatible = "socionext,uniphier-ld20-usb3-regulator";
831 reg = <0x130 0x10>;
832 clock-names = "link";
833 clocks = <&sys_clk 14>;
834 reset-names = "link";
835 resets = <&sys_rst 14>;
836 };
837
838 usb_hsphy0: phy@200 {
839 compatible = "socionext,uniphier-ld20-usb3-hsphy";
840 reg = <0x200 0x10>;
841 #phy-cells = <0>;
842 clock-names = "link", "phy";
843 clocks = <&sys_clk 14>, <&sys_clk 16>;
844 reset-names = "link", "phy";
845 resets = <&sys_rst 14>, <&sys_rst 16>;
846 vbus-supply = <&usb_vbus0>;
847 nvmem-cell-names = "rterm", "sel_t", "hs_i";
848 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
849 <&usb_hs_i0>;
850 };
851
852 usb_hsphy1: phy@210 {
853 compatible = "socionext,uniphier-ld20-usb3-hsphy";
854 reg = <0x210 0x10>;
855 #phy-cells = <0>;
856 clock-names = "link", "phy";
857 clocks = <&sys_clk 14>, <&sys_clk 16>;
858 reset-names = "link", "phy";
859 resets = <&sys_rst 14>, <&sys_rst 16>;
860 vbus-supply = <&usb_vbus1>;
861 nvmem-cell-names = "rterm", "sel_t", "hs_i";
862 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
863 <&usb_hs_i0>;
864 };
865
866 usb_hsphy2: phy@220 {
867 compatible = "socionext,uniphier-ld20-usb3-hsphy";
868 reg = <0x220 0x10>;
869 #phy-cells = <0>;
870 clock-names = "link", "phy";
871 clocks = <&sys_clk 14>, <&sys_clk 17>;
872 reset-names = "link", "phy";
873 resets = <&sys_rst 14>, <&sys_rst 17>;
874 vbus-supply = <&usb_vbus2>;
875 nvmem-cell-names = "rterm", "sel_t", "hs_i";
876 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
877 <&usb_hs_i2>;
878 };
879
880 usb_hsphy3: phy@230 {
881 compatible = "socionext,uniphier-ld20-usb3-hsphy";
882 reg = <0x230 0x10>;
883 #phy-cells = <0>;
884 clock-names = "link", "phy";
885 clocks = <&sys_clk 14>, <&sys_clk 17>;
886 reset-names = "link", "phy";
887 resets = <&sys_rst 14>, <&sys_rst 17>;
888 vbus-supply = <&usb_vbus3>;
889 nvmem-cell-names = "rterm", "sel_t", "hs_i";
890 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
891 <&usb_hs_i2>;
892 };
893
894 usb_ssphy0: phy@300 {
895 compatible = "socionext,uniphier-ld20-usb3-ssphy";
896 reg = <0x300 0x10>;
897 #phy-cells = <0>;
898 clock-names = "link", "phy";
899 clocks = <&sys_clk 14>, <&sys_clk 18>;
900 reset-names = "link", "phy";
901 resets = <&sys_rst 14>, <&sys_rst 18>;
902 vbus-supply = <&usb_vbus0>;
903 };
904
905 usb_ssphy1: phy@310 {
906 compatible = "socionext,uniphier-ld20-usb3-ssphy";
907 reg = <0x310 0x10>;
908 #phy-cells = <0>;
909 clock-names = "link", "phy";
910 clocks = <&sys_clk 14>, <&sys_clk 19>;
911 reset-names = "link", "phy";
912 resets = <&sys_rst 14>, <&sys_rst 19>;
913 vbus-supply = <&usb_vbus1>;
914 };
915 };
916
917 pcie: pcie@66000000 {
918 compatible = "socionext,uniphier-pcie";
919 status = "disabled";
920 reg-names = "dbi", "link", "config";
921 reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
922 <0x2fff0000 0x10000>;
923 #address-cells = <3>;
924 #size-cells = <2>;
925 clocks = <&sys_clk 24>;
926 resets = <&sys_rst 24>;
927 num-lanes = <1>;
928 num-viewport = <1>;
929 bus-range = <0x0 0xff>;
930 device_type = "pci";
931 ranges =
932 /* downstream I/O */
933 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
934 /* non-prefetchable memory */
935 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
936 #interrupt-cells = <1>;
937 interrupt-names = "dma", "msi";
938 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
940 interrupt-map-mask = <0 0 0 7>;
941 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
942 <0 0 0 2 &pcie_intc 1>, /* INTB */
943 <0 0 0 3 &pcie_intc 2>, /* INTC */
944 <0 0 0 4 &pcie_intc 3>; /* INTD */
945 phy-names = "pcie-phy";
946 phys = <&pcie_phy>;
947
948 pcie_intc: legacy-interrupt-controller {
949 interrupt-controller;
950 #interrupt-cells = <1>;
951 interrupt-parent = <&gic>;
952 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
953 };
954 };
955
956 pcie_phy: phy@66038000 {
957 compatible = "socionext,uniphier-ld20-pcie-phy";
958 reg = <0x66038000 0x4000>;
959 #phy-cells = <0>;
960 clock-names = "link";
961 clocks = <&sys_clk 24>;
962 reset-names = "link";
963 resets = <&sys_rst 24>;
964 socionext,syscon = <&soc_glue>;
965 };
966
967 nand: nand-controller@68000000 {
968 compatible = "socionext,uniphier-denali-nand-v5b";
969 status = "disabled";
970 reg-names = "nand_data", "denali_reg";
971 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
972 #address-cells = <1>;
973 #size-cells = <0>;
974 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
975 pinctrl-names = "default";
976 pinctrl-0 = <&pinctrl_nand>;
977 clock-names = "nand", "nand_x", "ecc";
978 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
979 reset-names = "nand", "reg";
980 resets = <&sys_rst 2>, <&sys_rst 2>;
981 };
982 };
983 };
984
985 #include "uniphier-pinctrl.dtsi"
986
987 &pinctrl_aout1 {
988 drive-strength = <4>; /* default: 3.5mA */
989
990 ao1dacck {
991 pins = "AO1DACCK";
992 drive-strength = <5>; /* 5mA */
993 };
994 };
995
996 &pinctrl_aoutiec1 {
997 drive-strength = <4>; /* default: 3.5mA */
998
999 ao1arc {
1000 pins = "AO1ARC";
1001 drive-strength = <11>; /* 11mA */
1002 };
1003 };
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