1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Unisoc UMS512 SoC DTS file
4 *
5 * Copyright (C) 2021, Unisoc Inc.
6 */
7
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10
11 / {
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 cpus {
17 #address-cells = <2>;
18 #size-cells = <0>;
19
20 cpu-map {
21 cluster0 {
22 core0 {
23 cpu = <&CPU0>;
24 };
25 core1 {
26 cpu = <&CPU1>;
27 };
28 core2 {
29 cpu = <&CPU2>;
30 };
31 core3 {
32 cpu = <&CPU3>;
33 };
34 core4 {
35 cpu = <&CPU4>;
36 };
37 core5 {
38 cpu = <&CPU5>;
39 };
40 core6 {
41 cpu = <&CPU6>;
42 };
43 core7 {
44 cpu = <&CPU7>;
45 };
46 };
47 };
48
49 CPU0: cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a55";
52 reg = <0x0 0x0>;
53 enable-method = "psci";
54 cpu-idle-states = <&CORE_PD>;
55 };
56
57 CPU1: cpu@100 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a55";
60 reg = <0x0 0x100>;
61 enable-method = "psci";
62 cpu-idle-states = <&CORE_PD>;
63 };
64
65 CPU2: cpu@200 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a55";
68 reg = <0x0 0x200>;
69 enable-method = "psci";
70 cpu-idle-states = <&CORE_PD>;
71 };
72
73 CPU3: cpu@300 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a55";
76 reg = <0x0 0x300>;
77 enable-method = "psci";
78 cpu-idle-states = <&CORE_PD>;
79 };
80
81 CPU4: cpu@400 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a55";
84 reg = <0x0 0x400>;
85 enable-method = "psci";
86 cpu-idle-states = <&CORE_PD>;
87 };
88
89 CPU5: cpu@500 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a55";
92 reg = <0x0 0x500>;
93 enable-method = "psci";
94 cpu-idle-states = <&CORE_PD>;
95 };
96
97 CPU6: cpu@600 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a75";
100 reg = <0x0 0x600>;
101 enable-method = "psci";
102 cpu-idle-states = <&CORE_PD>;
103 };
104
105 CPU7: cpu@700 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a75";
108 reg = <0x0 0x700>;
109 enable-method = "psci";
110 cpu-idle-states = <&CORE_PD>;
111 };
112 };
113
114 idle-states {
115 entry-method = "psci";
116 CORE_PD: cpu-pd {
117 compatible = "arm,idle-state";
118 entry-latency-us = <4000>;
119 exit-latency-us = <4000>;
120 min-residency-us = <10000>;
121 local-timer-stop;
122 arm,psci-suspend-param = <0x00010000>;
123 };
124 };
125
126 psci {
127 compatible = "arm,psci-0.2";
128 method = "smc";
129 };
130
131 timer {
132 compatible = "arm,armv8-timer";
133 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
134 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
135 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
136 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
137 };
138
139 pmu-a55 {
140 compatible = "arm,cortex-a55-pmu";
141 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
147 interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
148 };
149
150 pmu-a75 {
151 compatible = "arm,cortex-a75-pmu";
152 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
154 interrupt-affinity = <&CPU6>, <&CPU7>;
155 };
156
157 soc: soc {
158 compatible = "simple-bus";
159 #address-cells = <2>;
160 #size-cells = <2>;
161 ranges;
162
163 gic: interrupt-controller@12000000 {
164 compatible = "arm,gic-v3";
165 reg = <0x0 0x12000000 0 0x20000>, /* GICD */
166 <0x0 0x12040000 0 0x100000>; /* GICR */
167 #interrupt-cells = <3>;
168 #address-cells = <2>;
169 #size-cells = <2>;
170 ranges;
171 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
172 #redistributor-regions = <1>;
173 interrupt-controller;
174 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
175 };
176
177 ap_ahb_regs: syscon@20100000 {
178 compatible = "sprd,ums512-glbregs", "syscon",
179 "simple-mfd";
180 reg = <0 0x20100000 0 0x4000>;
181 #address-cells = <1>;
182 #size-cells = <1>;
183 ranges = <0 0 0x20100000 0x4000>;
184
185 apahb_gate: clock-controller@0 {
186 compatible = "sprd,ums512-apahb-gate";
187 reg = <0x0 0x3000>;
188 clocks = <&ext_26m>;
189 clock-names = "ext-26m";
190 #clock-cells = <1>;
191 };
192 };
193
194 pub_apb_regs: syscon@31050000 {
195 compatible = "sprd,ums512-glbregs", "syscon",
196 "simple-mfd";
197 reg = <0 0x31050000 0 0x9000>;
198 };
199
200 top_dvfs_apb_regs: syscon@322a0000 {
201 compatible = "sprd,ums512-glbregs", "syscon",
202 "simple-mfd";
203 reg = <0 0x322a0000 0 0x8000>;
204 };
205
206 ap_intc0_regs: syscon@32310000 {
207 compatible = "sprd,ums512-glbregs", "syscon",
208 "simple-mfd";
209 reg = <0 0x32310000 0 0x1000>;
210 };
211
212 ap_intc1_regs: syscon@32320000 {
213 compatible = "sprd,ums512-glbregs", "syscon",
214 "simple-mfd";
215 reg = <0 0x32320000 0 0x1000>;
216 };
217
218 ap_intc2_regs: syscon@32330000 {
219 compatible = "sprd,ums512-glbregs", "syscon",
220 "simple-mfd";
221 reg = <0 0x32330000 0 0x1000>;
222 };
223
224 ap_intc3_regs: syscon@32340000 {
225 compatible = "sprd,ums512-glbregs", "syscon",
226 "simple-mfd";
227 reg = <0 0x32340000 0 0x1000>;
228 };
229
230 ap_intc4_regs: syscon@32350000 {
231 compatible = "sprd,ums512-glbregs", "syscon",
232 "simple-mfd";
233 reg = <0 0x32350000 0 0x1000>;
234 };
235
236 ap_intc5_regs: syscon@32360000 {
237 compatible = "sprd,ums512-glbregs", "syscon",
238 "simple-mfd";
239 reg = <0 0x32360000 0 0x1000>;
240 };
241
242 anlg_phy_g0_regs: syscon@32390000 {
243 compatible = "sprd,ums512-glbregs", "syscon",
244 "simple-mfd";
245 reg = <0 0x32390000 0 0x3000>;
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges = <0 0 0x32390000 0x3000>;
249
250 dpll0: clock-controller@0 {
251 compatible = "sprd,ums512-g0-pll";
252 reg = <0x0 0x100>;
253 #clock-cells = <1>;
254 };
255 };
256
257 anlg_phy_g2_regs: syscon@323b0000 {
258 compatible = "sprd,ums512-glbregs", "syscon",
259 "simple-mfd";
260 reg = <0 0x323b0000 0 0x3000>;
261 #address-cells = <1>;
262 #size-cells = <1>;
263 ranges = <0 0 0x323b0000 0x3000>;
264
265 mpll1: clock-controller@0 {
266 compatible = "sprd,ums512-g2-pll";
267 reg = <0x0 0x100>;
268 #clock-cells = <1>;
269 };
270 };
271
272 anlg_phy_g3_regs: syscon@323c0000 {
273 compatible = "sprd,ums512-glbregs", "syscon",
274 "simple-mfd";
275 reg = <0 0x323c0000 0 0x3000>;
276 #address-cells = <1>;
277 #size-cells = <1>;
278 ranges = <0 0 0x323c0000 0x3000>;
279
280 pll1: clock-controller@0 {
281 compatible = "sprd,ums512-g3-pll";
282 reg = <0x0 0x3000>;
283 clocks = <&ext_26m>;
284 clock-names = "ext-26m";
285 #clock-cells = <1>;
286 };
287 };
288
289 anlg_phy_gc_regs: syscon@323e0000 {
290 compatible = "sprd,ums512-glbregs", "syscon",
291 "simple-mfd";
292 reg = <0 0x323e0000 0 0x3000>;
293 #address-cells = <1>;
294 #size-cells = <1>;
295 ranges = <0 0 0x323e0000 0x3000>;
296
297 pll2: clock-controller@0 {
298 compatible = "sprd,ums512-gc-pll";
299 reg = <0x0 0x100>;
300 clocks = <&ext_26m>;
301 clock-names = "ext-26m";
302 #clock-cells = <1>;
303 };
304 };
305
306 anlg_phy_g10_regs: syscon@323f0000 {
307 compatible = "sprd,ums512-glbregs", "syscon",
308 "simple-mfd";
309 reg = <0 0x323f0000 0 0x3000>;
310 };
311
312 aon_apb_regs: syscon@327d0000 {
313 compatible = "sprd,ums512-glbregs", "syscon",
314 "simple-mfd";
315 reg = <0 0x327d0000 0 0x3000>;
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges = <0 0 0x327d0000 0x3000>;
319
320 aonapb_gate: clock-controller@0 {
321 compatible = "sprd,ums512-aon-gate";
322 reg = <0x0 0x3000>;
323 clocks = <&ext_26m>;
324 clock-names = "ext-26m";
325 #clock-cells = <1>;
326 };
327 };
328
329 pmu_apb_regs: syscon@327e0000 {
330 compatible = "sprd,ums512-glbregs", "syscon",
331 "simple-mfd";
332 reg = <0 0x327e0000 0 0x3000>;
333 #address-cells = <1>;
334 #size-cells = <1>;
335 ranges = <0 0 0x327e0000 0x3000>;
336
337 pmu_gate: clock-controller@0 {
338 compatible = "sprd,ums512-pmu-gate";
339 reg = <0x0 0x3000>;
340 clocks = <&ext_26m>;
341 clock-names = "ext-26m";
342 #clock-cells = <1>;
343 };
344 };
345
346 audcp_apb_regs: syscon@3350d000 {
347 compatible = "sprd,ums512-glbregs", "syscon",
348 "simple-mfd";
349 reg = <0 0x3350d000 0 0x1000>;
350 #address-cells = <1>;
351 #size-cells = <1>;
352 ranges = <0 0 0x3350d000 0x1000>;
353
354 audcpapb_gate: clock-controller@0 {
355 compatible = "sprd,ums512-audcpapb-gate";
356 reg = <0x0 0x300>;
357 #clock-cells = <1>;
358 };
359 };
360
361 audcp_ahb_regs: syscon@335e0000 {
362 compatible = "sprd,ums512-glbregs", "syscon",
363 "simple-mfd";
364 reg = <0 0x335e0000 0 0x1000>;
365 #address-cells = <1>;
366 #size-cells = <1>;
367 ranges = <0 0 0x335e0000 0x1000>;
368
369 audcpahb_gate: clock-controller@0 {
370 compatible = "sprd,ums512-audcpahb-gate";
371 reg = <0x0 0x300>;
372 #clock-cells = <1>;
373 };
374 };
375
376 gpu_apb_regs: syscon@60100000 {
377 compatible = "sprd,ums512-glbregs", "syscon",
378 "simple-mfd";
379 reg = <0 0x60100000 0 0x3000>;
380 #address-cells = <1>;
381 #size-cells = <1>;
382 ranges = <0 0 0x60100000 0x3000>;
383
384 gpu_clk: clock-controller@0 {
385 compatible = "sprd,ums512-gpu-clk";
386 clocks = <&ext_26m>;
387 clock-names = "ext-26m";
388 reg = <0x0 0x100>;
389 #clock-cells = <1>;
390 };
391 };
392
393 gpu_dvfs_apb_regs: syscon@60110000 {
394 compatible = "sprd,ums512-glbregs", "syscon",
395 "simple-mfd";
396 reg = <0 0x60110000 0 0x3000>;
397 };
398
399 mm_ahb_regs: syscon@62200000 {
400 compatible = "sprd,ums512-glbregs", "syscon",
401 "simple-mfd";
402 reg = <0 0x62200000 0 0x3000>;
403 #address-cells = <1>;
404 #size-cells = <1>;
405 ranges = <0 0 0x62200000 0x3000>;
406
407 mm_gate: clock-controller@0 {
408 compatible = "sprd,ums512-mm-gate-clk";
409 reg = <0x0 0x3000>;
410 #clock-cells = <1>;
411 };
412 };
413
414 ap_apb_regs: syscon@71000000 {
415 compatible = "sprd,ums512-glbregs", "syscon",
416 "simple-mfd";
417 reg = <0 0x71000000 0 0x3000>;
418 #address-cells = <1>;
419 #size-cells = <1>;
420 ranges = <0 0 0x71000000 0x3000>;
421
422 apapb_gate: clock-controller@0 {
423 compatible = "sprd,ums512-apapb-gate";
424 reg = <0x0 0x3000>;
425 #clock-cells = <1>;
426 };
427 };
428
429 ap_clk: clock-controller@20200000 {
430 compatible = "sprd,ums512-ap-clk";
431 reg = <0 0x20200000 0 0x1000>;
432 clocks = <&ext_26m>;
433 clock-names = "ext-26m";
434 #clock-cells = <1>;
435 };
436
437 aon_clk: clock-controller@32080000 {
438 compatible = "sprd,ums512-aonapb-clk";
439 reg = <0 0x32080000 0 0x1000>;
440 clocks = <&ext_26m>, <&ext_32k>,
441 <&ext_4m>, <&rco_100m>;
442 clock-names = "ext-26m", "ext-32k",
443 "ext-4m", "rco-100m";
444 #clock-cells = <1>;
445 };
446
447 mm_clk: clock-controller@62100000 {
448 compatible = "sprd,ums512-mm-clk";
449 reg = <0 0x62100000 0 0x1000>;
450 clocks = <&ext_26m>;
451 clock-names = "ext-26m";
452 #clock-cells = <1>;
453 };
454
455 /* SoC Funnel */
456 funnel@3c002000 {
457 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
458 reg = <0 0x3c002000 0 0x1000>;
459 clocks = <&ext_26m>;
460 clock-names = "apb_pclk";
461
462 out-ports {
463 port {
464 funnel_soc_out_port: endpoint {
465 remote-endpoint = <&etb_in>;
466 };
467 };
468 };
469
470 in-ports {
471 #address-cells = <1>;
472 #size-cells = <0>;
473
474 port@1 {
475 reg = <1>;
476 funnel_soc_in_port: endpoint {
477 remote-endpoint =
478 <&funnel_corinth_out_port>;
479 };
480 };
481 };
482 };
483
484 /* SoC ETF */
485 soc_etb: etb@3c003000 {
486 compatible = "arm,coresight-tmc", "arm,primecell";
487 reg = <0 0x3c003000 0 0x1000>;
488 clocks = <&ext_26m>;
489 clock-names = "apb_pclk";
490
491 in-ports {
492 port {
493 etb_in: endpoint {
494 remote-endpoint =
495 <&funnel_soc_out_port>;
496 };
497 };
498 };
499 };
500
501 /* AP-CPU Funnel for core3/4/5/7 */
502 funnel@3e001000 {
503 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
504 reg = <0 0x3e001000 0 0x1000>;
505 clocks = <&ext_26m>;
506 clock-names = "apb_pclk";
507
508 out-ports {
509 port {
510 funnel_corinth_lit_out_port: endpoint {
511 remote-endpoint =
512 <&corinth_etf_lit_in>;
513 };
514 };
515 };
516
517 in-ports {
518 #address-cells = <1>;
519 #size-cells = <0>;
520
521 port@0 {
522 reg = <0>;
523 funnel_core_in_port3: endpoint {
524 remote-endpoint = <&etm3_out>;
525 };
526 };
527
528 port@1 {
529 reg = <1>;
530 funnel_core_in_port4: endpoint {
531 remote-endpoint = <&etm4_out>;
532 };
533 };
534
535 port@2 {
536 reg = <2>;
537 funnel_core_in_port5: endpoint {
538 remote-endpoint = <&etm5_out>;
539 };
540 };
541
542 port@3 {
543 reg = <3>;
544 funnel_core_in_port7: endpoint {
545 remote-endpoint = <&etm7_out>;
546 };
547 };
548 };
549 };
550
551 /* AP-CPU ETF for little cores */
552 etf@3e002000 {
553 compatible = "arm,coresight-tmc", "arm,primecell";
554 reg = <0 0x3e002000 0 0x1000>;
555 clocks = <&ext_26m>;
556 clock-names = "apb_pclk";
557
558 out-ports {
559 port {
560 corinth_etf_lit_out: endpoint {
561 remote-endpoint =
562 <&funnel_corinth_from_lit_in_port>;
563 };
564 };
565 };
566
567 in-ports {
568 port {
569 corinth_etf_lit_in: endpoint {
570 remote-endpoint =
571 <&funnel_corinth_lit_out_port>;
572 };
573 };
574 };
575 };
576
577 /* AP-CPU ETF for big cores */
578 etf@3e003000 {
579 compatible = "arm,coresight-tmc", "arm,primecell";
580 reg = <0 0x3e003000 0 0x1000>;
581 clocks = <&ext_26m>;
582 clock-names = "apb_pclk";
583
584 out-ports {
585 port {
586 corinth_etf_big_out: endpoint {
587 remote-endpoint =
588 <&funnel_corinth_from_big_in_port>;
589 };
590 };
591 };
592
593 in-ports {
594 port {
595 corinth_etf_big_in: endpoint {
596 remote-endpoint =
597 <&funnel_corinth_big_out_port>;
598 };
599 };
600 };
601 };
602
603 /* Funnel to SoC */
604 funnel@3e004000 {
605 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
606 reg = <0 0x3e004000 0 0x1000>;
607 clocks = <&ext_26m>;
608 clock-names = "apb_pclk";
609
610 out-ports {
611 port {
612 funnel_corinth_out_port: endpoint {
613 remote-endpoint =
614 <&funnel_soc_in_port>;
615 };
616 };
617 };
618
619 in-ports {
620 #address-cells = <1>;
621 #size-cells = <0>;
622
623 port@0 {
624 reg = <0>;
625 funnel_corinth_from_lit_in_port: endpoint {
626 remote-endpoint = <&corinth_etf_lit_out>;
627 };
628 };
629
630 port@1 {
631 reg = <1>;
632 funnel_corinth_from_big_in_port: endpoint {
633 remote-endpoint = <&corinth_etf_big_out>;
634 };
635 };
636 };
637 };
638
639 /* AP-CPU Funnel for core0/1/2/6 */
640 funnel@3e005000 {
641 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
642 reg = <0 0x3e005000 0 0x1000>;
643 clocks = <&ext_26m>;
644 clock-names = "apb_pclk";
645
646 out-ports {
647 port {
648 funnel_corinth_big_out_port: endpoint {
649 remote-endpoint = <&corinth_etf_big_in>;
650 };
651 };
652 };
653
654 in-ports {
655 #address-cells = <1>;
656 #size-cells = <0>;
657
658 port@0 {
659 reg = <0>;
660 funnel_core_in_port0: endpoint {
661 remote-endpoint = <&etm0_out>;
662 };
663 };
664
665 port@1 {
666 reg = <1>;
667 funnel_core_in_port1: endpoint {
668 remote-endpoint = <&etm1_out>;
669 };
670 };
671
672 port@2 {
673 reg = <2>;
674 funnel_core_in_port2: endpoint {
675 remote-endpoint = <&etm2_out>;
676 };
677 };
678
679 port@3 {
680 reg = <3>;
681 funnel_core_in_port6: endpoint {
682 remote-endpoint = <&etm6_out>;
683 };
684 };
685 };
686 };
687
688 etm0: etm@3f040000 {
689 compatible = "arm,coresight-etm4x", "arm,primecell";
690 reg = <0 0x3f040000 0 0x1000>;
691 cpu = <&CPU0>;
692 clocks = <&ext_26m>;
693 clock-names = "apb_pclk";
694
695 out-ports {
696 port {
697 etm0_out: endpoint {
698 remote-endpoint =
699 <&funnel_core_in_port0>;
700 };
701 };
702 };
703 };
704
705 etm1: etm@3f140000 {
706 compatible = "arm,coresight-etm4x", "arm,primecell";
707 reg = <0 0x3f140000 0 0x1000>;
708 cpu = <&CPU1>;
709 clocks = <&ext_26m>;
710 clock-names = "apb_pclk";
711
712 out-ports {
713 port {
714 etm1_out: endpoint {
715 remote-endpoint =
716 <&funnel_core_in_port1>;
717 };
718 };
719 };
720 };
721
722 etm2: etm@3f240000 {
723 compatible = "arm,coresight-etm4x", "arm,primecell";
724 reg = <0 0x3f240000 0 0x1000>;
725 cpu = <&CPU2>;
726 clocks = <&ext_26m>;
727 clock-names = "apb_pclk";
728
729 out-ports {
730 port {
731 etm2_out: endpoint {
732 remote-endpoint =
733 <&funnel_core_in_port2>;
734 };
735 };
736 };
737 };
738
739 etm3: etm@3f340000 {
740 compatible = "arm,coresight-etm4x", "arm,primecell";
741 reg = <0 0x3f340000 0 0x1000>;
742 cpu = <&CPU3>;
743 clocks = <&ext_26m>;
744 clock-names = "apb_pclk";
745
746 out-ports {
747 port {
748 etm3_out: endpoint {
749 remote-endpoint =
750 <&funnel_core_in_port3>;
751 };
752 };
753 };
754 };
755
756 etm4: etm@3f440000 {
757 compatible = "arm,coresight-etm4x", "arm,primecell";
758 reg = <0 0x3f440000 0 0x1000>;
759 cpu = <&CPU4>;
760 clocks = <&ext_26m>;
761 clock-names = "apb_pclk";
762
763 out-ports {
764 port {
765 etm4_out: endpoint {
766 remote-endpoint =
767 <&funnel_core_in_port4>;
768 };
769 };
770 };
771 };
772
773 etm5: etm@3f540000 {
774 compatible = "arm,coresight-etm4x", "arm,primecell";
775 reg = <0 0x3f540000 0 0x1000>;
776 cpu = <&CPU5>;
777 clocks = <&ext_26m>;
778 clock-names = "apb_pclk";
779
780 out-ports {
781 port {
782 etm5_out: endpoint {
783 remote-endpoint =
784 <&funnel_core_in_port5>;
785 };
786 };
787 };
788 };
789
790 etm6: etm@3f640000 {
791 compatible = "arm,coresight-etm4x", "arm,primecell";
792 reg = <0 0x3f640000 0 0x1000>;
793 cpu = <&CPU6>;
794 clocks = <&ext_26m>;
795 clock-names = "apb_pclk";
796
797 out-ports {
798 port {
799 etm6_out: endpoint {
800 remote-endpoint =
801 <&funnel_core_in_port6>;
802 };
803 };
804 };
805 };
806
807 etm7: etm@3f740000 {
808 compatible = "arm,coresight-etm4x", "arm,primecell";
809 reg = <0 0x3f740000 0 0x1000>;
810 cpu = <&CPU7>;
811 clocks = <&ext_26m>;
812 clock-names = "apb_pclk";
813
814 out-ports {
815 port {
816 etm7_out: endpoint {
817 remote-endpoint =
818 <&funnel_core_in_port7>;
819 };
820 };
821 };
822 };
823
824 apb@70000000 {
825 compatible = "simple-bus";
826 #address-cells = <1>;
827 #size-cells = <1>;
828 ranges = <0 0x0 0x70000000 0x10000000>;
829
830 uart0: serial@0 {
831 compatible = "sprd,ums512-uart",
832 "sprd,sc9836-uart";
833 reg = <0x0 0x100>;
834 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&ext_26m>;
836 status = "disabled";
837 };
838
839 uart1: serial@100000 {
840 compatible = "sprd,ums512-uart",
841 "sprd,sc9836-uart";
842 reg = <0x100000 0x100>;
843 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&ext_26m>;
845 status = "disabled";
846 };
847
848 sdio0: mmc@1100000 {
849 compatible = "sprd,sdhci-r11";
850 reg = <0x1100000 0x1000>;
851 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
852 clock-names = "sdio", "enable";
853 clocks = <&ap_clk CLK_SDIO0_2X>,
854 <&apapb_gate CLK_SDIO0_EB>;
855 assigned-clocks = <&ap_clk CLK_SDIO0_2X>;
856 assigned-clock-parents = <&pll1 CLK_RPLL>;
857 status = "disabled";
858 };
859
860 sdio3: mmc@1400000 {
861 compatible = "sprd,sdhci-r11";
862 reg = <0x1400000 0x1000>;
863 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
864 clock-names = "sdio", "enable";
865 clocks = <&ap_clk CLK_EMMC_2X>,
866 <&apapb_gate CLK_EMMC_EB>;
867 assigned-clocks = <&ap_clk CLK_EMMC_2X>;
868 assigned-clock-parents = <&pll1 CLK_RPLL>;
869 status = "disabled";
870 };
871 };
872
873 aon: bus@32000000 {
874 compatible = "simple-bus";
875 #address-cells = <1>;
876 #size-cells = <1>;
877 ranges = <0 0x0 0x32000000 0x1000000>;
878
879 adi_bus: spi@100000 {
880 compatible = "sprd,ums512-adi";
881 reg = <0x100000 0x100000>;
882 #address-cells = <1>;
883 #size-cells = <0>;
884 sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>,
885 <17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>,
886 <35 0x19b8>, <39 0x19ac>;
887 };
888 };
889 };
890
891 ext_26m: clk-26m {
892 compatible = "fixed-clock";
893 #clock-cells = <0>;
894 clock-frequency = <26000000>;
895 clock-output-names = "ext-26m";
896 };
897
898 ext_32k: clk-32k {
899 compatible = "fixed-clock";
900 #clock-cells = <0>;
901 clock-frequency = <32768>;
902 clock-output-names = "ext-32k";
903 };
904
905 ext_4m: clk-4m {
906 compatible = "fixed-clock";
907 #clock-cells = <0>;
908 clock-frequency = <4000000>;
909 clock-output-names = "ext-4m";
910 };
911
912 rco_100m: clk-100m {
913 compatible = "fixed-clock";
914 #clock-cells = <0>;
915 clock-frequency = <100000000>;
916 clock-output-names = "rco-100m";
917 };
918 };
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