1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree Source for AM625 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8 &cbass_main {
9 oc_sram: sram@70000000 {
10 compatible = "mmio-sram";
11 reg = <0x00 0x70000000 0x00 0x10000>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
15 };
16
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
21 ranges;
22 #interrupt-cells = <3>;
23 interrupt-controller;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
27 <0x01 0x00000000 0x00 0x2000>, /* GICC */
28 <0x01 0x00010000 0x00 0x1000>, /* GICH */
29 <0x01 0x00020000 0x00 0x2000>; /* GICV */
30 /*
31 * vcpumntirq:
32 * virtual CPU interface maintenance interrupt
33 */
34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
35
36 gic_its: msi-controller@1820000 {
37 compatible = "arm,gic-v3-its";
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
40 msi-controller;
41 #msi-cells = <1>;
42 };
43 };
44
45 main_conf: bus@100000 {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges = <0x0 0x00 0x00100000 0x20000>;
50
51 phy_gmii_sel: phy@4044 {
52 compatible = "ti,am654-phy-gmii-sel";
53 reg = <0x4044 0x8>;
54 #phy-cells = <1>;
55 };
56
57 epwm_tbclk: clock-controller@4130 {
58 compatible = "ti,am62-epwm-tbclk";
59 reg = <0x4130 0x4>;
60 #clock-cells = <1>;
61 };
62
63 audio_refclk0: clock-controller@82e0 {
64 compatible = "ti,am62-audio-refclk";
65 reg = <0x82e0 0x4>;
66 clocks = <&k3_clks 157 0>;
67 assigned-clocks = <&k3_clks 157 0>;
68 assigned-clock-parents = <&k3_clks 157 8>;
69 #clock-cells = <0>;
70 };
71
72 audio_refclk1: clock-controller@82e4 {
73 compatible = "ti,am62-audio-refclk";
74 reg = <0x82e4 0x4>;
75 clocks = <&k3_clks 157 10>;
76 assigned-clocks = <&k3_clks 157 10>;
77 assigned-clock-parents = <&k3_clks 157 18>;
78 #clock-cells = <0>;
79 };
80 };
81
82 dmss: bus@48000000 {
83 bootph-all;
84 compatible = "simple-bus";
85 #address-cells = <2>;
86 #size-cells = <2>;
87 dma-ranges;
88 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
89
90 ti,sci-dev-id = <25>;
91
92 secure_proxy_main: mailbox@4d000000 {
93 bootph-all;
94 compatible = "ti,am654-secure-proxy";
95 #mbox-cells = <1>;
96 reg-names = "target_data", "rt", "scfg";
97 reg = <0x00 0x4d000000 0x00 0x80000>,
98 <0x00 0x4a600000 0x00 0x80000>,
99 <0x00 0x4a400000 0x00 0x80000>;
100 interrupt-names = "rx_012";
101 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
102 };
103
104 inta_main_dmss: interrupt-controller@48000000 {
105 compatible = "ti,sci-inta";
106 reg = <0x00 0x48000000 0x00 0x100000>;
107 #interrupt-cells = <0>;
108 interrupt-controller;
109 interrupt-parent = <&gic500>;
110 msi-controller;
111 ti,sci = <&dmsc>;
112 ti,sci-dev-id = <28>;
113 ti,interrupt-ranges = <4 68 36>;
114 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
115 };
116
117 main_bcdma: dma-controller@485c0100 {
118 compatible = "ti,am64-dmss-bcdma";
119 reg = <0x00 0x485c0100 0x00 0x100>,
120 <0x00 0x4c000000 0x00 0x20000>,
121 <0x00 0x4a820000 0x00 0x20000>,
122 <0x00 0x4aa40000 0x00 0x20000>,
123 <0x00 0x4bc00000 0x00 0x100000>,
124 <0x00 0x48600000 0x00 0x8000>,
125 <0x00 0x484a4000 0x00 0x2000>,
126 <0x00 0x484c2000 0x00 0x2000>,
127 <0x00 0x48420000 0x00 0x2000>;
128 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
129 "ring", "tchan", "rchan", "bchan";
130 msi-parent = <&inta_main_dmss>;
131 #dma-cells = <3>;
132
133 ti,sci = <&dmsc>;
134 ti,sci-dev-id = <26>;
135 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
136 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
137 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
138 };
139
140 main_pktdma: dma-controller@485c0000 {
141 compatible = "ti,am64-dmss-pktdma";
142 reg = <0x00 0x485c0000 0x00 0x100>,
143 <0x00 0x4a800000 0x00 0x20000>,
144 <0x00 0x4aa00000 0x00 0x20000>,
145 <0x00 0x4b800000 0x00 0x200000>,
146 <0x00 0x485e0000 0x00 0x10000>,
147 <0x00 0x484a0000 0x00 0x2000>,
148 <0x00 0x484c0000 0x00 0x2000>,
149 <0x00 0x48430000 0x00 0x1000>;
150 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
151 "ring", "tchan", "rchan", "rflow";
152 msi-parent = <&inta_main_dmss>;
153 #dma-cells = <2>;
154
155 ti,sci = <&dmsc>;
156 ti,sci-dev-id = <30>;
157 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
158 <0x24>, /* CPSW_TX_CHAN */
159 <0x25>, /* SAUL_TX_0_CHAN */
160 <0x26>; /* SAUL_TX_1_CHAN */
161 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
162 <0x11>, /* RING_CPSW_TX_CHAN */
163 <0x12>, /* RING_SAUL_TX_0_CHAN */
164 <0x13>; /* RING_SAUL_TX_1_CHAN */
165 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
166 <0x2b>, /* CPSW_RX_CHAN */
167 <0x2d>, /* SAUL_RX_0_CHAN */
168 <0x2f>, /* SAUL_RX_1_CHAN */
169 <0x31>, /* SAUL_RX_2_CHAN */
170 <0x33>; /* SAUL_RX_3_CHAN */
171 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
172 <0x2c>, /* FLOW_CPSW_RX_CHAN */
173 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
174 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
175 };
176 };
177
178 dmsc: system-controller@44043000 {
179 bootph-all;
180 compatible = "ti,k2g-sci";
181 ti,host-id = <12>;
182 mbox-names = "rx", "tx";
183 mboxes = <&secure_proxy_main 12>,
184 <&secure_proxy_main 13>;
185 reg-names = "debug_messages";
186 reg = <0x00 0x44043000 0x00 0xfe0>;
187
188 k3_pds: power-controller {
189 bootph-all;
190 compatible = "ti,sci-pm-domain";
191 #power-domain-cells = <2>;
192 };
193
194 k3_clks: clock-controller {
195 bootph-all;
196 compatible = "ti,k2g-sci-clk";
197 #clock-cells = <2>;
198 };
199
200 k3_reset: reset-controller {
201 bootph-all;
202 compatible = "ti,sci-reset";
203 #reset-cells = <2>;
204 };
205 };
206
207 crypto: crypto@40900000 {
208 compatible = "ti,am62-sa3ul";
209 reg = <0x00 0x40900000 0x00 0x1200>;
210 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
211 <&main_pktdma 0x7507 0>;
212 dma-names = "tx", "rx1", "rx2";
213 };
214
215 secure_proxy_sa3: mailbox@43600000 {
216 bootph-pre-ram;
217 compatible = "ti,am654-secure-proxy";
218 #mbox-cells = <1>;
219 reg-names = "target_data", "rt", "scfg";
220 reg = <0x00 0x43600000 0x00 0x10000>,
221 <0x00 0x44880000 0x00 0x20000>,
222 <0x00 0x44860000 0x00 0x20000>;
223 /*
224 * Marked Disabled:
225 * Node is incomplete as it is meant for bootloaders and
226 * firmware on non-MPU processors
227 */
228 status = "disabled";
229 };
230
231 main_pmx0: pinctrl@f4000 {
232 bootph-all;
233 compatible = "pinctrl-single";
234 reg = <0x00 0xf4000 0x00 0x2ac>;
235 #pinctrl-cells = <1>;
236 pinctrl-single,register-width = <32>;
237 pinctrl-single,function-mask = <0xffffffff>;
238 };
239
240 main_esm: esm@420000 {
241 bootph-pre-ram;
242 compatible = "ti,j721e-esm";
243 reg = <0x00 0x420000 0x00 0x1000>;
244 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
245 };
246
247 main_timer0: timer@2400000 {
248 bootph-all;
249 compatible = "ti,am654-timer";
250 reg = <0x00 0x2400000 0x00 0x400>;
251 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&k3_clks 36 2>;
253 clock-names = "fck";
254 assigned-clocks = <&k3_clks 36 2>;
255 assigned-clock-parents = <&k3_clks 36 3>;
256 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
257 ti,timer-pwm;
258 };
259
260 main_timer1: timer@2410000 {
261 compatible = "ti,am654-timer";
262 reg = <0x00 0x2410000 0x00 0x400>;
263 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&k3_clks 37 2>;
265 clock-names = "fck";
266 assigned-clocks = <&k3_clks 37 2>;
267 assigned-clock-parents = <&k3_clks 37 3>;
268 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
269 ti,timer-pwm;
270 };
271
272 main_timer2: timer@2420000 {
273 compatible = "ti,am654-timer";
274 reg = <0x00 0x2420000 0x00 0x400>;
275 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&k3_clks 38 2>;
277 clock-names = "fck";
278 assigned-clocks = <&k3_clks 38 2>;
279 assigned-clock-parents = <&k3_clks 38 3>;
280 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
281 ti,timer-pwm;
282 };
283
284 main_timer3: timer@2430000 {
285 compatible = "ti,am654-timer";
286 reg = <0x00 0x2430000 0x00 0x400>;
287 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&k3_clks 39 2>;
289 clock-names = "fck";
290 assigned-clocks = <&k3_clks 39 2>;
291 assigned-clock-parents = <&k3_clks 39 3>;
292 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
293 ti,timer-pwm;
294 };
295
296 main_timer4: timer@2440000 {
297 compatible = "ti,am654-timer";
298 reg = <0x00 0x2440000 0x00 0x400>;
299 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&k3_clks 40 2>;
301 clock-names = "fck";
302 assigned-clocks = <&k3_clks 40 2>;
303 assigned-clock-parents = <&k3_clks 40 3>;
304 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
305 ti,timer-pwm;
306 };
307
308 main_timer5: timer@2450000 {
309 compatible = "ti,am654-timer";
310 reg = <0x00 0x2450000 0x00 0x400>;
311 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&k3_clks 41 2>;
313 clock-names = "fck";
314 assigned-clocks = <&k3_clks 41 2>;
315 assigned-clock-parents = <&k3_clks 41 3>;
316 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
317 ti,timer-pwm;
318 };
319
320 main_timer6: timer@2460000 {
321 compatible = "ti,am654-timer";
322 reg = <0x00 0x2460000 0x00 0x400>;
323 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&k3_clks 42 2>;
325 clock-names = "fck";
326 assigned-clocks = <&k3_clks 42 2>;
327 assigned-clock-parents = <&k3_clks 42 3>;
328 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
329 ti,timer-pwm;
330 };
331
332 main_timer7: timer@2470000 {
333 compatible = "ti,am654-timer";
334 reg = <0x00 0x2470000 0x00 0x400>;
335 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&k3_clks 43 2>;
337 clock-names = "fck";
338 assigned-clocks = <&k3_clks 43 2>;
339 assigned-clock-parents = <&k3_clks 43 3>;
340 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
341 ti,timer-pwm;
342 };
343
344 main_uart0: serial@2800000 {
345 compatible = "ti,am64-uart", "ti,am654-uart";
346 reg = <0x00 0x02800000 0x00 0x100>;
347 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
348 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
349 clocks = <&k3_clks 146 0>;
350 clock-names = "fclk";
351 status = "disabled";
352 };
353
354 main_uart1: serial@2810000 {
355 compatible = "ti,am64-uart", "ti,am654-uart";
356 reg = <0x00 0x02810000 0x00 0x100>;
357 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
358 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
359 clocks = <&k3_clks 152 0>;
360 clock-names = "fclk";
361 status = "disabled";
362 };
363
364 main_uart2: serial@2820000 {
365 compatible = "ti,am64-uart", "ti,am654-uart";
366 reg = <0x00 0x02820000 0x00 0x100>;
367 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
368 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
369 clocks = <&k3_clks 153 0>;
370 clock-names = "fclk";
371 status = "disabled";
372 };
373
374 main_uart3: serial@2830000 {
375 compatible = "ti,am64-uart", "ti,am654-uart";
376 reg = <0x00 0x02830000 0x00 0x100>;
377 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
378 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
379 clocks = <&k3_clks 154 0>;
380 clock-names = "fclk";
381 status = "disabled";
382 };
383
384 main_uart4: serial@2840000 {
385 compatible = "ti,am64-uart", "ti,am654-uart";
386 reg = <0x00 0x02840000 0x00 0x100>;
387 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
388 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
389 clocks = <&k3_clks 155 0>;
390 clock-names = "fclk";
391 status = "disabled";
392 };
393
394 main_uart5: serial@2850000 {
395 compatible = "ti,am64-uart", "ti,am654-uart";
396 reg = <0x00 0x02850000 0x00 0x100>;
397 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
398 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
399 clocks = <&k3_clks 156 0>;
400 clock-names = "fclk";
401 status = "disabled";
402 };
403
404 main_uart6: serial@2860000 {
405 compatible = "ti,am64-uart", "ti,am654-uart";
406 reg = <0x00 0x02860000 0x00 0x100>;
407 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
408 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
409 clocks = <&k3_clks 158 0>;
410 clock-names = "fclk";
411 status = "disabled";
412 };
413
414 main_i2c0: i2c@20000000 {
415 compatible = "ti,am64-i2c", "ti,omap4-i2c";
416 reg = <0x00 0x20000000 0x00 0x100>;
417 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
418 #address-cells = <1>;
419 #size-cells = <0>;
420 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
421 clocks = <&k3_clks 102 2>;
422 clock-names = "fck";
423 status = "disabled";
424 };
425
426 main_i2c1: i2c@20010000 {
427 compatible = "ti,am64-i2c", "ti,omap4-i2c";
428 reg = <0x00 0x20010000 0x00 0x100>;
429 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
431 #size-cells = <0>;
432 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
433 clocks = <&k3_clks 103 2>;
434 clock-names = "fck";
435 status = "disabled";
436 };
437
438 main_i2c2: i2c@20020000 {
439 compatible = "ti,am64-i2c", "ti,omap4-i2c";
440 reg = <0x00 0x20020000 0x00 0x100>;
441 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
442 #address-cells = <1>;
443 #size-cells = <0>;
444 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
445 clocks = <&k3_clks 104 2>;
446 clock-names = "fck";
447 status = "disabled";
448 };
449
450 main_i2c3: i2c@20030000 {
451 compatible = "ti,am64-i2c", "ti,omap4-i2c";
452 reg = <0x00 0x20030000 0x00 0x100>;
453 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
455 #size-cells = <0>;
456 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
457 clocks = <&k3_clks 105 2>;
458 clock-names = "fck";
459 status = "disabled";
460 };
461
462 main_spi0: spi@20100000 {
463 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
464 reg = <0x00 0x20100000 0x00 0x400>;
465 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
466 #address-cells = <1>;
467 #size-cells = <0>;
468 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
469 clocks = <&k3_clks 141 0>;
470 status = "disabled";
471 };
472
473 main_spi1: spi@20110000 {
474 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
475 reg = <0x00 0x20110000 0x00 0x400>;
476 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
477 #address-cells = <1>;
478 #size-cells = <0>;
479 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
480 clocks = <&k3_clks 142 0>;
481 status = "disabled";
482 };
483
484 main_spi2: spi@20120000 {
485 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
486 reg = <0x00 0x20120000 0x00 0x400>;
487 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
488 #address-cells = <1>;
489 #size-cells = <0>;
490 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
491 clocks = <&k3_clks 143 0>;
492 status = "disabled";
493 };
494
495 main_gpio_intr: interrupt-controller@a00000 {
496 compatible = "ti,sci-intr";
497 reg = <0x00 0x00a00000 0x00 0x800>;
498 ti,intr-trigger-type = <1>;
499 interrupt-controller;
500 interrupt-parent = <&gic500>;
501 #interrupt-cells = <1>;
502 ti,sci = <&dmsc>;
503 ti,sci-dev-id = <3>;
504 ti,interrupt-ranges = <0 32 16>;
505 };
506
507 main_gpio0: gpio@600000 {
508 compatible = "ti,am64-gpio", "ti,keystone-gpio";
509 reg = <0x0 0x00600000 0x0 0x100>;
510 gpio-ranges = <&main_pmx0 0 0 32>,
511 <&main_pmx0 32 33 38>,
512 <&main_pmx0 70 72 22>;
513 gpio-controller;
514 #gpio-cells = <2>;
515 interrupt-parent = <&main_gpio_intr>;
516 interrupts = <190>, <191>, <192>,
517 <193>, <194>, <195>;
518 interrupt-controller;
519 #interrupt-cells = <2>;
520 ti,ngpio = <92>;
521 ti,davinci-gpio-unbanked = <0>;
522 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
523 clocks = <&k3_clks 77 0>;
524 clock-names = "gpio";
525 };
526
527 main_gpio1: gpio@601000 {
528 compatible = "ti,am64-gpio", "ti,keystone-gpio";
529 reg = <0x0 0x00601000 0x0 0x100>;
530 gpio-controller;
531 gpio-ranges = <&main_pmx0 0 94 41>,
532 <&main_pmx0 41 136 6>,
533 <&main_pmx0 47 143 3>,
534 <&main_pmx0 50 149 2>;
535 #gpio-cells = <2>;
536 interrupt-parent = <&main_gpio_intr>;
537 interrupts = <180>, <181>, <182>,
538 <183>, <184>, <185>;
539 interrupt-controller;
540 #interrupt-cells = <2>;
541 ti,ngpio = <52>;
542 ti,davinci-gpio-unbanked = <0>;
543 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
544 clocks = <&k3_clks 78 0>;
545 clock-names = "gpio";
546 };
547
548 sdhci0: mmc@fa10000 {
549 compatible = "ti,am62-sdhci";
550 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
551 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
552 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
553 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
554 clock-names = "clk_ahb", "clk_xin";
555 assigned-clocks = <&k3_clks 57 6>;
556 assigned-clock-parents = <&k3_clks 57 8>;
557 bus-width = <8>;
558 mmc-ddr-1_8v;
559 mmc-hs200-1_8v;
560 ti,clkbuf-sel = <0x7>;
561 ti,otap-del-sel-legacy = <0x0>;
562 ti,otap-del-sel-mmc-hs = <0x0>;
563 ti,otap-del-sel-ddr52 = <0x5>;
564 ti,otap-del-sel-hs200 = <0x5>;
565 ti,itap-del-sel-legacy = <0xa>;
566 ti,itap-del-sel-mmc-hs = <0x1>;
567 status = "disabled";
568 };
569
570 sdhci1: mmc@fa00000 {
571 compatible = "ti,am62-sdhci";
572 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
573 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
574 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
575 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
576 clock-names = "clk_ahb", "clk_xin";
577 bus-width = <4>;
578 ti,clkbuf-sel = <0x7>;
579 ti,otap-del-sel-legacy = <0x8>;
580 ti,otap-del-sel-sd-hs = <0x0>;
581 ti,otap-del-sel-sdr12 = <0x0>;
582 ti,otap-del-sel-sdr25 = <0x0>;
583 ti,otap-del-sel-sdr50 = <0x8>;
584 ti,otap-del-sel-sdr104 = <0x7>;
585 ti,otap-del-sel-ddr50 = <0x4>;
586 ti,itap-del-sel-legacy = <0xa>;
587 ti,itap-del-sel-sd-hs = <0x1>;
588 ti,itap-del-sel-sdr12 = <0xa>;
589 ti,itap-del-sel-sdr25 = <0x1>;
590 status = "disabled";
591 };
592
593 sdhci2: mmc@fa20000 {
594 compatible = "ti,am62-sdhci";
595 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
596 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
597 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
598 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
599 clock-names = "clk_ahb", "clk_xin";
600 bus-width = <4>;
601 ti,clkbuf-sel = <0x7>;
602 ti,otap-del-sel-legacy = <0x8>;
603 ti,otap-del-sel-sd-hs = <0x0>;
604 ti,otap-del-sel-sdr12 = <0x0>;
605 ti,otap-del-sel-sdr25 = <0x0>;
606 ti,otap-del-sel-sdr50 = <0x8>;
607 ti,otap-del-sel-sdr104 = <0x7>;
608 ti,otap-del-sel-ddr50 = <0x8>;
609 ti,itap-del-sel-legacy = <0xa>;
610 ti,itap-del-sel-sd-hs = <0xa>;
611 ti,itap-del-sel-sdr12 = <0xa>;
612 ti,itap-del-sel-sdr25 = <0x1>;
613 status = "disabled";
614 };
615
616 usbss0: dwc3-usb@f900000 {
617 compatible = "ti,am62-usb";
618 reg = <0x00 0x0f900000 0x00 0x800>,
619 <0x00 0x0f908000 0x00 0x400>;
620 clocks = <&k3_clks 161 3>;
621 clock-names = "ref";
622 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
623 #address-cells = <2>;
624 #size-cells = <2>;
625 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
626 ranges;
627 status = "disabled";
628
629 usb0: usb@31000000 {
630 compatible = "snps,dwc3";
631 reg = <0x00 0x31000000 0x00 0x50000>;
632 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
633 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
634 interrupt-names = "host", "peripheral";
635 maximum-speed = "high-speed";
636 dr_mode = "otg";
637 snps,usb2-gadget-lpm-disable;
638 snps,usb2-lpm-disable;
639 };
640 };
641
642 usbss1: dwc3-usb@f910000 {
643 compatible = "ti,am62-usb";
644 reg = <0x00 0x0f910000 0x00 0x800>,
645 <0x00 0x0f918000 0x00 0x400>;
646 clocks = <&k3_clks 162 3>;
647 clock-names = "ref";
648 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
649 #address-cells = <2>;
650 #size-cells = <2>;
651 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
652 ranges;
653 status = "disabled";
654
655 usb1: usb@31100000 {
656 compatible = "snps,dwc3";
657 reg = <0x00 0x31100000 0x00 0x50000>;
658 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
659 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
660 interrupt-names = "host", "peripheral";
661 maximum-speed = "high-speed";
662 dr_mode = "otg";
663 snps,usb2-gadget-lpm-disable;
664 snps,usb2-lpm-disable;
665 };
666 };
667
668 fss: bus@fc00000 {
669 compatible = "simple-bus";
670 reg = <0x00 0x0fc00000 0x00 0x70000>;
671 #address-cells = <2>;
672 #size-cells = <2>;
673 ranges;
674
675 ospi0: spi@fc40000 {
676 compatible = "ti,am654-ospi", "cdns,qspi-nor";
677 reg = <0x00 0x0fc40000 0x00 0x100>,
678 <0x05 0x00000000 0x01 0x00000000>;
679 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
680 cdns,fifo-depth = <256>;
681 cdns,fifo-width = <4>;
682 cdns,trigger-address = <0x0>;
683 clocks = <&k3_clks 75 7>;
684 assigned-clocks = <&k3_clks 75 7>;
685 assigned-clock-parents = <&k3_clks 75 8>;
686 assigned-clock-rates = <166666666>;
687 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
688 #address-cells = <1>;
689 #size-cells = <0>;
690 status = "disabled";
691 };
692 };
693
694 gpu: gpu@fd00000 {
695 compatible = "ti,am62-gpu", "img,img-axe";
696 reg = <0x00 0x0fd00000 0x00 0x20000>;
697 clocks = <&k3_clks 187 0>;
698 clock-names = "core";
699 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
700 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
701 };
702
703 cpsw3g: ethernet@8000000 {
704 compatible = "ti,am642-cpsw-nuss";
705 #address-cells = <2>;
706 #size-cells = <2>;
707 reg = <0x00 0x08000000 0x00 0x200000>;
708 reg-names = "cpsw_nuss";
709 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
710 clocks = <&k3_clks 13 0>;
711 assigned-clocks = <&k3_clks 13 3>;
712 assigned-clock-parents = <&k3_clks 13 11>;
713 clock-names = "fck";
714 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
715
716 dmas = <&main_pktdma 0xc600 15>,
717 <&main_pktdma 0xc601 15>,
718 <&main_pktdma 0xc602 15>,
719 <&main_pktdma 0xc603 15>,
720 <&main_pktdma 0xc604 15>,
721 <&main_pktdma 0xc605 15>,
722 <&main_pktdma 0xc606 15>,
723 <&main_pktdma 0xc607 15>,
724 <&main_pktdma 0x4600 15>;
725 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
726 "tx7", "rx";
727
728 ethernet-ports {
729 #address-cells = <1>;
730 #size-cells = <0>;
731
732 cpsw_port1: port@1 {
733 reg = <1>;
734 ti,mac-only;
735 label = "port1";
736 phys = <&phy_gmii_sel 1>;
737 mac-address = [00 00 00 00 00 00];
738 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
739 };
740
741 cpsw_port2: port@2 {
742 reg = <2>;
743 ti,mac-only;
744 label = "port2";
745 phys = <&phy_gmii_sel 2>;
746 mac-address = [00 00 00 00 00 00];
747 };
748 };
749
750 cpsw3g_mdio: mdio@f00 {
751 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
752 reg = <0x00 0xf00 0x00 0x100>;
753 #address-cells = <1>;
754 #size-cells = <0>;
755 clocks = <&k3_clks 13 0>;
756 clock-names = "fck";
757 bus_freq = <1000000>;
758 status = "disabled";
759 };
760
761 cpts@3d000 {
762 compatible = "ti,j721e-cpts";
763 reg = <0x00 0x3d000 0x00 0x400>;
764 clocks = <&k3_clks 13 3>;
765 clock-names = "cpts";
766 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
767 interrupt-names = "cpts";
768 ti,cpts-ext-ts-inputs = <4>;
769 ti,cpts-periodic-outputs = <2>;
770 };
771 };
772
773 dss: dss@30200000 {
774 compatible = "ti,am625-dss";
775 reg = <0x00 0x30200000 0x00 0x1000>, /* common */
776 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
777 <0x00 0x30206000 0x00 0x1000>, /* vid */
778 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
779 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
780 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
781 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
782 <0x00 0x30201000 0x00 0x1000>; /* common1 */
783 reg-names = "common", "vidl1", "vid",
784 "ovr1", "ovr2", "vp1", "vp2", "common1";
785 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
786 clocks = <&k3_clks 186 6>,
787 <&dss_vp1_clk>,
788 <&k3_clks 186 2>;
789 clock-names = "fck", "vp1", "vp2";
790 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
791 status = "disabled";
792
793 dss_ports: ports {
794 #address-cells = <1>;
795 #size-cells = <0>;
796 };
797 };
798
799 hwspinlock: spinlock@2a000000 {
800 compatible = "ti,am64-hwspinlock";
801 reg = <0x00 0x2a000000 0x00 0x1000>;
802 #hwlock-cells = <1>;
803 };
804
805 mailbox0_cluster0: mailbox@29000000 {
806 compatible = "ti,am64-mailbox";
807 reg = <0x00 0x29000000 0x00 0x200>;
808 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
810 #mbox-cells = <1>;
811 ti,mbox-num-users = <4>;
812 ti,mbox-num-fifos = <16>;
813 };
814
815 ecap0: pwm@23100000 {
816 compatible = "ti,am3352-ecap";
817 #pwm-cells = <3>;
818 reg = <0x00 0x23100000 0x00 0x100>;
819 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
820 clocks = <&k3_clks 51 0>;
821 clock-names = "fck";
822 status = "disabled";
823 };
824
825 ecap1: pwm@23110000 {
826 compatible = "ti,am3352-ecap";
827 #pwm-cells = <3>;
828 reg = <0x00 0x23110000 0x00 0x100>;
829 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
830 clocks = <&k3_clks 52 0>;
831 clock-names = "fck";
832 status = "disabled";
833 };
834
835 ecap2: pwm@23120000 {
836 compatible = "ti,am3352-ecap";
837 #pwm-cells = <3>;
838 reg = <0x00 0x23120000 0x00 0x100>;
839 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
840 clocks = <&k3_clks 53 0>;
841 clock-names = "fck";
842 status = "disabled";
843 };
844
845 main_mcan0: can@20701000 {
846 compatible = "bosch,m_can";
847 reg = <0x00 0x20701000 0x00 0x200>,
848 <0x00 0x20708000 0x00 0x8000>;
849 reg-names = "m_can", "message_ram";
850 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
851 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
852 clock-names = "hclk", "cclk";
853 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
855 interrupt-names = "int0", "int1";
856 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
857 status = "disabled";
858 };
859
860 main_rti0: watchdog@e000000 {
861 compatible = "ti,j7-rti-wdt";
862 reg = <0x00 0x0e000000 0x00 0x100>;
863 clocks = <&k3_clks 125 0>;
864 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
865 assigned-clocks = <&k3_clks 125 0>;
866 assigned-clock-parents = <&k3_clks 125 2>;
867 };
868
869 main_rti1: watchdog@e010000 {
870 compatible = "ti,j7-rti-wdt";
871 reg = <0x00 0x0e010000 0x00 0x100>;
872 clocks = <&k3_clks 126 0>;
873 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
874 assigned-clocks = <&k3_clks 126 0>;
875 assigned-clock-parents = <&k3_clks 126 2>;
876 };
877
878 main_rti2: watchdog@e020000 {
879 compatible = "ti,j7-rti-wdt";
880 reg = <0x00 0x0e020000 0x00 0x100>;
881 clocks = <&k3_clks 127 0>;
882 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
883 assigned-clocks = <&k3_clks 127 0>;
884 assigned-clock-parents = <&k3_clks 127 2>;
885 };
886
887 main_rti3: watchdog@e030000 {
888 compatible = "ti,j7-rti-wdt";
889 reg = <0x00 0x0e030000 0x00 0x100>;
890 clocks = <&k3_clks 128 0>;
891 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
892 assigned-clocks = <&k3_clks 128 0>;
893 assigned-clock-parents = <&k3_clks 128 2>;
894 };
895
896 main_rti15: watchdog@e0f0000 {
897 compatible = "ti,j7-rti-wdt";
898 reg = <0x00 0x0e0f0000 0x00 0x100>;
899 clocks = <&k3_clks 130 0>;
900 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>;
901 assigned-clocks = <&k3_clks 130 0>;
902 assigned-clock-parents = <&k3_clks 130 2>;
903 };
904
905 epwm0: pwm@23000000 {
906 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
907 #pwm-cells = <3>;
908 reg = <0x00 0x23000000 0x00 0x100>;
909 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
910 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
911 clock-names = "tbclk", "fck";
912 status = "disabled";
913 };
914
915 epwm1: pwm@23010000 {
916 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
917 #pwm-cells = <3>;
918 reg = <0x00 0x23010000 0x00 0x100>;
919 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
920 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
921 clock-names = "tbclk", "fck";
922 status = "disabled";
923 };
924
925 epwm2: pwm@23020000 {
926 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
927 #pwm-cells = <3>;
928 reg = <0x00 0x23020000 0x00 0x100>;
929 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
930 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
931 clock-names = "tbclk", "fck";
932 status = "disabled";
933 };
934
935 mcasp0: audio-controller@2b00000 {
936 compatible = "ti,am33xx-mcasp-audio";
937 reg = <0x00 0x02b00000 0x00 0x2000>,
938 <0x00 0x02b08000 0x00 0x400>;
939 reg-names = "mpu", "dat";
940 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
942 interrupt-names = "tx", "rx";
943
944 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
945 dma-names = "tx", "rx";
946
947 clocks = <&k3_clks 190 0>;
948 clock-names = "fck";
949 assigned-clocks = <&k3_clks 190 0>;
950 assigned-clock-parents = <&k3_clks 190 2>;
951 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
952 status = "disabled";
953 };
954
955 mcasp1: audio-controller@2b10000 {
956 compatible = "ti,am33xx-mcasp-audio";
957 reg = <0x00 0x02b10000 0x00 0x2000>,
958 <0x00 0x02b18000 0x00 0x400>;
959 reg-names = "mpu", "dat";
960 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
962 interrupt-names = "tx", "rx";
963
964 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
965 dma-names = "tx", "rx";
966
967 clocks = <&k3_clks 191 0>;
968 clock-names = "fck";
969 assigned-clocks = <&k3_clks 191 0>;
970 assigned-clock-parents = <&k3_clks 191 2>;
971 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
972 status = "disabled";
973 };
974
975 mcasp2: audio-controller@2b20000 {
976 compatible = "ti,am33xx-mcasp-audio";
977 reg = <0x00 0x02b20000 0x00 0x2000>,
978 <0x00 0x02b28000 0x00 0x400>;
979 reg-names = "mpu", "dat";
980 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
982 interrupt-names = "tx", "rx";
983
984 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
985 dma-names = "tx", "rx";
986
987 clocks = <&k3_clks 192 0>;
988 clock-names = "fck";
989 assigned-clocks = <&k3_clks 192 0>;
990 assigned-clock-parents = <&k3_clks 192 2>;
991 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
992 status = "disabled";
993 };
994
995 ti_csi2rx0: ticsi2rx@30102000 {
996 compatible = "ti,j721e-csi2rx-shim";
997 dmas = <&main_bcdma 0 0x4700 0>;
998 dma-names = "rx0";
999 reg = <0x00 0x30102000 0x00 0x1000>;
1000 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1001 #address-cells = <2>;
1002 #size-cells = <2>;
1003 ranges;
1004 status = "disabled";
1005
1006 cdns_csi2rx0: csi-bridge@30101000 {
1007 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1008 reg = <0x00 0x30101000 0x00 0x1000>;
1009 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1010 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1011 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1012 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
1013 phys = <&dphy0>;
1014 phy-names = "dphy";
1015
1016 ports {
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1019
1020 csi0_port0: port@0 {
1021 reg = <0>;
1022 status = "disabled";
1023 };
1024
1025 csi0_port1: port@1 {
1026 reg = <1>;
1027 status = "disabled";
1028 };
1029
1030 csi0_port2: port@2 {
1031 reg = <2>;
1032 status = "disabled";
1033 };
1034
1035 csi0_port3: port@3 {
1036 reg = <3>;
1037 status = "disabled";
1038 };
1039
1040 csi0_port4: port@4 {
1041 reg = <4>;
1042 status = "disabled";
1043 };
1044 };
1045 };
1046 };
1047
1048 dphy0: phy@30110000 {
1049 compatible = "cdns,dphy-rx";
1050 reg = <0x00 0x30110000 0x00 0x1100>;
1051 #phy-cells = <0>;
1052 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1053 status = "disabled";
1054 };
1055
1056 gpmc0: memory-controller@3b000000 {
1057 compatible = "ti,am64-gpmc";
1058 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
1059 clocks = <&k3_clks 80 0>;
1060 clock-names = "fck";
1061 reg = <0x00 0x03b000000 0x00 0x400>,
1062 <0x00 0x050000000 0x00 0x8000000>;
1063 reg-names = "cfg", "data";
1064 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1065 gpmc,num-cs = <3>;
1066 gpmc,num-waitpins = <2>;
1067 #address-cells = <2>;
1068 #size-cells = <1>;
1069 interrupt-controller;
1070 #interrupt-cells = <2>;
1071 gpio-controller;
1072 #gpio-cells = <2>;
1073 status = "disabled";
1074 };
1075
1076 elm0: ecc@25010000 {
1077 compatible = "ti,am64-elm";
1078 reg = <0x00 0x25010000 0x00 0x2000>;
1079 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1080 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1081 clocks = <&k3_clks 54 0>;
1082 clock-names = "fck";
1083 status = "disabled";
1084 };
1085 };
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