1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree Source for AM62A SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8 &cbass_main {
9 oc_sram: sram@70000000 {
10 compatible = "mmio-sram";
11 reg = <0x00 0x70000000 0x00 0x10000>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
15 };
16
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
22 <0x01 0x00000000 0x00 0x2000>, /* GICC */
23 <0x01 0x00010000 0x00 0x1000>, /* GICH */
24 <0x01 0x00020000 0x00 0x2000>; /* GICV */
25 #address-cells = <2>;
26 #size-cells = <2>;
27 ranges;
28 #interrupt-cells = <3>;
29 interrupt-controller;
30 /*
31 * vcpumntirq:
32 * virtual CPU interface maintenance interrupt
33 */
34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
35
36 gic_its: msi-controller@1820000 {
37 compatible = "arm,gic-v3-its";
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
40 msi-controller;
41 #msi-cells = <1>;
42 };
43 };
44
45 main_conf: bus@100000 {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges = <0x00 0x00 0x00100000 0x20000>;
50
51 phy_gmii_sel: phy@4044 {
52 compatible = "ti,am654-phy-gmii-sel";
53 reg = <0x4044 0x8>;
54 #phy-cells = <1>;
55 };
56
57 epwm_tbclk: clock-controller@4130 {
58 compatible = "ti,am62-epwm-tbclk";
59 reg = <0x4130 0x4>;
60 #clock-cells = <1>;
61 };
62
63 audio_refclk0: clock-controller@82e0 {
64 compatible = "ti,am62-audio-refclk";
65 reg = <0x82e0 0x4>;
66 clocks = <&k3_clks 157 0>;
67 assigned-clocks = <&k3_clks 157 0>;
68 assigned-clock-parents = <&k3_clks 157 8>;
69 #clock-cells = <0>;
70 };
71
72 audio_refclk1: clock-controller@82e4 {
73 compatible = "ti,am62-audio-refclk";
74 reg = <0x82e4 0x4>;
75 clocks = <&k3_clks 157 10>;
76 assigned-clocks = <&k3_clks 157 10>;
77 assigned-clock-parents = <&k3_clks 157 18>;
78 #clock-cells = <0>;
79 };
80 };
81
82 dmss: bus@48000000 {
83 compatible = "simple-bus";
84 #address-cells = <2>;
85 #size-cells = <2>;
86 dma-ranges;
87 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
88
89 ti,sci-dev-id = <25>;
90
91 secure_proxy_main: mailbox@4d000000 {
92 compatible = "ti,am654-secure-proxy";
93 reg = <0x00 0x4d000000 0x00 0x80000>,
94 <0x00 0x4a600000 0x00 0x80000>,
95 <0x00 0x4a400000 0x00 0x80000>;
96 reg-names = "target_data", "rt", "scfg";
97 #mbox-cells = <1>;
98 interrupt-names = "rx_012";
99 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
100 };
101
102 inta_main_dmss: interrupt-controller@48000000 {
103 compatible = "ti,sci-inta";
104 reg = <0x00 0x48000000 0x00 0x100000>;
105 #interrupt-cells = <0>;
106 interrupt-controller;
107 interrupt-parent = <&gic500>;
108 msi-controller;
109 ti,sci = <&dmsc>;
110 ti,sci-dev-id = <28>;
111 ti,interrupt-ranges = <6 70 34>;
112 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
113 };
114
115 main_bcdma: dma-controller@485c0100 {
116 compatible = "ti,am64-dmss-bcdma";
117 reg = <0x00 0x485c0100 0x00 0x100>,
118 <0x00 0x4c000000 0x00 0x20000>,
119 <0x00 0x4a820000 0x00 0x20000>,
120 <0x00 0x4aa40000 0x00 0x20000>,
121 <0x00 0x4bc00000 0x00 0x100000>,
122 <0x00 0x48600000 0x00 0x8000>,
123 <0x00 0x484a4000 0x00 0x2000>,
124 <0x00 0x484c2000 0x00 0x2000>,
125 <0x00 0x48420000 0x00 0x2000>;
126 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
127 "ring", "tchan", "rchan", "bchan";
128 msi-parent = <&inta_main_dmss>;
129 #dma-cells = <3>;
130 ti,sci = <&dmsc>;
131 ti,sci-dev-id = <26>;
132 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
133 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
134 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
135 };
136
137 main_pktdma: dma-controller@485c0000 {
138 compatible = "ti,am64-dmss-pktdma";
139 reg = <0x00 0x485c0000 0x00 0x100>,
140 <0x00 0x4a800000 0x00 0x20000>,
141 <0x00 0x4aa00000 0x00 0x20000>,
142 <0x00 0x4b800000 0x00 0x200000>,
143 <0x00 0x485e0000 0x00 0x10000>,
144 <0x00 0x484a0000 0x00 0x2000>,
145 <0x00 0x484c0000 0x00 0x2000>,
146 <0x00 0x48430000 0x00 0x1000>;
147 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
148 "ring", "tchan", "rchan", "rflow";
149 msi-parent = <&inta_main_dmss>;
150 #dma-cells = <2>;
151 ti,sci = <&dmsc>;
152 ti,sci-dev-id = <30>;
153 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
154 <0x24>, /* CPSW_TX_CHAN */
155 <0x25>, /* SAUL_TX_0_CHAN */
156 <0x26>; /* SAUL_TX_1_CHAN */
157 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
158 <0x11>, /* RING_CPSW_TX_CHAN */
159 <0x12>, /* RING_SAUL_TX_0_CHAN */
160 <0x13>; /* RING_SAUL_TX_1_CHAN */
161 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
162 <0x2b>, /* CPSW_RX_CHAN */
163 <0x2d>, /* SAUL_RX_0_CHAN */
164 <0x2f>, /* SAUL_RX_1_CHAN */
165 <0x31>, /* SAUL_RX_2_CHAN */
166 <0x33>; /* SAUL_RX_3_CHAN */
167 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
168 <0x2c>, /* FLOW_CPSW_RX_CHAN */
169 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
170 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
171 };
172 };
173
174 dmss_csi: bus@4e000000 {
175 compatible = "simple-bus";
176 #address-cells = <2>;
177 #size-cells = <2>;
178 dma-ranges;
179 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>;
180
181 ti,sci-dev-id = <198>;
182
183 inta_main_dmss_csi: interrupt-controller@4e0a0000 {
184 compatible = "ti,sci-inta";
185 reg = <0x00 0x4e0a0000 0x00 0x8000>;
186 #interrupt-cells = <0>;
187 interrupt-controller;
188 interrupt-parent = <&gic500>;
189 msi-controller;
190 ti,sci = <&dmsc>;
191 ti,sci-dev-id = <200>;
192 ti,interrupt-ranges = <0 237 8>;
193 ti,unmapped-event-sources = <&main_bcdma_csi>;
194 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
195 };
196
197 main_bcdma_csi: dma-controller@4e230000 {
198 compatible = "ti,am62a-dmss-bcdma-csirx";
199 reg = <0x00 0x4e230000 0x00 0x100>,
200 <0x00 0x4e180000 0x00 0x8000>,
201 <0x00 0x4e100000 0x00 0x10000>;
202 reg-names = "gcfg", "rchanrt", "ringrt";
203 msi-parent = <&inta_main_dmss_csi>;
204 #dma-cells = <3>;
205 ti,sci = <&dmsc>;
206 ti,sci-dev-id = <199>;
207 ti,sci-rm-range-rchan = <0x21>;
208 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
209 };
210 };
211
212 dmsc: system-controller@44043000 {
213 compatible = "ti,k2g-sci";
214 reg = <0x00 0x44043000 0x00 0xfe0>;
215 reg-names = "debug_messages";
216 ti,host-id = <12>;
217 mbox-names = "rx", "tx";
218 mboxes = <&secure_proxy_main 12>,
219 <&secure_proxy_main 13>;
220
221 k3_pds: power-controller {
222 compatible = "ti,sci-pm-domain";
223 #power-domain-cells = <2>;
224 };
225
226 k3_clks: clock-controller {
227 compatible = "ti,k2g-sci-clk";
228 #clock-cells = <2>;
229 };
230
231 k3_reset: reset-controller {
232 compatible = "ti,sci-reset";
233 #reset-cells = <2>;
234 };
235 };
236
237 crypto: crypto@40900000 {
238 compatible = "ti,am62-sa3ul";
239 reg = <0x00 0x40900000 0x00 0x1200>;
240 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
241 <&main_pktdma 0x7507 0>;
242 dma-names = "tx", "rx1", "rx2";
243 };
244
245 secure_proxy_sa3: mailbox@43600000 {
246 compatible = "ti,am654-secure-proxy";
247 #mbox-cells = <1>;
248 reg-names = "target_data", "rt", "scfg";
249 reg = <0x00 0x43600000 0x00 0x10000>,
250 <0x00 0x44880000 0x00 0x20000>,
251 <0x00 0x44860000 0x00 0x20000>;
252 /*
253 * Marked Disabled:
254 * Node is incomplete as it is meant for bootloaders and
255 * firmware on non-MPU processors
256 */
257 status = "disabled";
258 };
259
260 main_pmx0: pinctrl@f4000 {
261 compatible = "pinctrl-single";
262 reg = <0x00 0xf4000 0x00 0x2ac>;
263 #pinctrl-cells = <1>;
264 pinctrl-single,register-width = <32>;
265 pinctrl-single,function-mask = <0xffffffff>;
266 };
267
268 main_esm: esm@420000 {
269 compatible = "ti,j721e-esm";
270 reg = <0x0 0x420000 0x0 0x1000>;
271 bootph-pre-ram;
272 /* Interrupt sources: rti0, rti1, wrti0, rti4, rti2, rti3 */
273 ti,esm-pins = <192>, <193>, <195>, <204>, <209>, <210>;
274 };
275
276 main_timer0: timer@2400000 {
277 compatible = "ti,am654-timer";
278 reg = <0x00 0x2400000 0x00 0x400>;
279 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&k3_clks 36 2>;
281 clock-names = "fck";
282 assigned-clocks = <&k3_clks 36 2>;
283 assigned-clock-parents = <&k3_clks 36 3>;
284 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
285 ti,timer-pwm;
286 };
287
288 main_timer1: timer@2410000 {
289 compatible = "ti,am654-timer";
290 reg = <0x00 0x2410000 0x00 0x400>;
291 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&k3_clks 37 2>;
293 clock-names = "fck";
294 assigned-clocks = <&k3_clks 37 2>;
295 assigned-clock-parents = <&k3_clks 37 3>;
296 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
297 ti,timer-pwm;
298 };
299
300 main_timer2: timer@2420000 {
301 compatible = "ti,am654-timer";
302 reg = <0x00 0x2420000 0x00 0x400>;
303 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&k3_clks 38 2>;
305 clock-names = "fck";
306 assigned-clocks = <&k3_clks 38 2>;
307 assigned-clock-parents = <&k3_clks 38 3>;
308 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
309 ti,timer-pwm;
310 };
311
312 main_timer3: timer@2430000 {
313 compatible = "ti,am654-timer";
314 reg = <0x00 0x2430000 0x00 0x400>;
315 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&k3_clks 39 2>;
317 clock-names = "fck";
318 assigned-clocks = <&k3_clks 39 2>;
319 assigned-clock-parents = <&k3_clks 39 3>;
320 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
321 ti,timer-pwm;
322 };
323
324 main_timer4: timer@2440000 {
325 compatible = "ti,am654-timer";
326 reg = <0x00 0x2440000 0x00 0x400>;
327 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&k3_clks 40 2>;
329 clock-names = "fck";
330 assigned-clocks = <&k3_clks 40 2>;
331 assigned-clock-parents = <&k3_clks 40 3>;
332 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
333 ti,timer-pwm;
334 };
335
336 main_timer5: timer@2450000 {
337 compatible = "ti,am654-timer";
338 reg = <0x00 0x2450000 0x00 0x400>;
339 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&k3_clks 41 2>;
341 clock-names = "fck";
342 assigned-clocks = <&k3_clks 41 2>;
343 assigned-clock-parents = <&k3_clks 41 3>;
344 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
345 ti,timer-pwm;
346 };
347
348 main_timer6: timer@2460000 {
349 compatible = "ti,am654-timer";
350 reg = <0x00 0x2460000 0x00 0x400>;
351 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&k3_clks 42 2>;
353 clock-names = "fck";
354 assigned-clocks = <&k3_clks 42 2>;
355 assigned-clock-parents = <&k3_clks 42 3>;
356 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
357 ti,timer-pwm;
358 };
359
360 main_timer7: timer@2470000 {
361 compatible = "ti,am654-timer";
362 reg = <0x00 0x2470000 0x00 0x400>;
363 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&k3_clks 43 2>;
365 clock-names = "fck";
366 assigned-clocks = <&k3_clks 43 2>;
367 assigned-clock-parents = <&k3_clks 43 3>;
368 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
369 ti,timer-pwm;
370 };
371
372 main_uart0: serial@2800000 {
373 compatible = "ti,am64-uart", "ti,am654-uart";
374 reg = <0x00 0x02800000 0x00 0x100>;
375 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
376 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
377 clocks = <&k3_clks 146 0>;
378 clock-names = "fclk";
379 status = "disabled";
380 };
381
382 main_uart1: serial@2810000 {
383 compatible = "ti,am64-uart", "ti,am654-uart";
384 reg = <0x00 0x02810000 0x00 0x100>;
385 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
386 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
387 clocks = <&k3_clks 152 0>;
388 clock-names = "fclk";
389 status = "disabled";
390 };
391
392 main_uart2: serial@2820000 {
393 compatible = "ti,am64-uart", "ti,am654-uart";
394 reg = <0x00 0x02820000 0x00 0x100>;
395 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
396 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
397 clocks = <&k3_clks 153 0>;
398 clock-names = "fclk";
399 status = "disabled";
400 };
401
402 main_uart3: serial@2830000 {
403 compatible = "ti,am64-uart", "ti,am654-uart";
404 reg = <0x00 0x02830000 0x00 0x100>;
405 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
406 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
407 clocks = <&k3_clks 154 0>;
408 clock-names = "fclk";
409 status = "disabled";
410 };
411
412 main_uart4: serial@2840000 {
413 compatible = "ti,am64-uart", "ti,am654-uart";
414 reg = <0x00 0x02840000 0x00 0x100>;
415 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
416 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
417 clocks = <&k3_clks 155 0>;
418 clock-names = "fclk";
419 status = "disabled";
420 };
421
422 main_uart5: serial@2850000 {
423 compatible = "ti,am64-uart", "ti,am654-uart";
424 reg = <0x00 0x02850000 0x00 0x100>;
425 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
426 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
427 clocks = <&k3_clks 156 0>;
428 clock-names = "fclk";
429 status = "disabled";
430 };
431
432 main_uart6: serial@2860000 {
433 compatible = "ti,am64-uart", "ti,am654-uart";
434 reg = <0x00 0x02860000 0x00 0x100>;
435 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
436 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
437 clocks = <&k3_clks 158 0>;
438 clock-names = "fclk";
439 status = "disabled";
440 };
441
442 main_i2c0: i2c@20000000 {
443 compatible = "ti,am64-i2c", "ti,omap4-i2c";
444 reg = <0x00 0x20000000 0x00 0x100>;
445 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
446 #address-cells = <1>;
447 #size-cells = <0>;
448 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
449 clocks = <&k3_clks 102 2>;
450 clock-names = "fck";
451 status = "disabled";
452 };
453
454 main_i2c1: i2c@20010000 {
455 compatible = "ti,am64-i2c", "ti,omap4-i2c";
456 reg = <0x00 0x20010000 0x00 0x100>;
457 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
458 #address-cells = <1>;
459 #size-cells = <0>;
460 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
461 clocks = <&k3_clks 103 2>;
462 clock-names = "fck";
463 status = "disabled";
464 };
465
466 main_i2c2: i2c@20020000 {
467 compatible = "ti,am64-i2c", "ti,omap4-i2c";
468 reg = <0x00 0x20020000 0x00 0x100>;
469 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
470 #address-cells = <1>;
471 #size-cells = <0>;
472 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
473 clocks = <&k3_clks 104 2>;
474 clock-names = "fck";
475 status = "disabled";
476 };
477
478 main_i2c3: i2c@20030000 {
479 compatible = "ti,am64-i2c", "ti,omap4-i2c";
480 reg = <0x00 0x20030000 0x00 0x100>;
481 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
482 #address-cells = <1>;
483 #size-cells = <0>;
484 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
485 clocks = <&k3_clks 105 2>;
486 clock-names = "fck";
487 status = "disabled";
488 };
489
490 main_spi0: spi@20100000 {
491 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
492 reg = <0x00 0x20100000 0x00 0x400>;
493 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
494 #address-cells = <1>;
495 #size-cells = <0>;
496 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
497 clocks = <&k3_clks 141 0>;
498 status = "disabled";
499 };
500
501 main_spi1: spi@20110000 {
502 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
503 reg = <0x00 0x20110000 0x00 0x400>;
504 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
508 clocks = <&k3_clks 142 0>;
509 status = "disabled";
510 };
511
512 main_spi2: spi@20120000 {
513 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
514 reg = <0x00 0x20120000 0x00 0x400>;
515 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
516 #address-cells = <1>;
517 #size-cells = <0>;
518 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
519 clocks = <&k3_clks 143 0>;
520 status = "disabled";
521 };
522
523 main_gpio_intr: interrupt-controller@a00000 {
524 compatible = "ti,sci-intr";
525 reg = <0x00 0x00a00000 0x00 0x800>;
526 ti,intr-trigger-type = <1>;
527 interrupt-controller;
528 interrupt-parent = <&gic500>;
529 #interrupt-cells = <1>;
530 ti,sci = <&dmsc>;
531 ti,sci-dev-id = <3>;
532 ti,interrupt-ranges = <0 32 16>;
533 status = "disabled";
534 };
535
536 main_gpio0: gpio@600000 {
537 compatible = "ti,am64-gpio", "ti,keystone-gpio";
538 reg = <0x00 0x00600000 0x0 0x100>;
539 gpio-controller;
540 #gpio-cells = <2>;
541 interrupt-parent = <&main_gpio_intr>;
542 interrupts = <190>, <191>, <192>,
543 <193>, <194>, <195>;
544 interrupt-controller;
545 #interrupt-cells = <2>;
546 ti,ngpio = <92>;
547 ti,davinci-gpio-unbanked = <0>;
548 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
549 clocks = <&k3_clks 77 0>;
550 clock-names = "gpio";
551 status = "disabled";
552 };
553
554 main_gpio1: gpio@601000 {
555 compatible = "ti,am64-gpio", "ti,keystone-gpio";
556 reg = <0x00 0x00601000 0x0 0x100>;
557 gpio-controller;
558 #gpio-cells = <2>;
559 interrupt-parent = <&main_gpio_intr>;
560 interrupts = <180>, <181>, <182>,
561 <183>, <184>, <185>;
562 interrupt-controller;
563 #interrupt-cells = <2>;
564 ti,ngpio = <52>;
565 ti,davinci-gpio-unbanked = <0>;
566 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
567 clocks = <&k3_clks 78 0>;
568 clock-names = "gpio";
569 status = "disabled";
570 };
571
572 sdhci0: mmc@fa10000 {
573 compatible = "ti,am62-sdhci";
574 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
575 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
576 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
577 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
578 clock-names = "clk_ahb", "clk_xin";
579 assigned-clocks = <&k3_clks 57 6>;
580 assigned-clock-parents = <&k3_clks 57 8>;
581 bus-width = <8>;
582 mmc-hs200-1_8v;
583 ti,clkbuf-sel = <0x7>;
584 ti,otap-del-sel-legacy = <0x0>;
585 ti,otap-del-sel-mmc-hs = <0x0>;
586 ti,otap-del-sel-hs200 = <0x6>;
587 status = "disabled";
588 };
589
590 sdhci1: mmc@fa00000 {
591 compatible = "ti,am62-sdhci";
592 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
593 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
594 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
595 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
596 clock-names = "clk_ahb", "clk_xin";
597 bus-width = <4>;
598 ti,clkbuf-sel = <0x7>;
599 ti,otap-del-sel-legacy = <0x0>;
600 ti,otap-del-sel-sd-hs = <0x0>;
601 ti,otap-del-sel-sdr12 = <0xf>;
602 ti,otap-del-sel-sdr25 = <0xf>;
603 ti,otap-del-sel-sdr50 = <0xc>;
604 ti,otap-del-sel-sdr104 = <0x6>;
605 ti,otap-del-sel-ddr50 = <0x9>;
606 ti,itap-del-sel-legacy = <0x0>;
607 ti,itap-del-sel-sd-hs = <0x0>;
608 ti,itap-del-sel-sdr12 = <0x0>;
609 ti,itap-del-sel-sdr25 = <0x0>;
610 status = "disabled";
611 };
612
613 sdhci2: mmc@fa20000 {
614 compatible = "ti,am62-sdhci";
615 reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>;
616 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
617 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
618 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
619 clock-names = "clk_ahb", "clk_xin";
620 bus-width = <4>;
621 ti,clkbuf-sel = <0x7>;
622 ti,otap-del-sel-legacy = <0x0>;
623 ti,otap-del-sel-sd-hs = <0x0>;
624 ti,otap-del-sel-sdr12 = <0xf>;
625 ti,otap-del-sel-sdr25 = <0xf>;
626 ti,otap-del-sel-sdr50 = <0xc>;
627 ti,otap-del-sel-sdr104 = <0x6>;
628 ti,otap-del-sel-ddr50 = <0x9>;
629 ti,itap-del-sel-legacy = <0x0>;
630 ti,itap-del-sel-sd-hs = <0x0>;
631 ti,itap-del-sel-sdr12 = <0x0>;
632 ti,itap-del-sel-sdr25 = <0x0>;
633 status = "disabled";
634 };
635
636 usbss0: dwc3-usb@f900000 {
637 compatible = "ti,am62-usb";
638 reg = <0x00 0x0f900000 0x00 0x800>,
639 <0x00 0x0f908000 0x00 0x400>;
640 clocks = <&k3_clks 161 3>;
641 clock-names = "ref";
642 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
643 #address-cells = <2>;
644 #size-cells = <2>;
645 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
646 ranges;
647 status = "disabled";
648
649 usb0: usb@31000000 {
650 compatible = "snps,dwc3";
651 reg = <0x00 0x31000000 0x00 0x50000>;
652 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
653 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
654 interrupt-names = "host", "peripheral";
655 maximum-speed = "high-speed";
656 dr_mode = "otg";
657 snps,usb2-gadget-lpm-disable;
658 snps,usb2-lpm-disable;
659 };
660 };
661
662 usbss1: dwc3-usb@f910000 {
663 compatible = "ti,am62-usb";
664 reg = <0x00 0x0f910000 0x00 0x800>,
665 <0x00 0x0f918000 0x00 0x400>;
666 clocks = <&k3_clks 162 3>;
667 clock-names = "ref";
668 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
669 #address-cells = <2>;
670 #size-cells = <2>;
671 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
672 ranges;
673 status = "disabled";
674
675 usb1: usb@31100000 {
676 compatible = "snps,dwc3";
677 reg = <0x00 0x31100000 0x00 0x50000>;
678 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
679 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
680 interrupt-names = "host", "peripheral";
681 maximum-speed = "high-speed";
682 dr_mode = "otg";
683 snps,usb2-gadget-lpm-disable;
684 snps,usb2-lpm-disable;
685 };
686 };
687
688 fss: bus@fc00000 {
689 compatible = "simple-bus";
690 reg = <0x00 0x0fc00000 0x00 0x70000>;
691 #address-cells = <2>;
692 #size-cells = <2>;
693 ranges;
694 status = "disabled";
695
696 ospi0: spi@fc40000 {
697 compatible = "ti,am654-ospi", "cdns,qspi-nor";
698 reg = <0x00 0x0fc40000 0x00 0x100>,
699 <0x05 0x00000000 0x01 0x00000000>;
700 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
701 cdns,fifo-depth = <256>;
702 cdns,fifo-width = <4>;
703 cdns,trigger-address = <0x0>;
704 clocks = <&k3_clks 75 7>;
705 assigned-clocks = <&k3_clks 75 7>;
706 assigned-clock-parents = <&k3_clks 75 8>;
707 assigned-clock-rates = <166666666>;
708 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
709 #address-cells = <1>;
710 #size-cells = <0>;
711 };
712 };
713
714 cpsw3g: ethernet@8000000 {
715 compatible = "ti,am642-cpsw-nuss";
716 #address-cells = <2>;
717 #size-cells = <2>;
718 reg = <0x0 0x8000000 0x0 0x200000>;
719 reg-names = "cpsw_nuss";
720 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
721 clocks = <&k3_clks 13 0>;
722 assigned-clocks = <&k3_clks 13 3>;
723 assigned-clock-parents = <&k3_clks 13 11>;
724 clock-names = "fck";
725 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
726 status = "disabled";
727
728 dmas = <&main_pktdma 0xc600 15>,
729 <&main_pktdma 0xc601 15>,
730 <&main_pktdma 0xc602 15>,
731 <&main_pktdma 0xc603 15>,
732 <&main_pktdma 0xc604 15>,
733 <&main_pktdma 0xc605 15>,
734 <&main_pktdma 0xc606 15>,
735 <&main_pktdma 0xc607 15>,
736 <&main_pktdma 0x4600 15>;
737 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
738 "tx7", "rx";
739
740 ethernet-ports {
741 #address-cells = <1>;
742 #size-cells = <0>;
743
744 cpsw_port1: port@1 {
745 reg = <1>;
746 ti,mac-only;
747 label = "port1";
748 phys = <&phy_gmii_sel 1>;
749 mac-address = [00 00 00 00 00 00];
750 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
751 };
752
753 cpsw_port2: port@2 {
754 reg = <2>;
755 ti,mac-only;
756 label = "port2";
757 phys = <&phy_gmii_sel 2>;
758 mac-address = [00 00 00 00 00 00];
759 };
760 };
761
762 cpsw3g_mdio: mdio@f00 {
763 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
764 reg = <0x0 0xf00 0x0 0x100>;
765 #address-cells = <1>;
766 #size-cells = <0>;
767 clocks = <&k3_clks 13 0>;
768 clock-names = "fck";
769 bus_freq = <1000000>;
770 };
771
772 cpts@3d000 {
773 compatible = "ti,j721e-cpts";
774 reg = <0x0 0x3d000 0x0 0x400>;
775 clocks = <&k3_clks 13 3>;
776 clock-names = "cpts";
777 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
778 interrupt-names = "cpts";
779 ti,cpts-ext-ts-inputs = <4>;
780 ti,cpts-periodic-outputs = <2>;
781 };
782 };
783
784 hwspinlock: spinlock@2a000000 {
785 compatible = "ti,am64-hwspinlock";
786 reg = <0x00 0x2a000000 0x00 0x1000>;
787 #hwlock-cells = <1>;
788 };
789
790 mailbox0_cluster0: mailbox@29000000 {
791 compatible = "ti,am64-mailbox";
792 reg = <0x00 0x29000000 0x00 0x200>;
793 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
794 #mbox-cells = <1>;
795 ti,mbox-num-users = <4>;
796 ti,mbox-num-fifos = <16>;
797 };
798
799 mailbox0_cluster1: mailbox@29010000 {
800 compatible = "ti,am64-mailbox";
801 reg = <0x00 0x29010000 0x00 0x200>;
802 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
803 #mbox-cells = <1>;
804 ti,mbox-num-users = <4>;
805 ti,mbox-num-fifos = <16>;
806 };
807
808 mailbox0_cluster2: mailbox@29020000 {
809 compatible = "ti,am64-mailbox";
810 reg = <0x00 0x29020000 0x00 0x200>;
811 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
812 #mbox-cells = <1>;
813 ti,mbox-num-users = <4>;
814 ti,mbox-num-fifos = <16>;
815 };
816
817 mailbox0_cluster3: mailbox@29030000 {
818 compatible = "ti,am64-mailbox";
819 reg = <0x00 0x29030000 0x00 0x200>;
820 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
821 #mbox-cells = <1>;
822 ti,mbox-num-users = <4>;
823 ti,mbox-num-fifos = <16>;
824 };
825
826 main_mcan0: can@20701000 {
827 compatible = "bosch,m_can";
828 reg = <0x00 0x20701000 0x00 0x200>,
829 <0x00 0x20708000 0x00 0x8000>;
830 reg-names = "m_can", "message_ram";
831 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
832 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
833 clock-names = "hclk", "cclk";
834 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "int0", "int1";
837 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
838 status = "disabled";
839 };
840
841 main_rti0: watchdog@e000000 {
842 compatible = "ti,j7-rti-wdt";
843 reg = <0x00 0x0e000000 0x00 0x100>;
844 clocks = <&k3_clks 125 0>;
845 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
846 assigned-clocks = <&k3_clks 125 0>;
847 assigned-clock-parents = <&k3_clks 125 2>;
848 };
849
850 main_rti1: watchdog@e010000 {
851 compatible = "ti,j7-rti-wdt";
852 reg = <0x00 0x0e010000 0x00 0x100>;
853 clocks = <&k3_clks 126 0>;
854 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
855 assigned-clocks = <&k3_clks 126 0>;
856 assigned-clock-parents = <&k3_clks 126 2>;
857 };
858
859 main_rti2: watchdog@e020000 {
860 compatible = "ti,j7-rti-wdt";
861 reg = <0x00 0x0e020000 0x00 0x100>;
862 clocks = <&k3_clks 127 0>;
863 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
864 assigned-clocks = <&k3_clks 127 0>;
865 assigned-clock-parents = <&k3_clks 127 2>;
866 };
867
868 main_rti3: watchdog@e030000 {
869 compatible = "ti,j7-rti-wdt";
870 reg = <0x00 0x0e030000 0x00 0x100>;
871 clocks = <&k3_clks 128 0>;
872 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
873 assigned-clocks = <&k3_clks 128 0>;
874 assigned-clock-parents = <&k3_clks 128 2>;
875 };
876
877 main_rti4: watchdog@e040000 {
878 compatible = "ti,j7-rti-wdt";
879 reg = <0x00 0x0e040000 0x00 0x100>;
880 clocks = <&k3_clks 205 0>;
881 power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>;
882 assigned-clocks = <&k3_clks 205 0>;
883 assigned-clock-parents = <&k3_clks 205 2>;
884 };
885
886 epwm0: pwm@23000000 {
887 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
888 #pwm-cells = <3>;
889 reg = <0x00 0x23000000 0x00 0x100>;
890 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
891 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
892 clock-names = "tbclk", "fck";
893 status = "disabled";
894 };
895
896 epwm1: pwm@23010000 {
897 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
898 #pwm-cells = <3>;
899 reg = <0x00 0x23010000 0x00 0x100>;
900 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
901 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
902 clock-names = "tbclk", "fck";
903 status = "disabled";
904 };
905
906 epwm2: pwm@23020000 {
907 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
908 #pwm-cells = <3>;
909 reg = <0x00 0x23020000 0x00 0x100>;
910 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
911 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
912 clock-names = "tbclk", "fck";
913 status = "disabled";
914 };
915
916 ecap0: pwm@23100000 {
917 compatible = "ti,am3352-ecap";
918 #pwm-cells = <3>;
919 reg = <0x00 0x23100000 0x00 0x100>;
920 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
921 clocks = <&k3_clks 51 0>;
922 clock-names = "fck";
923 status = "disabled";
924 };
925
926 ecap1: pwm@23110000 {
927 compatible = "ti,am3352-ecap";
928 #pwm-cells = <3>;
929 reg = <0x00 0x23110000 0x00 0x100>;
930 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
931 clocks = <&k3_clks 52 0>;
932 clock-names = "fck";
933 status = "disabled";
934 };
935
936 ecap2: pwm@23120000 {
937 compatible = "ti,am3352-ecap";
938 #pwm-cells = <3>;
939 reg = <0x00 0x23120000 0x00 0x100>;
940 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
941 clocks = <&k3_clks 53 0>;
942 clock-names = "fck";
943 status = "disabled";
944 };
945
946 mcasp0: audio-controller@2b00000 {
947 compatible = "ti,am33xx-mcasp-audio";
948 reg = <0x00 0x02b00000 0x00 0x2000>,
949 <0x00 0x02b08000 0x00 0x400>;
950 reg-names = "mpu", "dat";
951 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
953 interrupt-names = "tx", "rx";
954
955 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
956 dma-names = "tx", "rx";
957
958 clocks = <&k3_clks 190 0>;
959 clock-names = "fck";
960 assigned-clocks = <&k3_clks 190 0>;
961 assigned-clock-parents = <&k3_clks 190 2>;
962 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
963 status = "disabled";
964 };
965
966 mcasp1: audio-controller@2b10000 {
967 compatible = "ti,am33xx-mcasp-audio";
968 reg = <0x00 0x02b10000 0x00 0x2000>,
969 <0x00 0x02b18000 0x00 0x400>;
970 reg-names = "mpu", "dat";
971 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
973 interrupt-names = "tx", "rx";
974
975 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
976 dma-names = "tx", "rx";
977
978 clocks = <&k3_clks 191 0>;
979 clock-names = "fck";
980 assigned-clocks = <&k3_clks 191 0>;
981 assigned-clock-parents = <&k3_clks 191 2>;
982 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
983 status = "disabled";
984 };
985
986 mcasp2: audio-controller@2b20000 {
987 compatible = "ti,am33xx-mcasp-audio";
988 reg = <0x00 0x02b20000 0x00 0x2000>,
989 <0x00 0x02b28000 0x00 0x400>;
990 reg-names = "mpu", "dat";
991 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
993 interrupt-names = "tx", "rx";
994
995 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
996 dma-names = "tx", "rx";
997
998 clocks = <&k3_clks 192 0>;
999 clock-names = "fck";
1000 assigned-clocks = <&k3_clks 192 0>;
1001 assigned-clock-parents = <&k3_clks 192 2>;
1002 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1003 status = "disabled";
1004 };
1005
1006 ti_csi2rx0: ticsi2rx@30102000 {
1007 compatible = "ti,j721e-csi2rx-shim";
1008 dmas = <&main_bcdma_csi 0 0x5000 0>;
1009 dma-names = "rx0";
1010 reg = <0x00 0x30102000 0x00 0x1000>;
1011 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1012 #address-cells = <2>;
1013 #size-cells = <2>;
1014 ranges;
1015 status = "disabled";
1016
1017 cdns_csi2rx0: csi-bridge@30101000 {
1018 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1019 reg = <0x00 0x30101000 0x00 0x1000>;
1020 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1021 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1022 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1023 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
1024 phys = <&dphy0>;
1025 phy-names = "dphy";
1026
1027 ports {
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1030
1031 csi0_port0: port@0 {
1032 reg = <0>;
1033 status = "disabled";
1034 };
1035
1036 csi0_port1: port@1 {
1037 reg = <1>;
1038 status = "disabled";
1039 };
1040
1041 csi0_port2: port@2 {
1042 reg = <2>;
1043 status = "disabled";
1044 };
1045
1046 csi0_port3: port@3 {
1047 reg = <3>;
1048 status = "disabled";
1049 };
1050
1051 csi0_port4: port@4 {
1052 reg = <4>;
1053 status = "disabled";
1054 };
1055 };
1056 };
1057 };
1058
1059 dphy0: phy@30110000 {
1060 compatible = "cdns,dphy-rx";
1061 reg = <0x00 0x30110000 0x00 0x1100>;
1062 #phy-cells = <0>;
1063 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1064 status = "disabled";
1065 };
1066
1067 dss: dss@30200000 {
1068 compatible = "ti,am62a7-dss";
1069 reg = <0x00 0x30200000 0x00 0x1000>, /* common */
1070 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
1071 <0x00 0x30206000 0x00 0x1000>, /* vid */
1072 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
1073 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
1074 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */
1075 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
1076 <0x00 0x30201000 0x00 0x1000>; /* common1 */
1077 reg-names = "common", "vidl1", "vid",
1078 "ovr1", "ovr2", "vp1", "vp2", "common1";
1079 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
1080 clocks = <&k3_clks 186 6>,
1081 <&k3_clks 186 0>,
1082 <&k3_clks 186 2>;
1083 clock-names = "fck", "vp1", "vp2";
1084 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1085 status = "disabled";
1086
1087 dss_ports: ports {
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1090 };
1091 };
1092
1093 vpu: video-codec@30210000 {
1094 compatible = "ti,j721s2-wave521c", "cnm,wave521c";
1095 reg = <0x00 0x30210000 0x00 0x10000>;
1096 clocks = <&k3_clks 204 2>;
1097 power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
1098 };
1099
1100 e5010: jpeg-encoder@fd20000 {
1101 compatible = "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc";
1102 reg = <0x00 0xfd20000 0x00 0x100>,
1103 <0x00 0xfd20200 0x00 0x200>;
1104 reg-names = "core", "mmu";
1105 clocks = <&k3_clks 201 0>;
1106 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
1107 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1108 };
1109 };
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