1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Copyright (C) 2023 - 2024 PHYTEC America LLC
4 * Author: Garrett Giordano <ggiordano@phytec.com>
5 *
6 * Product homepage:
7 * https://www.phytec.com/product/phycore-am62a
8 */
9
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13
14 / {
15 model = "PHYTEC phyCORE-AM62Ax";
16 compatible = "phytec,am62a-phycore-som", "ti,am62a7";
17
18 aliases {
19 ethernet0 = &cpsw_port1;
20 gpio0 = &main_gpio0;
21 gpio1 = &main_gpio1;
22 i2c0 = &main_i2c0;
23 mmc0 = &sdhci0;
24 rtc0 = &i2c_som_rtc;
25 spi0 = &ospi0;
26 };
27
28 leds {
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&leds_pins_default>;
32
33 led-0 {
34 color = <LED_COLOR_ID_GREEN>;
35 gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>;
36 linux,default-trigger = "heartbeat";
37 function = LED_FUNCTION_HEARTBEAT;
38 };
39 };
40
41 memory@80000000 {
42 device_type = "memory";
43 /* 2G RAM */
44 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
45 };
46
47 reserved-memory {
48 #address-cells = <2>;
49 #size-cells = <2>;
50 ranges;
51
52 /* global cma region */
53 linux,cma {
54 compatible = "shared-dma-pool";
55 reusable;
56 size = <0x00 0x24000000>;
57 alloc-ranges = <0x00 0xc0000000 0x00 0x24000000>;
58 linux,cma-default;
59 };
60
61 secure_tfa_ddr: tfa@9e780000 {
62 reg = <0x00 0x9e780000 0x00 0x80000>;
63 alignment = <0x1000>;
64 no-map;
65 };
66
67 secure_ddr: optee@9e800000 {
68 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
69 alignment = <0x1000>;
70 no-map;
71 };
72
73 wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
74 compatible = "shared-dma-pool";
75 reg = <0x00 0x9c900000 0x00 0x01e00000>;
76 no-map;
77 };
78 };
79
80 vcc_5v0_som: regulator-vcc-5v0-som {
81 compatible = "regulator-fixed";
82 regulator-name = "VCC_5V0_SOM";
83 regulator-min-microvolt = <5000000>;
84 regulator-max-microvolt = <5000000>;
85 regulator-always-on;
86 regulator-boot-on;
87 };
88 };
89
90 &main_pmx0 {
91 leds_pins_default: leds-default-pins {
92 pinctrl-single,pins = <
93 AM62AX_IOPAD(0x034, PIN_OUTPUT, 7) /* (K20) OSPI0_CSN2.GPIO0_13 */
94 >;
95 };
96
97 main_i2c0_pins_default: main-i2c0-default-pins {
98 pinctrl-single,pins = <
99 AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */
100 AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */
101 >;
102 };
103
104 main_mdio1_pins_default: main-mdio1-default-pins {
105 pinctrl-single,pins = <
106 AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
107 AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
108 >;
109 };
110
111 main_mmc0_pins_default: main-mmc0-default-pins {
112 pinctrl-single,pins = <
113 AM62AX_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y6) MMC0_CMD */
114 AM62AX_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB7) MMC0_CLK */
115 AM62AX_IOPAD(0x214, PIN_INPUT_PULLUP, 0) /* (AA6) MMC0_DAT0 */
116 AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AB6) MMC0_DAT1 */
117 AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (Y7) MMC0_DAT2 */
118 AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (AA7) MMC0_DAT3 */
119 AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (Y8) MMC0_DAT4 */
120 AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (W7) MMC0_DAT5 */
121 AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */
122 AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */
123 >;
124 };
125
126 main_rgmii1_pins_default: main-rgmii1-default-pins {
127 pinctrl-single,pins = <
128 AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
129 AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
130 AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
131 AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
132 AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
133 AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
134 AM62AX_IOPAD(0x134, PIN_OUTPUT, 0) /* (Y17) RGMII1_TD0 */
135 AM62AX_IOPAD(0x138, PIN_OUTPUT, 0) /* (V16) RGMII1_TD1 */
136 AM62AX_IOPAD(0x13c, PIN_OUTPUT, 0) /* (Y16) RGMII1_TD2 */
137 AM62AX_IOPAD(0x140, PIN_OUTPUT, 0) /* (AA17) RGMII1_TD3 */
138 AM62AX_IOPAD(0x130, PIN_OUTPUT, 0) /* (AB17) RGMII1_TXC */
139 AM62AX_IOPAD(0x12c, PIN_OUTPUT, 0) /* (W16) RGMII1_TX_CTL */
140 >;
141 };
142
143 ospi0_pins_default: ospi0-default-pins {
144 pinctrl-single,pins = <
145 AM62AX_IOPAD(0x000, PIN_OUTPUT, 0) /* (L22) OSPI0_CLK */
146 AM62AX_IOPAD(0x02c, PIN_OUTPUT, 0) /* (H21) OSPI0_CSn0 */
147 AM62AX_IOPAD(0x038, PIN_OUTPUT, 0) /* (G20) OSPI0_CSn3 */
148 AM62AX_IOPAD(0x00c, PIN_INPUT, 0) /* (J21) OSPI0_D0 */
149 AM62AX_IOPAD(0x010, PIN_INPUT, 0) /* (J18) OSPI0_D1 */
150 AM62AX_IOPAD(0x014, PIN_INPUT, 0) /* (J19) OSPI0_D2 */
151 AM62AX_IOPAD(0x018, PIN_INPUT, 0) /* (H18) OSPI0_D3 */
152 AM62AX_IOPAD(0x01c, PIN_INPUT, 0) /* (K21) OSPI0_D4 */
153 AM62AX_IOPAD(0x020, PIN_INPUT, 0) /* (H19) OSPI0_D5 */
154 AM62AX_IOPAD(0x024, PIN_INPUT, 0) /* (J20) OSPI0_D6 */
155 AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
156 AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */
157 >;
158 };
159
160 pmic_irq_pins_default: pmic-irq-default-pins {
161 pinctrl-single,pins = <
162 AM62AX_IOPAD(0x1f4, PIN_INPUT, 0) /* (D16) EXTINTn */
163 >;
164 };
165 };
166
167 &cpsw3g {
168 status = "okay";
169 pinctrl-names = "default";
170 pinctrl-0 = <&main_rgmii1_pins_default>;
171 };
172
173 &cpsw_port1 {
174 phy-mode = "rgmii-rxid";
175 phy-handle = <&cpsw3g_phy1>;
176 };
177
178 &cpsw3g_mdio {
179 pinctrl-names = "default";
180 pinctrl-0 = <&main_mdio1_pins_default>;
181
182 cpsw3g_phy1: ethernet-phy@1 {
183 compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
184 reg = <1>;
185 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
186 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
187 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
188 };
189 };
190
191 &fss {
192 status = "okay";
193 };
194
195 &main_i2c0 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&main_i2c0_pins_default>;
198 clock-frequency = <400000>;
199 status = "okay";
200
201 pmic@30 {
202 compatible = "ti,tps65219";
203 reg = <0x30>;
204 buck1-supply = <&vcc_5v0_som>;
205 buck2-supply = <&vcc_5v0_som>;
206 buck3-supply = <&vcc_5v0_som>;
207 ldo1-supply = <&vdd_3v3>;
208 ldo2-supply = <&vdd_1v8>;
209 ldo3-supply = <&vcc_5v0_som>;
210 ldo4-supply = <&vcc_5v0_som>;
211
212 pinctrl-names = "default";
213 pinctrl-0 = <&pmic_irq_pins_default>;
214 interrupt-parent = <&gic500>;
215 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
216 interrupt-controller;
217 #interrupt-cells = <1>;
218 ti,power-button;
219 system-power-controller;
220
221 regulators {
222 vdd_3v3: buck1 {
223 regulator-name = "VDD_3V3";
224 regulator-min-microvolt = <3300000>;
225 regulator-max-microvolt = <3300000>;
226 regulator-boot-on;
227 regulator-always-on;
228 };
229
230 vdd_1v8: buck2 {
231 regulator-name = "VDD_1V8";
232 regulator-min-microvolt = <1800000>;
233 regulator-max-microvolt = <1800000>;
234 regulator-boot-on;
235 regulator-always-on;
236 };
237
238 vdd_lpddr4: buck3 {
239 regulator-name = "VDD_LPDDR4";
240 regulator-min-microvolt = <1100000>;
241 regulator-max-microvolt = <1100000>;
242 regulator-boot-on;
243 regulator-always-on;
244 };
245
246 vddshv5_sdio: ldo1 {
247 regulator-name = "VDDSHV5_SDIO";
248 regulator-min-microvolt = <3300000>;
249 regulator-max-microvolt = <3300000>;
250 regulator-allow-bypass;
251 regulator-boot-on;
252 regulator-always-on;
253 };
254
255 vddr_core: ldo2 {
256 regulator-name = "VDDR_CORE";
257 regulator-min-microvolt = <850000>;
258 regulator-max-microvolt = <850000>;
259 regulator-boot-on;
260 regulator-always-on;
261 };
262
263 vdda_1v8: ldo3 {
264 regulator-name = "VDDA_1V8";
265 regulator-min-microvolt = <1800000>;
266 regulator-max-microvolt = <1800000>;
267 regulator-boot-on;
268 regulator-always-on;
269 };
270
271 vdd_2v5: ldo4 {
272 regulator-name = "VDD_2V5";
273 regulator-min-microvolt = <2500000>;
274 regulator-max-microvolt = <2500000>;
275 regulator-boot-on;
276 regulator-always-on;
277 };
278 };
279 };
280
281 eeprom@50 {
282 compatible = "atmel,24c32";
283 pagesize = <32>;
284 reg = <0x50>;
285 };
286
287 i2c_som_rtc: rtc@52 {
288 compatible = "microcrystal,rv3028";
289 reg = <0x52>;
290 };
291 };
292
293 &main_gpio0 {
294 status = "okay";
295 };
296
297 &main_gpio1 {
298 status = "okay";
299 };
300
301 &main_gpio_intr {
302 status = "okay";
303 };
304
305 &ospi0 {
306 pinctrl-names = "default";
307 pinctrl-0 = <&ospi0_pins_default>;
308 status = "okay";
309
310 serial_flash: flash@0 {
311 compatible = "jedec,spi-nor";
312 reg = <0x0>;
313 spi-tx-bus-width = <8>;
314 spi-rx-bus-width = <8>;
315 spi-max-frequency = <25000000>;
316 cdns,tshsl-ns = <60>;
317 cdns,tsd2d-ns = <60>;
318 cdns,tchsh-ns = <60>;
319 cdns,tslch-ns = <60>;
320 cdns,read-delay = <0>;
321 };
322 };
323
324 &sdhci0 {
325 pinctrl-names = "default";
326 pinctrl-0 = <&main_mmc0_pins_default>;
327 disable-wp;
328 non-removable;
329 status = "okay";
330 };
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