1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree file for the MAIN domain peripherals shared by AM62P and J722S
4 *
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8 &cbass_main {
9 oc_sram: sram@70000000 {
10 compatible = "mmio-sram";
11 #address-cells = <1>;
12 #size-cells = <1>;
13 };
14
15 gic500: interrupt-controller@1800000 {
16 compatible = "arm,gic-v3";
17 #address-cells = <2>;
18 #size-cells = <2>;
19 ranges;
20 #interrupt-cells = <3>;
21 interrupt-controller;
22 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
23 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
24 <0x01 0x00000000 0x00 0x2000>, /* GICC */
25 <0x01 0x00010000 0x00 0x1000>, /* GICH */
26 <0x01 0x00020000 0x00 0x2000>; /* GICV */
27 /*
28 * vcpumntirq:
29 * virtual CPU interface maintenance interrupt
30 */
31 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
32
33 gic_its: msi-controller@1820000 {
34 compatible = "arm,gic-v3-its";
35 reg = <0x00 0x01820000 0x00 0x10000>;
36 socionext,synquacer-pre-its = <0x1000000 0x400000>;
37 msi-controller;
38 #msi-cells = <1>;
39 };
40 };
41
42 main_conf: bus@100000 {
43 compatible = "simple-bus";
44 reg = <0x00 0x00100000 0x00 0x20000>;
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges = <0x00 0x00 0x00100000 0x20000>;
48
49 phy_gmii_sel: phy@4044 {
50 compatible = "ti,am654-phy-gmii-sel";
51 reg = <0x4044 0x8>;
52 #phy-cells = <1>;
53 };
54
55 epwm_tbclk: clock-controller@4130 {
56 compatible = "ti,am62-epwm-tbclk";
57 reg = <0x4130 0x4>;
58 #clock-cells = <1>;
59 };
60 };
61
62 dmss: bus@48000000 {
63 compatible = "simple-bus";
64 #address-cells = <2>;
65 #size-cells = <2>;
66 dma-ranges;
67 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
68 bootph-all;
69
70 ti,sci-dev-id = <25>;
71
72 secure_proxy_main: mailbox@4d000000 {
73 compatible = "ti,am654-secure-proxy";
74 #mbox-cells = <1>;
75 reg-names = "target_data", "rt", "scfg";
76 reg = <0x00 0x4d000000 0x00 0x80000>,
77 <0x00 0x4a600000 0x00 0x80000>,
78 <0x00 0x4a400000 0x00 0x80000>;
79 interrupt-names = "rx_012";
80 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
81 bootph-all;
82 };
83
84 inta_main_dmss: interrupt-controller@48000000 {
85 compatible = "ti,sci-inta";
86 reg = <0x00 0x48000000 0x00 0x100000>;
87 #interrupt-cells = <0>;
88 interrupt-controller;
89 interrupt-parent = <&gic500>;
90 msi-controller;
91 ti,sci = <&dmsc>;
92 ti,sci-dev-id = <28>;
93 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
94 };
95
96 main_bcdma: dma-controller@485c0100 {
97 compatible = "ti,am64-dmss-bcdma";
98 reg = <0x00 0x485c0100 0x00 0x100>,
99 <0x00 0x4c000000 0x00 0x20000>,
100 <0x00 0x4a820000 0x00 0x20000>,
101 <0x00 0x4aa40000 0x00 0x20000>,
102 <0x00 0x4bc00000 0x00 0x100000>,
103 <0x00 0x48600000 0x00 0x8000>,
104 <0x00 0x484a4000 0x00 0x2000>,
105 <0x00 0x484c2000 0x00 0x2000>,
106 <0x00 0x48420000 0x00 0x2000>;
107 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
108 "ring", "tchan", "rchan", "bchan";
109 msi-parent = <&inta_main_dmss>;
110 #dma-cells = <3>;
111
112 ti,sci = <&dmsc>;
113 ti,sci-dev-id = <26>;
114 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
115 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
116 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
117 bootph-all;
118 };
119
120 main_pktdma: dma-controller@485c0000 {
121 compatible = "ti,am64-dmss-pktdma";
122 reg = <0x00 0x485c0000 0x00 0x100>,
123 <0x00 0x4a800000 0x00 0x20000>,
124 <0x00 0x4aa00000 0x00 0x20000>,
125 <0x00 0x4b800000 0x00 0x200000>,
126 <0x00 0x485e0000 0x00 0x10000>,
127 <0x00 0x484a0000 0x00 0x2000>,
128 <0x00 0x484c0000 0x00 0x2000>,
129 <0x00 0x48430000 0x00 0x1000>;
130 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
131 "ring", "tchan", "rchan", "rflow";
132 msi-parent = <&inta_main_dmss>;
133 #dma-cells = <2>;
134 bootph-all;
135
136 ti,sci = <&dmsc>;
137 ti,sci-dev-id = <30>;
138 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
139 <0x24>, /* CPSW_TX_CHAN */
140 <0x25>, /* SAUL_TX_0_CHAN */
141 <0x26>; /* SAUL_TX_1_CHAN */
142 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
143 <0x11>, /* RING_CPSW_TX_CHAN */
144 <0x12>, /* RING_SAUL_TX_0_CHAN */
145 <0x13>; /* RING_SAUL_TX_1_CHAN */
146 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
147 <0x2b>, /* CPSW_RX_CHAN */
148 <0x2d>, /* SAUL_RX_0_CHAN */
149 <0x2f>, /* SAUL_RX_1_CHAN */
150 <0x31>, /* SAUL_RX_2_CHAN */
151 <0x33>; /* SAUL_RX_3_CHAN */
152 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
153 <0x2c>, /* FLOW_CPSW_RX_CHAN */
154 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
155 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
156 };
157 };
158
159 dmss_csi: bus@4e000000 {
160 compatible = "simple-bus";
161 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>;
162 #address-cells = <2>;
163 #size-cells = <2>;
164 dma-ranges;
165 ti,sci-dev-id = <198>;
166
167 inta_main_dmss_csi: interrupt-controller@4e400000 {
168 compatible = "ti,sci-inta";
169 reg = <0x00 0x4e400000 0x00 0x8000>;
170 #interrupt-cells = <0>;
171 interrupt-controller;
172 interrupt-parent = <&gic500>;
173 msi-controller;
174 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
175 ti,sci = <&dmsc>;
176 ti,sci-dev-id = <200>;
177 ti,interrupt-ranges = <0 237 8>;
178 ti,unmapped-event-sources = <&main_bcdma_csi>;
179 };
180
181 main_bcdma_csi: dma-controller@4e230000 {
182 compatible = "ti,am62a-dmss-bcdma-csirx";
183 reg = <0x00 0x4e230000 0x00 0x100>,
184 <0x00 0x4e180000 0x00 0x8000>,
185 <0x00 0x4e100000 0x00 0x10000>;
186 reg-names = "gcfg", "rchanrt", "ringrt";
187 #dma-cells = <3>;
188 msi-parent = <&inta_main_dmss_csi>;
189 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
190 ti,sci = <&dmsc>;
191 ti,sci-dev-id = <199>;
192 ti,sci-rm-range-rchan = <0x21>;
193 };
194 };
195
196 dmsc: system-controller@44043000 {
197 compatible = "ti,k2g-sci";
198 ti,host-id = <12>;
199 mbox-names = "rx", "tx";
200 mboxes = <&secure_proxy_main 12>,
201 <&secure_proxy_main 13>;
202 reg-names = "debug_messages";
203 reg = <0x00 0x44043000 0x00 0xfe0>;
204 bootph-all;
205
206 k3_pds: power-controller {
207 compatible = "ti,sci-pm-domain";
208 #power-domain-cells = <2>;
209 bootph-all;
210 };
211
212 k3_clks: clock-controller {
213 compatible = "ti,k2g-sci-clk";
214 #clock-cells = <2>;
215 bootph-all;
216 };
217
218 k3_reset: reset-controller {
219 compatible = "ti,sci-reset";
220 #reset-cells = <2>;
221 bootph-all;
222 };
223 };
224
225 crypto: crypto@40900000 {
226 compatible = "ti,am62-sa3ul";
227 reg = <0x00 0x40900000 0x00 0x1200>;
228 #address-cells = <2>;
229 #size-cells = <2>;
230 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
231 <&main_pktdma 0x7507 0>;
232 dma-names = "tx", "rx1", "rx2";
233 };
234
235 secure_proxy_sa3: mailbox@43600000 {
236 compatible = "ti,am654-secure-proxy";
237 #mbox-cells = <1>;
238 reg-names = "target_data", "rt", "scfg";
239 reg = <0x00 0x43600000 0x00 0x10000>,
240 <0x00 0x44880000 0x00 0x20000>,
241 <0x00 0x44860000 0x00 0x20000>;
242 /*
243 * Marked Disabled:
244 * Node is incomplete as it is meant for bootloaders and
245 * firmware on non-MPU processors
246 */
247 status = "disabled";
248 bootph-all;
249 };
250
251 main_pmx0: pinctrl@f4000 {
252 compatible = "pinctrl-single";
253 reg = <0x00 0xf4000 0x00 0x2ac>;
254 #pinctrl-cells = <1>;
255 pinctrl-single,register-width = <32>;
256 pinctrl-single,function-mask = <0xffffffff>;
257 bootph-all;
258 };
259
260 main_esm: esm@420000 {
261 compatible = "ti,j721e-esm";
262 reg = <0x00 0x420000 0x00 0x1000>;
263 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
264 bootph-pre-ram;
265 };
266
267 main_timer0: timer@2400000 {
268 compatible = "ti,am654-timer";
269 reg = <0x00 0x2400000 0x00 0x400>;
270 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&k3_clks 36 2>;
272 clock-names = "fck";
273 assigned-clocks = <&k3_clks 36 2>;
274 assigned-clock-parents = <&k3_clks 36 3>;
275 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
276 ti,timer-pwm;
277 bootph-all;
278 };
279
280 main_timer1: timer@2410000 {
281 compatible = "ti,am654-timer";
282 reg = <0x00 0x2410000 0x00 0x400>;
283 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&k3_clks 37 2>;
285 clock-names = "fck";
286 assigned-clocks = <&k3_clks 37 2>;
287 assigned-clock-parents = <&k3_clks 37 3>;
288 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
289 ti,timer-pwm;
290 };
291
292 main_timer2: timer@2420000 {
293 compatible = "ti,am654-timer";
294 reg = <0x00 0x2420000 0x00 0x400>;
295 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&k3_clks 38 2>;
297 clock-names = "fck";
298 assigned-clocks = <&k3_clks 38 2>;
299 assigned-clock-parents = <&k3_clks 38 3>;
300 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
301 ti,timer-pwm;
302 };
303
304 main_timer3: timer@2430000 {
305 compatible = "ti,am654-timer";
306 reg = <0x00 0x2430000 0x00 0x400>;
307 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&k3_clks 39 2>;
309 clock-names = "fck";
310 assigned-clocks = <&k3_clks 39 2>;
311 assigned-clock-parents = <&k3_clks 39 3>;
312 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
313 ti,timer-pwm;
314 };
315
316 main_timer4: timer@2440000 {
317 compatible = "ti,am654-timer";
318 reg = <0x00 0x2440000 0x00 0x400>;
319 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&k3_clks 40 2>;
321 clock-names = "fck";
322 assigned-clocks = <&k3_clks 40 2>;
323 assigned-clock-parents = <&k3_clks 40 3>;
324 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
325 ti,timer-pwm;
326 };
327
328 main_timer5: timer@2450000 {
329 compatible = "ti,am654-timer";
330 reg = <0x00 0x2450000 0x00 0x400>;
331 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&k3_clks 41 2>;
333 clock-names = "fck";
334 assigned-clocks = <&k3_clks 41 2>;
335 assigned-clock-parents = <&k3_clks 41 3>;
336 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
337 ti,timer-pwm;
338 };
339
340 main_timer6: timer@2460000 {
341 compatible = "ti,am654-timer";
342 reg = <0x00 0x2460000 0x00 0x400>;
343 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&k3_clks 42 2>;
345 clock-names = "fck";
346 assigned-clocks = <&k3_clks 42 2>;
347 assigned-clock-parents = <&k3_clks 42 3>;
348 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
349 ti,timer-pwm;
350 };
351
352 main_timer7: timer@2470000 {
353 compatible = "ti,am654-timer";
354 reg = <0x00 0x2470000 0x00 0x400>;
355 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&k3_clks 43 2>;
357 clock-names = "fck";
358 assigned-clocks = <&k3_clks 43 2>;
359 assigned-clock-parents = <&k3_clks 43 3>;
360 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
361 ti,timer-pwm;
362 };
363
364 main_uart0: serial@2800000 {
365 compatible = "ti,am64-uart", "ti,am654-uart";
366 reg = <0x00 0x02800000 0x00 0x100>;
367 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
368 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
369 clocks = <&k3_clks 146 0>;
370 clock-names = "fclk";
371 status = "disabled";
372 };
373
374 main_uart1: serial@2810000 {
375 compatible = "ti,am64-uart", "ti,am654-uart";
376 reg = <0x00 0x02810000 0x00 0x100>;
377 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
378 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
379 clocks = <&k3_clks 152 0>;
380 clock-names = "fclk";
381 status = "disabled";
382 };
383
384 main_uart2: serial@2820000 {
385 compatible = "ti,am64-uart", "ti,am654-uart";
386 reg = <0x00 0x02820000 0x00 0x100>;
387 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
388 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
389 clocks = <&k3_clks 153 0>;
390 clock-names = "fclk";
391 status = "disabled";
392 };
393
394 main_uart3: serial@2830000 {
395 compatible = "ti,am64-uart", "ti,am654-uart";
396 reg = <0x00 0x02830000 0x00 0x100>;
397 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
398 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
399 clocks = <&k3_clks 154 0>;
400 clock-names = "fclk";
401 status = "disabled";
402 };
403
404 main_uart4: serial@2840000 {
405 compatible = "ti,am64-uart", "ti,am654-uart";
406 reg = <0x00 0x02840000 0x00 0x100>;
407 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
408 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
409 clocks = <&k3_clks 155 0>;
410 clock-names = "fclk";
411 status = "disabled";
412 };
413
414 main_uart5: serial@2850000 {
415 compatible = "ti,am64-uart", "ti,am654-uart";
416 reg = <0x00 0x02850000 0x00 0x100>;
417 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
418 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
419 clocks = <&k3_clks 156 0>;
420 clock-names = "fclk";
421 status = "disabled";
422 };
423
424 main_uart6: serial@2860000 {
425 compatible = "ti,am64-uart", "ti,am654-uart";
426 reg = <0x00 0x02860000 0x00 0x100>;
427 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
428 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
429 clocks = <&k3_clks 158 0>;
430 clock-names = "fclk";
431 status = "disabled";
432 };
433
434 main_i2c0: i2c@20000000 {
435 compatible = "ti,am64-i2c", "ti,omap4-i2c";
436 reg = <0x00 0x20000000 0x00 0x100>;
437 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
438 #address-cells = <1>;
439 #size-cells = <0>;
440 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
441 clocks = <&k3_clks 102 2>;
442 clock-names = "fck";
443 status = "disabled";
444 };
445
446 main_i2c1: i2c@20010000 {
447 compatible = "ti,am64-i2c", "ti,omap4-i2c";
448 reg = <0x00 0x20010000 0x00 0x100>;
449 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
450 #address-cells = <1>;
451 #size-cells = <0>;
452 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
453 clocks = <&k3_clks 103 2>;
454 clock-names = "fck";
455 status = "disabled";
456 };
457
458 main_i2c2: i2c@20020000 {
459 compatible = "ti,am64-i2c", "ti,omap4-i2c";
460 reg = <0x00 0x20020000 0x00 0x100>;
461 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
462 #address-cells = <1>;
463 #size-cells = <0>;
464 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
465 clocks = <&k3_clks 104 2>;
466 clock-names = "fck";
467 status = "disabled";
468 };
469
470 main_i2c3: i2c@20030000 {
471 compatible = "ti,am64-i2c", "ti,omap4-i2c";
472 reg = <0x00 0x20030000 0x00 0x100>;
473 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
477 clocks = <&k3_clks 105 2>;
478 clock-names = "fck";
479 status = "disabled";
480 };
481
482 main_spi0: spi@20100000 {
483 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
484 reg = <0x00 0x20100000 0x00 0x400>;
485 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
486 #address-cells = <1>;
487 #size-cells = <0>;
488 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
489 clocks = <&k3_clks 141 0>;
490 status = "disabled";
491 };
492
493 main_spi1: spi@20110000 {
494 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
495 reg = <0x00 0x20110000 0x00 0x400>;
496 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
497 #address-cells = <1>;
498 #size-cells = <0>;
499 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
500 clocks = <&k3_clks 142 0>;
501 status = "disabled";
502 };
503
504 main_spi2: spi@20120000 {
505 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
506 reg = <0x00 0x20120000 0x00 0x400>;
507 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
511 clocks = <&k3_clks 143 0>;
512 status = "disabled";
513 };
514
515 main_gpio_intr: interrupt-controller@a00000 {
516 compatible = "ti,sci-intr";
517 reg = <0x00 0x00a00000 0x00 0x800>;
518 ti,intr-trigger-type = <1>;
519 interrupt-controller;
520 interrupt-parent = <&gic500>;
521 #interrupt-cells = <1>;
522 ti,sci = <&dmsc>;
523 ti,sci-dev-id = <3>;
524 ti,interrupt-ranges = <0 32 16>;
525 };
526
527 main_gpio0: gpio@600000 {
528 compatible = "ti,am64-gpio", "ti,keystone-gpio";
529 reg = <0x00 0x00600000 0x00 0x100>;
530 gpio-controller;
531 #gpio-cells = <2>;
532 interrupt-parent = <&main_gpio_intr>;
533 interrupts = <190>, <191>, <192>,
534 <193>, <194>, <195>;
535 interrupt-controller;
536 #interrupt-cells = <2>;
537 ti,davinci-gpio-unbanked = <0>;
538 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
539 clocks = <&k3_clks 77 0>;
540 clock-names = "gpio";
541 };
542
543 main_gpio1: gpio@601000 {
544 compatible = "ti,am64-gpio", "ti,keystone-gpio";
545 reg = <0x00 0x00601000 0x00 0x100>;
546 gpio-controller;
547 #gpio-cells = <2>;
548 interrupt-parent = <&main_gpio_intr>;
549 interrupts = <180>, <181>, <182>,
550 <183>, <184>, <185>;
551 interrupt-controller;
552 #interrupt-cells = <2>;
553 ti,davinci-gpio-unbanked = <0>;
554 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
555 clocks = <&k3_clks 78 0>;
556 clock-names = "gpio";
557 };
558
559 sdhci0: mmc@fa10000 {
560 compatible = "ti,am64-sdhci-8bit";
561 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
562 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
563 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
564 clocks = <&k3_clks 57 1>, <&k3_clks 57 2>;
565 clock-names = "clk_ahb", "clk_xin";
566 assigned-clocks = <&k3_clks 57 2>;
567 assigned-clock-parents = <&k3_clks 57 4>;
568 bus-width = <8>;
569 mmc-ddr-1_8v;
570 mmc-hs200-1_8v;
571 mmc-hs400-1_8v;
572 ti,clkbuf-sel = <0x7>;
573 ti,strobe-sel = <0x77>;
574 ti,trm-icp = <0x8>;
575 ti,otap-del-sel-legacy = <0x1>;
576 ti,otap-del-sel-mmc-hs = <0x1>;
577 ti,otap-del-sel-ddr52 = <0x6>;
578 ti,otap-del-sel-hs200 = <0x8>;
579 ti,otap-del-sel-hs400 = <0x5>;
580 ti,itap-del-sel-legacy = <0x10>;
581 ti,itap-del-sel-mmc-hs = <0xa>;
582 ti,itap-del-sel-ddr52 = <0x3>;
583 status = "disabled";
584 };
585
586 sdhci1: mmc@fa00000 {
587 compatible = "ti,am62-sdhci";
588 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
589 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
590 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
591 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
592 clock-names = "clk_ahb", "clk_xin";
593 bus-width = <4>;
594 ti,clkbuf-sel = <0x7>;
595 ti,otap-del-sel-legacy = <0x0>;
596 ti,otap-del-sel-sd-hs = <0x0>;
597 ti,otap-del-sel-sdr12 = <0xf>;
598 ti,otap-del-sel-sdr25 = <0xf>;
599 ti,otap-del-sel-sdr50 = <0xc>;
600 ti,otap-del-sel-ddr50 = <0x9>;
601 ti,otap-del-sel-sdr104 = <0x6>;
602 ti,itap-del-sel-legacy = <0x0>;
603 ti,itap-del-sel-sd-hs = <0x0>;
604 ti,itap-del-sel-sdr12 = <0x0>;
605 ti,itap-del-sel-sdr25 = <0x0>;
606 status = "disabled";
607 };
608
609 sdhci2: mmc@fa20000 {
610 compatible = "ti,am62-sdhci";
611 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
612 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
613 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
614 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
615 clock-names = "clk_ahb", "clk_xin";
616 bus-width = <4>;
617 ti,clkbuf-sel = <0x7>;
618 ti,otap-del-sel-legacy = <0x0>;
619 ti,otap-del-sel-sd-hs = <0x0>;
620 ti,otap-del-sel-sdr12 = <0xf>;
621 ti,otap-del-sel-sdr25 = <0xf>;
622 ti,otap-del-sel-sdr50 = <0xc>;
623 ti,otap-del-sel-ddr50 = <0x9>;
624 ti,otap-del-sel-sdr104 = <0x6>;
625 ti,itap-del-sel-legacy = <0x0>;
626 ti,itap-del-sel-sd-hs = <0x0>;
627 ti,itap-del-sel-sdr12 = <0x0>;
628 ti,itap-del-sel-sdr25 = <0x0>;
629 status = "disabled";
630 };
631
632 usbss0: usb@f900000 {
633 compatible = "ti,am62-usb";
634 reg = <0x00 0x0f900000 0x00 0x800>,
635 <0x00 0x0f908000 0x00 0x400>;
636 clocks = <&k3_clks 161 3>;
637 clock-names = "ref";
638 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
639 #address-cells = <2>;
640 #size-cells = <2>;
641 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
642 ranges;
643 status = "disabled";
644
645 usb0: usb@31000000 {
646 compatible = "snps,dwc3";
647 reg = <0x00 0x31000000 0x00 0x50000>;
648 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
649 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
650 interrupt-names = "host", "peripheral";
651 maximum-speed = "high-speed";
652 dr_mode = "otg";
653 snps,usb2-gadget-lpm-disable;
654 snps,usb2-lpm-disable;
655 };
656 };
657
658 fss: bus@fc00000 {
659 compatible = "simple-bus";
660 reg = <0x00 0x0fc00000 0x00 0x70000>;
661 #address-cells = <2>;
662 #size-cells = <2>;
663 ranges;
664
665 ospi0: spi@fc40000 {
666 compatible = "ti,am654-ospi", "cdns,qspi-nor";
667 reg = <0x00 0x0fc40000 0x00 0x100>,
668 <0x05 0x00000000 0x01 0x00000000>;
669 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
670 cdns,fifo-depth = <256>;
671 cdns,fifo-width = <4>;
672 cdns,trigger-address = <0x0>;
673 clocks = <&k3_clks 75 7>;
674 assigned-clocks = <&k3_clks 75 7>;
675 assigned-clock-parents = <&k3_clks 75 8>;
676 assigned-clock-rates = <166666666>;
677 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
678 #address-cells = <1>;
679 #size-cells = <0>;
680 status = "disabled";
681 };
682 };
683
684 cpsw3g: ethernet@8000000 {
685 compatible = "ti,am642-cpsw-nuss";
686 #address-cells = <2>;
687 #size-cells = <2>;
688 reg = <0x00 0x08000000 0x00 0x200000>;
689 reg-names = "cpsw_nuss";
690 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
691 clocks = <&k3_clks 13 0>;
692 assigned-clocks = <&k3_clks 13 3>;
693 assigned-clock-parents = <&k3_clks 13 11>;
694 clock-names = "fck";
695 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
696 status = "disabled";
697
698 dmas = <&main_pktdma 0xc600 15>,
699 <&main_pktdma 0xc601 15>,
700 <&main_pktdma 0xc602 15>,
701 <&main_pktdma 0xc603 15>,
702 <&main_pktdma 0xc604 15>,
703 <&main_pktdma 0xc605 15>,
704 <&main_pktdma 0xc606 15>,
705 <&main_pktdma 0xc607 15>,
706 <&main_pktdma 0x4600 15>;
707 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
708 "tx7", "rx";
709
710 ethernet-ports {
711 #address-cells = <1>;
712 #size-cells = <0>;
713
714 cpsw_port1: port@1 {
715 reg = <1>;
716 ti,mac-only;
717 label = "port1";
718 phys = <&phy_gmii_sel 1>;
719 mac-address = [00 00 00 00 00 00];
720 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
721 status = "disabled";
722 };
723
724 cpsw_port2: port@2 {
725 reg = <2>;
726 ti,mac-only;
727 label = "port2";
728 phys = <&phy_gmii_sel 2>;
729 mac-address = [00 00 00 00 00 00];
730 status = "disabled";
731 };
732 };
733
734 cpsw3g_mdio: mdio@f00 {
735 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
736 reg = <0x00 0xf00 0x00 0x100>;
737 #address-cells = <1>;
738 #size-cells = <0>;
739 clocks = <&k3_clks 13 0>;
740 clock-names = "fck";
741 bus_freq = <1000000>;
742 status = "disabled";
743 };
744
745 cpts@3d000 {
746 compatible = "ti,j721e-cpts";
747 reg = <0x00 0x3d000 0x00 0x400>;
748 clocks = <&k3_clks 13 3>;
749 clock-names = "cpts";
750 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
751 interrupt-names = "cpts";
752 ti,cpts-ext-ts-inputs = <4>;
753 ti,cpts-periodic-outputs = <2>;
754 };
755 };
756
757 hwspinlock: spinlock@2a000000 {
758 compatible = "ti,am64-hwspinlock";
759 reg = <0x00 0x2a000000 0x00 0x1000>;
760 #hwlock-cells = <1>;
761 };
762
763 mailbox0_cluster0: mailbox@29000000 {
764 compatible = "ti,am64-mailbox";
765 reg = <0x00 0x29000000 0x00 0x200>;
766 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
767 #mbox-cells = <1>;
768 ti,mbox-num-users = <4>;
769 ti,mbox-num-fifos = <16>;
770 };
771
772 mailbox0_cluster1: mailbox@29010000 {
773 compatible = "ti,am64-mailbox";
774 reg = <0x00 0x29010000 0x00 0x200>;
775 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
776 #mbox-cells = <1>;
777 ti,mbox-num-users = <4>;
778 ti,mbox-num-fifos = <16>;
779 };
780
781 mailbox0_cluster2: mailbox@29020000 {
782 compatible = "ti,am64-mailbox";
783 reg = <0x00 0x29020000 0x00 0x200>;
784 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
785 #mbox-cells = <1>;
786 ti,mbox-num-users = <4>;
787 ti,mbox-num-fifos = <16>;
788 };
789
790 mailbox0_cluster3: mailbox@29030000 {
791 compatible = "ti,am64-mailbox";
792 reg = <0x00 0x29030000 0x00 0x200>;
793 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
794 #mbox-cells = <1>;
795 ti,mbox-num-users = <4>;
796 ti,mbox-num-fifos = <16>;
797 };
798
799 ecap0: pwm@23100000 {
800 compatible = "ti,am3352-ecap";
801 #pwm-cells = <3>;
802 reg = <0x00 0x23100000 0x00 0x100>;
803 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
804 clocks = <&k3_clks 51 0>;
805 clock-names = "fck";
806 status = "disabled";
807 };
808
809 ecap1: pwm@23110000 {
810 compatible = "ti,am3352-ecap";
811 #pwm-cells = <3>;
812 reg = <0x00 0x23110000 0x00 0x100>;
813 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
814 clocks = <&k3_clks 52 0>;
815 clock-names = "fck";
816 status = "disabled";
817 };
818
819 ecap2: pwm@23120000 {
820 compatible = "ti,am3352-ecap";
821 #pwm-cells = <3>;
822 reg = <0x00 0x23120000 0x00 0x100>;
823 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
824 clocks = <&k3_clks 53 0>;
825 clock-names = "fck";
826 status = "disabled";
827 };
828
829 main_mcan0: can@20701000 {
830 compatible = "bosch,m_can";
831 reg = <0x00 0x20701000 0x00 0x200>,
832 <0x00 0x20708000 0x00 0x8000>;
833 reg-names = "m_can", "message_ram";
834 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
835 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
836 clock-names = "hclk", "cclk";
837 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
838 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
839 interrupt-names = "int0", "int1";
840 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
841 status = "disabled";
842 };
843
844 main_mcan1: can@20711000 {
845 compatible = "bosch,m_can";
846 reg = <0x00 0x20711000 0x00 0x200>,
847 <0x00 0x20718000 0x00 0x8000>;
848 reg-names = "m_can", "message_ram";
849 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
850 clocks = <&k3_clks 99 6>, <&k3_clks 99 1>;
851 clock-names = "hclk", "cclk";
852 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
854 interrupt-names = "int0", "int1";
855 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
856 status = "disabled";
857 };
858
859 main_rti0: watchdog@e000000 {
860 compatible = "ti,j7-rti-wdt";
861 reg = <0x00 0x0e000000 0x00 0x100>;
862 clocks = <&k3_clks 125 0>;
863 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
864 assigned-clocks = <&k3_clks 125 0>;
865 assigned-clock-parents = <&k3_clks 125 2>;
866 };
867
868 main_rti1: watchdog@e010000 {
869 compatible = "ti,j7-rti-wdt";
870 reg = <0x00 0x0e010000 0x00 0x100>;
871 clocks = <&k3_clks 126 0>;
872 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
873 assigned-clocks = <&k3_clks 126 0>;
874 assigned-clock-parents = <&k3_clks 126 2>;
875 };
876
877 main_rti2: watchdog@e020000 {
878 compatible = "ti,j7-rti-wdt";
879 reg = <0x00 0x0e020000 0x00 0x100>;
880 clocks = <&k3_clks 127 0>;
881 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
882 assigned-clocks = <&k3_clks 127 0>;
883 assigned-clock-parents = <&k3_clks 127 2>;
884 };
885
886 main_rti3: watchdog@e030000 {
887 compatible = "ti,j7-rti-wdt";
888 reg = <0x00 0x0e030000 0x00 0x100>;
889 clocks = <&k3_clks 128 0>;
890 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
891 assigned-clocks = <&k3_clks 128 0>;
892 assigned-clock-parents = <&k3_clks 128 2>;
893 };
894
895 main_rti15: watchdog@e0f0000 {
896 compatible = "ti,j7-rti-wdt";
897 reg = <0x00 0x0e0f0000 0x00 0x100>;
898 clocks = <&k3_clks 130 0>;
899 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>;
900 assigned-clocks = <&k3_clks 130 0>;
901 assigned-clock-parents = <&k3_clks 130 2>;
902 };
903
904 epwm0: pwm@23000000 {
905 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
906 #pwm-cells = <3>;
907 reg = <0x00 0x23000000 0x00 0x100>;
908 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
909 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
910 clock-names = "tbclk", "fck";
911 status = "disabled";
912 };
913
914 epwm1: pwm@23010000 {
915 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
916 #pwm-cells = <3>;
917 reg = <0x00 0x23010000 0x00 0x100>;
918 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
919 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
920 clock-names = "tbclk", "fck";
921 status = "disabled";
922 };
923
924 epwm2: pwm@23020000 {
925 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
926 #pwm-cells = <3>;
927 reg = <0x00 0x23020000 0x00 0x100>;
928 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
929 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
930 clock-names = "tbclk", "fck";
931 status = "disabled";
932 };
933
934 mcasp0: audio-controller@2b00000 {
935 compatible = "ti,am33xx-mcasp-audio";
936 reg = <0x00 0x02b00000 0x00 0x2000>,
937 <0x00 0x02b08000 0x00 0x400>;
938 reg-names = "mpu", "dat";
939 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
941 interrupt-names = "tx", "rx";
942
943 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
944 dma-names = "tx", "rx";
945
946 clocks = <&k3_clks 190 0>;
947 clock-names = "fck";
948 assigned-clocks = <&k3_clks 190 0>;
949 assigned-clock-parents = <&k3_clks 190 2>;
950 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
951 status = "disabled";
952 };
953
954 mcasp1: audio-controller@2b10000 {
955 compatible = "ti,am33xx-mcasp-audio";
956 reg = <0x00 0x02b10000 0x00 0x2000>,
957 <0x00 0x02b18000 0x00 0x400>;
958 reg-names = "mpu", "dat";
959 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
961 interrupt-names = "tx", "rx";
962
963 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
964 dma-names = "tx", "rx";
965
966 clocks = <&k3_clks 191 0>;
967 clock-names = "fck";
968 assigned-clocks = <&k3_clks 191 0>;
969 assigned-clock-parents = <&k3_clks 191 2>;
970 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
971 status = "disabled";
972 };
973
974 mcasp2: audio-controller@2b20000 {
975 compatible = "ti,am33xx-mcasp-audio";
976 reg = <0x00 0x02b20000 0x00 0x2000>,
977 <0x00 0x02b28000 0x00 0x400>;
978 reg-names = "mpu", "dat";
979 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
981 interrupt-names = "tx", "rx";
982
983 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
984 dma-names = "tx", "rx";
985
986 clocks = <&k3_clks 192 0>;
987 clock-names = "fck";
988 assigned-clocks = <&k3_clks 192 0>;
989 assigned-clock-parents = <&k3_clks 192 2>;
990 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
991 status = "disabled";
992 };
993
994 ti_csi2rx0: ticsi2rx@30102000 {
995 compatible = "ti,j721e-csi2rx-shim";
996 reg = <0x00 0x30102000 0x00 0x1000>;
997 ranges;
998 #address-cells = <2>;
999 #size-cells = <2>;
1000 dmas = <&main_bcdma_csi 0 0x5000 0>;
1001 dma-names = "rx0";
1002 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1003 status = "disabled";
1004
1005 cdns_csi2rx0: csi-bridge@30101000 {
1006 compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1007 reg = <0x00 0x30101000 0x00 0x1000>;
1008 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1009 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1010 clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1011 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
1012 phys = <&dphy0>;
1013 phy-names = "dphy";
1014
1015 ports {
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1018
1019 csi0_port0: port@0 {
1020 reg = <0>;
1021 status = "disabled";
1022 };
1023
1024 csi0_port1: port@1 {
1025 reg = <1>;
1026 status = "disabled";
1027 };
1028
1029 csi0_port2: port@2 {
1030 reg = <2>;
1031 status = "disabled";
1032 };
1033
1034 csi0_port3: port@3 {
1035 reg = <3>;
1036 status = "disabled";
1037 };
1038
1039 csi0_port4: port@4 {
1040 reg = <4>;
1041 status = "disabled";
1042 };
1043 };
1044 };
1045 };
1046
1047 dphy0: phy@30110000 {
1048 compatible = "cdns,dphy-rx";
1049 reg = <0x00 0x30110000 0x00 0x1100>;
1050 #phy-cells = <0>;
1051 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1052 status = "disabled";
1053 };
1054
1055 vpu: video-codec@30210000 {
1056 compatible = "ti,j721s2-wave521c", "cnm,wave521c";
1057 reg = <0x00 0x30210000 0x00 0x10000>;
1058 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&k3_clks 204 2>;
1060 power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
1061 };
1062 };
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