1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree file for the MCU domain peripherals shared by AM62P and J722S
4 *
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8 &cbass_mcu {
9 mcu_pmx0: pinctrl@4084000 {
10 compatible = "pinctrl-single";
11 reg = <0x00 0x04084000 0x00 0x88>;
12 #pinctrl-cells = <1>;
13 pinctrl-single,register-width = <32>;
14 pinctrl-single,function-mask = <0xffffffff>;
15 pinctrl-single,gpio-range =
16 <&mcu_pmx_range 0 21 PIN_GPIO_RANGE_IOPAD>,
17 <&mcu_pmx_range 23 1 PIN_GPIO_RANGE_IOPAD>,
18 <&mcu_pmx_range 32 2 PIN_GPIO_RANGE_IOPAD>;
19 bootph-all;
20
21 mcu_pmx_range: gpio-range {
22 #pinctrl-single,gpio-range-cells = <3>;
23 };
24 };
25
26 mcu_esm: esm@4100000 {
27 compatible = "ti,j721e-esm";
28 reg = <0x00 0x4100000 0x00 0x1000>;
29 ti,esm-pins = <0>, <1>, <2>, <85>;
30 status = "reserved";
31 bootph-pre-ram;
32 };
33
34 /*
35 * The MCU domain timer interrupts are routed only to the ESM module,
36 * and not currently available for Linux. The MCU domain timers are
37 * of limited use without interrupts, and likely reserved by the ESM.
38 */
39 mcu_timer0: timer@4800000 {
40 compatible = "ti,am654-timer";
41 reg = <0x00 0x4800000 0x00 0x400>;
42 clocks = <&k3_clks 35 2>;
43 clock-names = "fck";
44 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
45 ti,timer-pwm;
46 status = "reserved";
47 };
48
49 mcu_timer1: timer@4810000 {
50 compatible = "ti,am654-timer";
51 reg = <0x00 0x4810000 0x00 0x400>;
52 clocks = <&k3_clks 48 2>;
53 clock-names = "fck";
54 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
55 ti,timer-pwm;
56 status = "reserved";
57 };
58
59 mcu_timer2: timer@4820000 {
60 compatible = "ti,am654-timer";
61 reg = <0x00 0x4820000 0x00 0x400>;
62 clocks = <&k3_clks 49 2>;
63 clock-names = "fck";
64 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
65 ti,timer-pwm;
66 status = "reserved";
67 };
68
69 mcu_timer3: timer@4830000 {
70 compatible = "ti,am654-timer";
71 reg = <0x00 0x4830000 0x00 0x400>;
72 clocks = <&k3_clks 50 2>;
73 clock-names = "fck";
74 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
75 ti,timer-pwm;
76 status = "reserved";
77 };
78
79 mcu_uart0: serial@4a00000 {
80 compatible = "ti,am64-uart", "ti,am654-uart";
81 reg = <0x00 0x04a00000 0x00 0x100>;
82 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
83 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
84 clocks = <&k3_clks 149 0>;
85 clock-names = "fclk";
86 status = "disabled";
87 };
88
89 mcu_i2c0: i2c@4900000 {
90 compatible = "ti,am64-i2c", "ti,omap4-i2c";
91 reg = <0x00 0x04900000 0x00 0x100>;
92 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
93 #address-cells = <1>;
94 #size-cells = <0>;
95 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
96 clocks = <&k3_clks 106 2>;
97 clock-names = "fck";
98 status = "disabled";
99 };
100
101 mcu_spi0: spi@4b00000 {
102 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
103 reg = <0x00 0x04b00000 0x00 0x400>;
104 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
105 #address-cells = <1>;
106 #size-cells = <0>;
107 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
108 clocks = <&k3_clks 147 0>;
109 status = "disabled";
110 };
111
112 mcu_spi1: spi@4b10000 {
113 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
114 reg = <0x00 0x04b10000 0x00 0x400>;
115 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
119 clocks = <&k3_clks 148 0>;
120 status = "disabled";
121 };
122
123 mcu_gpio_intr: interrupt-controller@4210000 {
124 compatible = "ti,sci-intr";
125 reg = <0x00 0x04210000 0x00 0x200>;
126 ti,intr-trigger-type = <1>;
127 interrupt-controller;
128 interrupt-parent = <&gic500>;
129 #interrupt-cells = <1>;
130 ti,sci = <&dmsc>;
131 ti,sci-dev-id = <5>;
132 ti,interrupt-ranges = <0 104 4>;
133 };
134
135 mcu_gpio0: gpio@4201000 {
136 compatible = "ti,am64-gpio", "ti,keystone-gpio";
137 reg = <0x00 0x4201000 0x00 0x100>;
138 gpio-controller;
139 #gpio-cells = <2>;
140 interrupt-parent = <&mcu_gpio_intr>;
141 interrupts = <30>, <31>;
142 interrupt-controller;
143 #interrupt-cells = <2>;
144 ti,ngpio = <24>;
145 ti,davinci-gpio-unbanked = <0>;
146 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
147 clocks = <&k3_clks 79 0>;
148 clock-names = "gpio";
149 gpio-ranges = <&mcu_pmx0 0 0 21>, <&mcu_pmx0 21 23 1>,
150 <&mcu_pmx0 22 32 2>;
151 };
152
153 mcu_rti0: watchdog@4880000 {
154 compatible = "ti,j7-rti-wdt";
155 reg = <0x00 0x04880000 0x00 0x100>;
156 clocks = <&k3_clks 131 0>;
157 power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
158 assigned-clocks = <&k3_clks 131 0>;
159 assigned-clock-parents = <&k3_clks 131 2>;
160 /* Tightly coupled to M4F */
161 status = "reserved";
162 };
163
164 mcu_mcan0: can@4e08000 {
165 compatible = "bosch,m_can";
166 reg = <0x00 0x4e08000 0x00 0x200>,
167 <0x00 0x4e00000 0x00 0x8000>;
168 reg-names = "m_can", "message_ram";
169 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
170 clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
171 clock-names = "hclk", "cclk";
172 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
173 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
175 interrupt-names = "int0", "int1";
176 status = "disabled";
177 };
178
179 mcu_mcan1: can@4e18000 {
180 compatible = "bosch,m_can";
181 reg = <0x00 0x4e18000 0x00 0x200>,
182 <0x00 0x4e10000 0x00 0x8000>;
183 reg-names = "m_can", "message_ram";
184 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
185 clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
186 clock-names = "hclk", "cclk";
187 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
188 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
190 interrupt-names = "int0", "int1";
191 status = "disabled";
192 };
193
194 mcu_r5fss0: r5fss@79000000 {
195 compatible = "ti,am62-r5fss";
196 #address-cells = <1>;
197 #size-cells = <1>;
198 ranges = <0x79000000 0x00 0x79000000 0x8000>,
199 <0x79020000 0x00 0x79020000 0x8000>;
200 power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>;
201 status = "disabled";
202
203 mcu_r5fss0_core0: r5f@79000000 {
204 compatible = "ti,am62-r5f";
205 reg = <0x79000000 0x00008000>,
206 <0x79020000 0x00008000>;
207 reg-names = "atcm", "btcm";
208 ti,sci = <&dmsc>;
209 ti,sci-dev-id = <9>;
210 ti,sci-proc-ids = <0x03 0xff>;
211 resets = <&k3_reset 9 1>;
212 firmware-name = "am62p-mcu-r5f0_0-fw";
213 ti,atcm-enable = <0>;
214 ti,btcm-enable = <1>;
215 ti,loczrama = <0>;
216 };
217 };
218 };
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