1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree Source for AM64 SoC Family MCU Domain peripherals
4 *
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8 &cbass_mcu {
9 /*
10 * The MCU domain timer interrupts are routed only to the ESM module,
11 * and not currently available for Linux. The MCU domain timers are
12 * of limited use without interrupts, and likely reserved by the ESM.
13 */
14 mcu_timer0: timer@4800000 {
15 compatible = "ti,am654-timer";
16 reg = <0x00 0x4800000 0x00 0x400>;
17 clocks = <&k3_clks 35 1>;
18 clock-names = "fck";
19 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
20 ti,timer-pwm;
21 status = "reserved";
22 };
23
24 mcu_timer1: timer@4810000 {
25 compatible = "ti,am654-timer";
26 reg = <0x00 0x4810000 0x00 0x400>;
27 clocks = <&k3_clks 48 1>;
28 clock-names = "fck";
29 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
30 ti,timer-pwm;
31 status = "reserved";
32 };
33
34 mcu_timer2: timer@4820000 {
35 compatible = "ti,am654-timer";
36 reg = <0x00 0x4820000 0x00 0x400>;
37 clocks = <&k3_clks 49 1>;
38 clock-names = "fck";
39 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
40 ti,timer-pwm;
41 status = "reserved";
42 };
43
44 mcu_timer3: timer@4830000 {
45 compatible = "ti,am654-timer";
46 reg = <0x00 0x4830000 0x00 0x400>;
47 clocks = <&k3_clks 50 1>;
48 clock-names = "fck";
49 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
50 ti,timer-pwm;
51 status = "reserved";
52 };
53
54 mcu_uart0: serial@4a00000 {
55 compatible = "ti,am64-uart", "ti,am654-uart";
56 reg = <0x00 0x04a00000 0x00 0x100>;
57 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
58 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
59 clocks = <&k3_clks 149 0>;
60 clock-names = "fclk";
61 status = "disabled";
62 };
63
64 mcu_uart1: serial@4a10000 {
65 compatible = "ti,am64-uart", "ti,am654-uart";
66 reg = <0x00 0x04a10000 0x00 0x100>;
67 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
68 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
69 clocks = <&k3_clks 160 0>;
70 clock-names = "fclk";
71 status = "disabled";
72 };
73
74 mcu_i2c0: i2c@4900000 {
75 compatible = "ti,am64-i2c", "ti,omap4-i2c";
76 reg = <0x00 0x04900000 0x00 0x100>;
77 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
78 #address-cells = <1>;
79 #size-cells = <0>;
80 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
81 clocks = <&k3_clks 106 2>;
82 clock-names = "fck";
83 status = "disabled";
84 };
85
86 mcu_i2c1: i2c@4910000 {
87 compatible = "ti,am64-i2c", "ti,omap4-i2c";
88 reg = <0x00 0x04910000 0x00 0x100>;
89 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
90 #address-cells = <1>;
91 #size-cells = <0>;
92 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
93 clocks = <&k3_clks 107 2>;
94 clock-names = "fck";
95 status = "disabled";
96 };
97
98 mcu_spi0: spi@4b00000 {
99 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
100 reg = <0x00 0x04b00000 0x00 0x400>;
101 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
102 #address-cells = <1>;
103 #size-cells = <0>;
104 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
105 clocks = <&k3_clks 147 0>;
106 status = "disabled";
107 };
108
109 mcu_spi1: spi@4b10000 {
110 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
111 reg = <0x00 0x04b10000 0x00 0x400>;
112 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
113 #address-cells = <1>;
114 #size-cells = <0>;
115 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
116 clocks = <&k3_clks 148 0>;
117 status = "disabled";
118 };
119
120 mcu_gpio_intr: interrupt-controller@4210000 {
121 compatible = "ti,sci-intr";
122 reg = <0x00 0x04210000 0x00 0x200>;
123 ti,intr-trigger-type = <1>;
124 interrupt-controller;
125 interrupt-parent = <&gic500>;
126 #interrupt-cells = <1>;
127 ti,sci = <&dmsc>;
128 ti,sci-dev-id = <5>;
129 ti,interrupt-ranges = <0 104 4>;
130 };
131
132 mcu_gpio0: gpio@4201000 {
133 compatible = "ti,am64-gpio", "ti,keystone-gpio";
134 reg = <0x0 0x4201000 0x0 0x100>;
135 gpio-controller;
136 #gpio-cells = <2>;
137 interrupt-parent = <&mcu_gpio_intr>;
138 interrupts = <30>, <31>;
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 ti,ngpio = <23>;
142 ti,davinci-gpio-unbanked = <0>;
143 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
144 clocks = <&k3_clks 79 0>;
145 clock-names = "gpio";
146 };
147
148 mcu_pmx0: pinctrl@4084000 {
149 bootph-all;
150 compatible = "pinctrl-single";
151 reg = <0x00 0x4084000 0x00 0x84>;
152 #pinctrl-cells = <1>;
153 pinctrl-single,register-width = <32>;
154 pinctrl-single,function-mask = <0xffffffff>;
155 };
156
157 mcu_esm: esm@4100000 {
158 bootph-pre-ram;
159 compatible = "ti,j721e-esm";
160 reg = <0x00 0x4100000 0x00 0x1000>;
161 ti,esm-pins = <0>, <1>;
162 };
163 };
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