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TOMOYO Linux Cross Reference
Linux/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-pcie-usb2.dtso

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  1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
  2 /*
  3  * DT overlay for PCIe support (limits USB to 2.0/high-speed)
  4  *
  5  * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
  6  * Author: Matt McKee <mmckee@phytec.com>
  7  *
  8  * Copyright (C) 2024 PHYTEC America, LLC - https://www.phytec.com
  9  * Author: Nathan Morrisson <nmorrisson@phytec.com>
 10  */
 11 
 12 /dts-v1/;
 13 /plugin/;
 14 
 15 #include <dt-bindings/gpio/gpio.h>
 16 #include <dt-bindings/phy/phy.h>
 17 #include <dt-bindings/phy/phy-cadence.h>
 18 
 19 #include "k3-pinctrl.h"
 20 #include "k3-serdes.h"
 21 
 22 &{/} {
 23         pcie_refclk0: pcie-refclk0 {
 24                 compatible = "gpio-gate-clock";
 25                 pinctrl-names = "default";
 26                 pinctrl-0 = <&pcie_usb_sel_pins_default>;
 27                 clocks = <&serdes_refclk>;
 28                 #clock-cells = <0>;
 29                 enable-gpios = <&main_gpio1 7 GPIO_ACTIVE_HIGH>;
 30         };
 31 };
 32 
 33 &main_pmx0 {
 34         pcie_usb_sel_pins_default: pcie-usb-sel-default-pins {
 35                 pinctrl-single,pins = <
 36                         AM64X_IOPAD(0x017c, PIN_OUTPUT, 7)      /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */
 37                 >;
 38         };
 39 
 40         pcie_pins_default: pcie-default-pins {
 41                 pinctrl-single,pins = <
 42                         AM64X_IOPAD(0x0098, PIN_OUTPUT, 7)      /* (W19) GPMC0_WAIT0.GPIO0_37 */
 43                 >;
 44         };
 45 };
 46 
 47 &pcie0_rc {
 48         pinctrl-names = "default";
 49         pinctrl-0 = <&pcie_pins_default>;
 50         reset-gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>;
 51         phys = <&serdes0_pcie_usb_link>;
 52         phy-names = "pcie-phy";
 53         num-lanes = <1>;
 54         status = "okay";
 55 };
 56 
 57 &serdes0_pcie_usb_link {
 58         cdns,phy-type = <PHY_TYPE_PCIE>;
 59 };
 60 
 61 &serdes_ln_ctrl {
 62         idle-states = <AM64_SERDES0_LANE0_PCIE0>;
 63 };
 64 
 65 &serdes0 {
 66         assigned-clock-parents = <&pcie_refclk0>, <&pcie_refclk0>, <&pcie_refclk0>;
 67 };
 68 
 69 &serdes_refclk {
 70         clock-frequency = <100000000>;
 71 };
 72 
 73 /*
 74  * Assign pcie_refclk0 to serdes_wiz0 as ext_ref_clk.
 75  * This makes sure that the clock generator gets enabled at the right time.
 76  */
 77 &serdes_wiz0 {
 78         clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&pcie_refclk0>;
 79 };
 80 
 81 &usbss0 {
 82         ti,usb2-only;
 83 };
 84 
 85 &usb0 {
 86         maximum-speed = "high-speed";
 87 };

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