1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
4 *
5 */
6
7 #include <dt-bindings/net/ti-dp83869.h>
8
9 / {
10 model = "SolidRun AM642 SoM";
11 compatible = "solidrun,am642-sr-som", "ti,am642";
12
13 aliases {
14 ethernet0 = &cpsw_port1;
15 ethernet1 = &icssg1_emac0;
16 ethernet2 = &icssg1_emac1;
17 mmc0 = &sdhci0;
18 mmc1 = &sdhci1;
19 serial2 = &main_uart0;
20 };
21
22 chosen {
23 /* SoC default UART console */
24 stdout-path = "serial2:115200n8";
25 };
26
27 /* PRU Ethernet Controller */
28 ethernet {
29 compatible = "ti,am642-icssg-prueth";
30 pinctrl-names = "default";
31 pinctrl-0 = <&pru_rgmii1_default_pins>, <&pru_rgmii2_default_pins>;
32
33 sram = <&oc_sram>;
34 ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
35 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
36 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
37 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
38 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
39 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
40 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
41
42 /* configure internal pinmux for mii mode */
43 ti,pruss-gp-mux-sel = <2>, <2>, <2>, <2>, <2>, <2>;
44
45 ti,mii-g-rt = <&icssg1_mii_g_rt>;
46 ti,mii-rt = <&icssg1_mii_rt>;
47 ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
48
49 /*
50 * Configure icssg interrupt controller to map pru-internal
51 * interrupts 8/9 via channels 0/1 to host interrupts 0/1.
52 *
53 * For details see interrupt controller documentation:
54 * Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml
55 */
56 interrupt-parent = <&icssg1_intc>;
57 interrupts = <24 0 2>, <25 1 3>;
58 interrupt-names = "tx_ts0", "tx_ts1";
59
60 dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
61 <&main_pktdma 0xc201 15>, /* egress slice 0 */
62 <&main_pktdma 0xc202 15>, /* egress slice 0 */
63 <&main_pktdma 0xc203 15>, /* egress slice 0 */
64 <&main_pktdma 0xc204 15>, /* egress slice 1 */
65 <&main_pktdma 0xc205 15>, /* egress slice 1 */
66 <&main_pktdma 0xc206 15>, /* egress slice 1 */
67 <&main_pktdma 0xc207 15>, /* egress slice 1 */
68 <&main_pktdma 0x4200 15>, /* ingress slice 0 */
69 <&main_pktdma 0x4201 15>; /* ingress slice 1 */
70 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
71 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
72 "rx0", "rx1";
73
74 ethernet-ports {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 icssg1_emac0: port@0 {
79 reg = <0>;
80 ti,syscon-rgmii-delay = <&main_conf 0x4110>;
81 /* Filled in by bootloader */
82 local-mac-address = [00 00 00 00 00 00];
83 phy-handle = <ðernet_phy2>;
84 phy-mode = "rgmii-id";
85 };
86
87 icssg1_emac1: port@1 {
88 reg = <1>;
89 ti,syscon-rgmii-delay = <&main_conf 0x4114>;
90 /* Filled in by bootloader */
91 local-mac-address = [00 00 00 00 00 00];
92 phy-handle = <ðernet_phy1>;
93 phy-mode = "rgmii-id";
94 };
95 };
96 };
97
98 /* DDR16SS0:
99 * - Bank 1 @ 0x080000000-0x0FFFFFFFF: max. 2GB in 32-bit address space
100 * - Bank 2 @ 0x880000000-0x9FFFFFFFF: max. 6GB in 64-bit address space
101 */
102 memory@80000000 {
103 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
104 <0x00000008 0x80000000 0x00000001 0x80000000>;
105 device_type = "memory";
106 };
107
108 reserved-memory {
109 #address-cells = <2>;
110 #size-cells = <2>;
111 ranges;
112
113 secure_ddr: optee@9e800000 {
114 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
115 no-map;
116 };
117
118 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
119 compatible = "shared-dma-pool";
120 reg = <0x00 0xa0000000 0x00 0x100000>;
121 no-map;
122 };
123
124 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
125 compatible = "shared-dma-pool";
126 reg = <0x00 0xa0100000 0x00 0xf00000>;
127 no-map;
128 };
129
130 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
131 compatible = "shared-dma-pool";
132 reg = <0x00 0xa1000000 0x00 0x100000>;
133 no-map;
134 };
135
136 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
137 compatible = "shared-dma-pool";
138 reg = <0x00 0xa1100000 0x00 0xf00000>;
139 no-map;
140 };
141
142 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
143 compatible = "shared-dma-pool";
144 reg = <0x00 0xa2000000 0x00 0x100000>;
145 no-map;
146 };
147
148 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
149 compatible = "shared-dma-pool";
150 reg = <0x00 0xa2100000 0x00 0xf00000>;
151 no-map;
152 };
153
154 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
155 compatible = "shared-dma-pool";
156 reg = <0x00 0xa3000000 0x00 0x100000>;
157 no-map;
158 };
159
160 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
161 compatible = "shared-dma-pool";
162 reg = <0x00 0xa3100000 0x00 0xf00000>;
163 no-map;
164 };
165 };
166
167 vdd_mmc0: regulator-vdd-mmc0 {
168 compatible = "regulator-fixed";
169 regulator-name = "vdd-mmc0";
170 regulator-min-microvolt = <1800000>;
171 regulator-max-microvolt = <1800000>;
172 regulator-always-on;
173 regulator-boot-on;
174 };
175 };
176
177 &cpsw3g {
178 pinctrl-names = "default";
179 pinctrl-0 = <&rgmii1_default_pins>;
180 status = "okay";
181 };
182
183 &cpsw3g_mdio {
184 pinctrl-names = "default";
185 pinctrl-0 = <&mdio0_default_pins>;
186 status = "okay";
187
188 ethernet_phy0: ethernet-phy@0 {
189 compatible = "ethernet-phy-id2000.a0f1";
190 reg = <0>;
191 pinctrl-names = "default";
192 pinctrl-0 = <ðernet_phy0_default_pins>;
193 ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
194 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
195 /*
196 * Disable interrupts because ISR never clears 0x0040
197 *
198 * interrupt-parent = <&main_gpio1>;
199 * interrupts = <70 IRQ_TYPE_LEVEL_LOW>;
200 */
201 /*
202 * Disable HW Reset because clock signal is daisy-chained
203 *
204 * reset-gpios = <&main_gpio0 84 GPIO_ACTIVE_LOW>;
205 * reset-assert-us = <1>;
206 * reset-deassert-us = <30>;
207 */
208 };
209 };
210
211 &cpsw_port1 {
212 phy-mode = "rgmii-id";
213 phy-handle = <ðernet_phy0>;
214 status = "okay";
215 };
216
217 &icssg1_mdio {
218 pinctrl-names = "default";
219 pinctrl-0 = <&pru1_mdio0_default_pins>;
220 status = "okay";
221
222 ethernet_phy1: ethernet-phy@3 {
223 compatible = "ethernet-phy-id2000.a0f1";
224 reg = <3>;
225 pinctrl-names = "default";
226 pinctrl-0 = <ðernet_phy1_default_pins>;
227 ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
228 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
229 /*
230 * Disable interrupts because ISR never clears 0x0040
231 *
232 * interrupt-parent = <&main_gpio1>;
233 * interrupts = <70 IRQ_TYPE_LEVEL_LOW>;
234 */
235 /*
236 * Disable HW Reset because clock signal is daisy-chained
237 *
238 * reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>;
239 * reset-assert-us = <1>;
240 * reset-deassert-us = <30>;
241 */
242 };
243
244 ethernet_phy2: ethernet-phy@f {
245 compatible = "ethernet-phy-id2000.a0f1";
246 reg = <0xf>;
247 pinctrl-names = "default";
248 pinctrl-0 = <ðernet_phy2_default_pins>;
249 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
250 /*
251 * Disable interrupts because ISR never clears 0x0040
252 *
253 * interrupt-parent = <&main_gpio1>;
254 * interrupts = <70 IRQ_TYPE_LEVEL_LOW>;
255 */
256 /*
257 * Disable HW Reset because clock signal is daisy-chained
258 *
259 * reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>;
260 * reset-assert-us = <1>;
261 * reset-deassert-us = <30>;
262 */
263 };
264 };
265
266 &mailbox0_cluster2 {
267 status = "okay";
268
269 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
270 ti,mbox-rx = <0 0 2>;
271 ti,mbox-tx = <1 0 2>;
272 };
273
274 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
275 ti,mbox-rx = <2 0 2>;
276 ti,mbox-tx = <3 0 2>;
277 };
278 };
279
280 &mailbox0_cluster4 {
281 status = "okay";
282
283 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
284 ti,mbox-rx = <0 0 2>;
285 ti,mbox-tx = <1 0 2>;
286 };
287
288 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
289 ti,mbox-rx = <2 0 2>;
290 ti,mbox-tx = <3 0 2>;
291 };
292 };
293
294 &main_i2c0 {
295 pinctrl-names = "default";
296 pinctrl-0 = <&main_i2c0_default_pins>;
297 status = "okay";
298
299 som_eeprom: eeprom@50 {
300 compatible = "atmel,24c01";
301 reg = <0x50>;
302 pagesize = <8>;
303 };
304 };
305
306 &main_pmx0 {
307 /* hog global functions */
308 pinctrl-names = "default";
309 pinctrl-0 = <ðernet_phy_default_pins>;
310
311 ethernet_phy_default_pins: ethernet-phy-default-pins {
312 pinctrl-single,pins = <
313 /* interrupt / power-down, external pull-up on SoM */
314 AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* EXTINTn.GPIO1_70 */
315 >;
316 };
317
318 ethernet_phy0_default_pins: ethernet-phy0-default-pins {
319 pinctrl-single,pins = <
320 /* reset */
321 AM64X_IOPAD(0x0154, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO19.GPIO0_84 */
322 /* reference clock */
323 AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* EXT_REFCLK1.CLKOUT0 */
324 >;
325 };
326
327 ethernet_phy1_default_pins: ethernet-phy1-default-pins {
328 pinctrl-single,pins = <
329 /* reset */
330 AM64X_IOPAD(0x0150, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO18.GPIO0_20 */
331 /* led0, external pull-down on SoM */
332 AM64X_IOPAD(0x0128, PIN_INPUT, 7) /* PRG1_PRU1_GPO8.GPIO0_73 */
333 /* led1/rxer */
334 AM64X_IOPAD(0x011c, PIN_INPUT, 7) /* PRG1_PRU1_GPO5.GPIO0_70 */
335 >;
336 };
337
338 ethernet_phy2_default_pins: ethernet-phy2-default-pins {
339 pinctrl-single,pins = <
340 /* reset */
341 AM64X_IOPAD(0x00d4, PIN_OUTPUT, 7) /* PRG1_PRU0_GPO7.GPIO0_52 */
342 /* led0, external pull-down on SoM */
343 AM64X_IOPAD(0x00d8, PIN_INPUT, 7) /* PRG1_PRU0_GPO8.GPIO0_53 */
344 /* led1/rxer */
345 AM64X_IOPAD(0x00cc, PIN_INPUT, 7) /* PRG1_PRU0_GPO5.GPIO0_50 */
346 >;
347 };
348
349 main_i2c0_default_pins: main-i2c0-default-pins {
350 pinctrl-single,pins = <
351 /* external pull-up on SoM */
352 AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* I2C0_SCL.I2C0_SCL */
353 AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* I2C0_SDA.I2C0_SDA */
354 >;
355 };
356
357 /*
358 * main_mmc0_default_pins: main-mmc0-default-pins
359 *
360 * MMC0_CMD: no padconfig
361 * MMC0_CLK: no padconfig, external pull-up on SoM
362 * MMC0_DAT0: no padconfig
363 * MMC0_DAT1: no padconfig
364 * MMC0_DAT2: no padconfig
365 * MMC0_DAT3: no padconfig
366 * MMC0_DAT4: no padconfig
367 * MMC0_DAT5: no padconfig
368 * MMC0_DAT6: no padconfig
369 * MMC0_DAT7: no padconfig
370 * MMC0_DS: no padconfig, external pull-down on SoM
371 */
372
373 main_mmc1_default_pins: main-mmc1-default-pins {
374 pinctrl-single,pins = <
375 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
376 AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* MMC1_CLK.MMC1_CLK */
377 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* MMC1_DAT0.MMC1_DAT0 */
378 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* MMC1_DAT1.MMC1_DAT1 */
379 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* MMC1_DAT2.MMC1_DAT2 */
380 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* MMC1_DAT3.MMC1_DAT3 */
381 /* external pull-down on SoM & Carrier */
382 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* MMC1_SDCD.MMC1_SDCD */
383 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB: clock loopback */
384 >;
385 };
386
387 main_uart0_default_pins: main-uart0-default-pins {
388 pinctrl-single,pins = <
389 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* UART0_RXD.UART0_RXD */
390 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* UART0_TXD.UART0_TXD */
391 >;
392 };
393
394 mdio0_default_pins: mdio0-default-pins {
395 pinctrl-single,pins = <
396 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* PRG0_PRU1_GPO19.MDIO0_MDC */
397 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* PRG0_PRU1_GPO18.MDIO0_MDIO */
398 >;
399 };
400
401 ospi0_default_pins: ospi0-default-pins {
402 pinctrl-single,pins = <
403 /* external pull-down on SoM */
404 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* OSPI0_CLK.OSPI0_CLK */
405 AM64X_IOPAD(0x0008, PIN_OUTPUT, 0) /* OSPI0_DQS.OSPI0_DQS */
406 /* external pull-up on SoM */
407 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* OSPI0_CSn0.OSPI0_CSn0 */
408 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* OSPI0_D0.OSPI0_D0 */
409 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* OSPI0_D1.OSPI0_D1 */
410 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* OSPI0_D2.OSPI0_D2 */
411 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* OSPI0_D3.OSPI0_D3 */
412 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* OSPI0_D4.OSPI0_D4 */
413 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* OSPI0_D5.OSPI0_D5 */
414 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* OSPI0_D6.OSPI0_D6 */
415 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* OSPI0_D7.OSPI0_D7 */
416 >;
417 };
418
419 ospi0_flash0_default_pins: ospi0-flash0-default-pins {
420 pinctrl-single,pins = <
421 AM64X_IOPAD(0x0034, PIN_OUTPUT, 7) /* OSPI0_CSn2.GPIO0_13 */
422 AM64X_IOPAD(0x0038, PIN_INPUT, 7) /* OSPI0_CSn3.GPIO0_14 */
423 >;
424 };
425
426 pru1_mdio0_default_pins: pru1-mdio0-default-pins {
427 pinctrl-single,pins = <
428 AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* PRG1_MDIO0_MDC.PRG1_MDIO0_MDC */
429 AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* PRG1_MDIO0_MDIO.PRG1_MDIO0_MDIO */
430 >;
431 };
432
433 pru_rgmii1_default_pins: pru-rgmii1-default-pins {
434 pinctrl-single,pins = <
435 AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
436 AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
437 AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
438 AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
439 AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
440 AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
441 AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
442 AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
443 AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
444 AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
445 AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
446 AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
447 >;
448 };
449
450 pru_rgmii2_default_pins: pru-rgmii2-default-pins {
451 pinctrl-single,pins = <
452 AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* PRG1_PRU1_GPO0.RGMII2_RD0 */
453 AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* PRG1_PRU1_GPO1.RGMII2_RD1 */
454 AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* PRG1_PRU1_GPO2.RGMII2_RD2 */
455 AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* PRG1_PRU1_GPO3.RGMII2_RD3 */
456 AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* PRG1_PRU1_GPO6.RGMII2_RXC */
457 AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* PRG1_PRU1_GPO4.RGMII2_RX_CTL */
458 AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO11.RGMII2_TD0 */
459 AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO12.RGMII2_TD1 */
460 AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO13.RGMII2_TD2 */
461 AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO14.RGMII2_TD3 */
462 AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* PRG1_PRU1_GPO16.RGMII2_TXC */
463 AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO15.RGMII2_TX_CTL */
464 >;
465 };
466
467 rgmii1_default_pins: rgmii1-default-pins {
468 pinctrl-single,pins = <
469 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* PRG0_PRU1_GPO7.RGMII1_RD0 */
470 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* PRG0_PRU1_GPO9.RGMII1_RD1 */
471 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* PRG0_PRU1_GPO10.RGMII1_RD2 */
472 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* PRG0_PRU1_GPO17.RGMII1_RD3 */
473 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* PRG0_PRU0_GPO10.RGMII1_RXC */
474 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* PRG0_PRU0_GPO9.RGMII1_RX_CTL */
475 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO7.RGMII1_TD0 */
476 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO9.RGMII1_TD1 */
477 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO10.RGMII1_TD2 */
478 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO17.RGMII1_TD3 */
479 AM64X_IOPAD(0x00e0, PIN_INPUT, 4) /* PRG1_PRU0_GPO10.RGMII1_TXC */
480 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* PRG1_PRU0_GPO9.RGMII1_TX_CTL */
481 >;
482 };
483
484 usb0_default_pins: usb0-default-pins {
485 pinctrl-single,pins = <
486 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */
487 >;
488 };
489 };
490
491 &main_r5fss0_core0 {
492 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
493 memory-region = <&main_r5fss0_core0_dma_memory_region>,
494 <&main_r5fss0_core0_memory_region>;
495 };
496
497 &main_r5fss0_core1 {
498 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
499 memory-region = <&main_r5fss0_core1_dma_memory_region>,
500 <&main_r5fss0_core1_memory_region>;
501 };
502
503 &main_r5fss1_core0 {
504 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
505 memory-region = <&main_r5fss1_core0_dma_memory_region>,
506 <&main_r5fss1_core0_memory_region>;
507 };
508
509 &main_r5fss1_core1 {
510 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
511 memory-region = <&main_r5fss1_core1_dma_memory_region>,
512 <&main_r5fss1_core1_memory_region>;
513 };
514
515 /* SoC default UART console */
516 &main_uart0 {
517 pinctrl-names = "default";
518 pinctrl-0 = <&main_uart0_default_pins>;
519 status = "okay";
520 };
521
522 &ospi0 {
523 pinctrl-names = "default";
524 pinctrl-0 = <&ospi0_default_pins>;
525 num-cs = <1>;
526 status = "okay";
527
528 flash@0 {
529 compatible = "jedec,spi-nor";
530 reg = <0>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&ospi0_flash0_default_pins>;
533 spi-tx-bus-width = <8>;
534 spi-rx-bus-width = <8>;
535 spi-max-frequency = <200000000>;
536 cdns,tshsl-ns = <50>;
537 cdns,tsd2d-ns = <50>;
538 cdns,tchsh-ns = <4>;
539 cdns,tslch-ns = <4>;
540 cdns,read-delay = <0>;
541 interrupt-parent = <&main_gpio0>;
542 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
543 reset-gpios = <&main_gpio0 13 GPIO_ACTIVE_LOW>;
544 };
545 };
546
547 &sdhci0 {
548 /* mmc0 pins have no padconfig */
549 bus-width = <8>;
550 ti,driver-strength-ohm = <50>;
551 disable-wp;
552 non-removable;
553 cap-mmc-hw-reset;
554 no-sd;
555 /*
556 * MMC controller supports switching between 1.8V and 3.3V signalling.
557 * However MMC0 (unlike MMC1) does not integrate an LDO.
558 * Explicitly link a regulator node for indicating to the driver which
559 * voltages are actually usable.
560 */
561 vqmmc-supply = <&vdd_mmc0>;
562 status = "okay";
563 };
564
565 /*
566 * microSD is on carrier - however since SoC can boot from it,
567 * configure it just in case.
568 */
569 &sdhci1 {
570 pinctrl-names = "default";
571 pinctrl-0 = <&main_mmc1_default_pins>;
572 bus-width = <4>;
573 ti,driver-strength-ohm = <50>;
574 disable-wp;
575 status = "okay";
576 };
577
578 /*
579 * USB settings are a carrier choice - however since SoC can boot from it,
580 * configure as USB-2.0 OTG here, keeping USB-3 serdes disabled.
581 */
582 &usb0 {
583 pinctrl-names = "default";
584 pinctrl-0 = <&usb0_default_pins>;
585 dr_mode = "otg";
586 maximum-speed = "high-speed";
587 };
588
589 &usbss0 {
590 ti,vbus-divider;
591 ti,usb2-only;
592 };
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