1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree Source for AM6 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7 #include <dt-bindings/phy/phy-am654-serdes.h>
8
9 &cbass_main {
10 msmc_ram: sram@70000000 {
11 compatible = "mmio-sram";
12 reg = <0x0 0x70000000 0x0 0x200000>;
13 #address-cells = <1>;
14 #size-cells = <1>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
16
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
19 };
20
21 sysfw-sram@f0000 {
22 reg = <0xf0000 0x10000>;
23 };
24
25 l3cache-sram@100000 {
26 reg = <0x100000 0x100000>;
27 };
28 };
29
30 gic500: interrupt-controller@1800000 {
31 compatible = "arm,gic-v3";
32 #address-cells = <2>;
33 #size-cells = <2>;
34 ranges;
35 #interrupt-cells = <3>;
36 interrupt-controller;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
42 /*
43 * vcpumntirq:
44 * virtual CPU interface maintenance interrupt
45 */
46 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
47
48 gic_its: msi-controller@1820000 {
49 compatible = "arm,gic-v3-its";
50 reg = <0x00 0x01820000 0x00 0x10000>;
51 socionext,synquacer-pre-its = <0x1000000 0x400000>;
52 msi-controller;
53 #msi-cells = <1>;
54 };
55 };
56
57 serdes0: serdes@900000 {
58 compatible = "ti,phy-am654-serdes";
59 reg = <0x0 0x900000 0x0 0x2000>;
60 reg-names = "serdes";
61 #phy-cells = <2>;
62 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
63 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
64 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
65 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
66 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
67 ti,serdes-clk = <&serdes0_clk>;
68 #clock-cells = <1>;
69 mux-controls = <&serdes0_mux 0>;
70 };
71
72 serdes1: serdes@910000 {
73 compatible = "ti,phy-am654-serdes";
74 reg = <0x0 0x910000 0x0 0x2000>;
75 reg-names = "serdes";
76 #phy-cells = <2>;
77 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
78 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
79 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
80 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
81 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
82 ti,serdes-clk = <&serdes1_clk>;
83 #clock-cells = <1>;
84 mux-controls = <&serdes1_mux 0>;
85 };
86
87 main_uart0: serial@2800000 {
88 compatible = "ti,am654-uart";
89 reg = <0x00 0x02800000 0x00 0x100>;
90 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
91 clock-frequency = <48000000>;
92 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
93 status = "disabled";
94 };
95
96 main_uart1: serial@2810000 {
97 compatible = "ti,am654-uart";
98 reg = <0x00 0x02810000 0x00 0x100>;
99 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
100 clock-frequency = <48000000>;
101 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
102 status = "disabled";
103 };
104
105 main_uart2: serial@2820000 {
106 compatible = "ti,am654-uart";
107 reg = <0x00 0x02820000 0x00 0x100>;
108 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
109 clock-frequency = <48000000>;
110 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
111 status = "disabled";
112 };
113
114 crypto: crypto@4e00000 {
115 compatible = "ti,am654-sa2ul";
116 reg = <0x0 0x4e00000 0x0 0x1200>;
117 power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
118 #address-cells = <2>;
119 #size-cells = <2>;
120 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
121
122 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
123 <&main_udmap 0x4003>;
124 dma-names = "tx", "rx1", "rx2";
125
126 rng: rng@4e10000 {
127 compatible = "inside-secure,safexcel-eip76";
128 reg = <0x0 0x4e10000 0x0 0x7d>;
129 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
130 status = "disabled"; /* Used by OP-TEE */
131 };
132 };
133
134 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
135 main_timerio_input: pinctrl@104200 {
136 compatible = "pinctrl-single";
137 reg = <0x0 0x104200 0x0 0x30>;
138 #pinctrl-cells = <1>;
139 pinctrl-single,register-width = <32>;
140 pinctrl-single,function-mask = <0x0000001ff>;
141 };
142
143 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
144 main_timerio_output: pinctrl@104280 {
145 compatible = "pinctrl-single";
146 reg = <0x0 0x104280 0x0 0x20>;
147 #pinctrl-cells = <1>;
148 pinctrl-single,register-width = <32>;
149 pinctrl-single,function-mask = <0x0000000f>;
150 };
151
152 main_pmx0: pinctrl@11c000 {
153 compatible = "pinctrl-single";
154 reg = <0x0 0x11c000 0x0 0x2e4>;
155 #pinctrl-cells = <1>;
156 pinctrl-single,register-width = <32>;
157 pinctrl-single,function-mask = <0xffffffff>;
158 };
159
160 main_pmx1: pinctrl@11c2e8 {
161 compatible = "pinctrl-single";
162 reg = <0x0 0x11c2e8 0x0 0x24>;
163 #pinctrl-cells = <1>;
164 pinctrl-single,register-width = <32>;
165 pinctrl-single,function-mask = <0xffffffff>;
166 };
167
168 main_i2c0: i2c@2000000 {
169 compatible = "ti,am654-i2c", "ti,omap4-i2c";
170 reg = <0x0 0x2000000 0x0 0x100>;
171 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 clock-names = "fck";
175 clocks = <&k3_clks 110 1>;
176 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
177 status = "disabled";
178 };
179
180 main_i2c1: i2c@2010000 {
181 compatible = "ti,am654-i2c", "ti,omap4-i2c";
182 reg = <0x0 0x2010000 0x0 0x100>;
183 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
184 #address-cells = <1>;
185 #size-cells = <0>;
186 clock-names = "fck";
187 clocks = <&k3_clks 111 1>;
188 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
189 status = "disabled";
190 };
191
192 main_i2c2: i2c@2020000 {
193 compatible = "ti,am654-i2c", "ti,omap4-i2c";
194 reg = <0x0 0x2020000 0x0 0x100>;
195 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
196 #address-cells = <1>;
197 #size-cells = <0>;
198 clock-names = "fck";
199 clocks = <&k3_clks 112 1>;
200 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
201 status = "disabled";
202 };
203
204 main_i2c3: i2c@2030000 {
205 compatible = "ti,am654-i2c", "ti,omap4-i2c";
206 reg = <0x0 0x2030000 0x0 0x100>;
207 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
208 #address-cells = <1>;
209 #size-cells = <0>;
210 clock-names = "fck";
211 clocks = <&k3_clks 113 1>;
212 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
213 status = "disabled";
214 };
215
216 ecap0: pwm@3100000 {
217 compatible = "ti,am654-ecap", "ti,am3352-ecap";
218 #pwm-cells = <3>;
219 reg = <0x0 0x03100000 0x0 0x60>;
220 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
221 clocks = <&k3_clks 39 0>;
222 clock-names = "fck";
223 status = "disabled";
224 };
225
226 main_spi0: spi@2100000 {
227 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
228 reg = <0x0 0x2100000 0x0 0x400>;
229 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&k3_clks 137 1>;
231 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
232 #address-cells = <1>;
233 #size-cells = <0>;
234 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
235 dma-names = "tx0", "rx0";
236 status = "disabled";
237 };
238
239 main_spi1: spi@2110000 {
240 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
241 reg = <0x0 0x2110000 0x0 0x400>;
242 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&k3_clks 138 1>;
244 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
245 #address-cells = <1>;
246 #size-cells = <0>;
247 assigned-clocks = <&k3_clks 137 1>;
248 assigned-clock-rates = <48000000>;
249 status = "disabled";
250 };
251
252 main_spi2: spi@2120000 {
253 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
254 reg = <0x0 0x2120000 0x0 0x400>;
255 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&k3_clks 139 1>;
257 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
258 #address-cells = <1>;
259 #size-cells = <0>;
260 status = "disabled";
261 };
262
263 main_spi3: spi@2130000 {
264 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
265 reg = <0x0 0x2130000 0x0 0x400>;
266 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&k3_clks 140 1>;
268 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 status = "disabled";
272 };
273
274 main_spi4: spi@2140000 {
275 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
276 reg = <0x0 0x2140000 0x0 0x400>;
277 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&k3_clks 141 1>;
279 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282 status = "disabled";
283 };
284
285 main_timer0: timer@2400000 {
286 compatible = "ti,am654-timer";
287 reg = <0x00 0x2400000 0x00 0x400>;
288 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&k3_clks 23 0>;
290 clock-names = "fck";
291 assigned-clocks = <&k3_clks 23 0>;
292 assigned-clock-parents = <&k3_clks 23 1>;
293 power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>;
294 ti,timer-pwm;
295 };
296
297 main_timer1: timer@2410000 {
298 compatible = "ti,am654-timer";
299 reg = <0x00 0x2410000 0x00 0x400>;
300 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&k3_clks 24 0>;
302 clock-names = "fck";
303 assigned-clocks = <&k3_clks 24 0>;
304 assigned-clock-parents = <&k3_clks 24 1>;
305 power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>;
306 ti,timer-pwm;
307 };
308
309 main_timer2: timer@2420000 {
310 compatible = "ti,am654-timer";
311 reg = <0x00 0x2420000 0x00 0x400>;
312 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&k3_clks 27 0>;
314 clock-names = "fck";
315 assigned-clocks = <&k3_clks 27 0>;
316 assigned-clock-parents = <&k3_clks 27 1>;
317 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
318 ti,timer-pwm;
319 };
320
321 main_timer3: timer@2430000 {
322 compatible = "ti,am654-timer";
323 reg = <0x00 0x2430000 0x00 0x400>;
324 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&k3_clks 28 0>;
326 clock-names = "fck";
327 assigned-clocks = <&k3_clks 28 0>;
328 assigned-clock-parents = <&k3_clks 28 1>;
329 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
330 ti,timer-pwm;
331 };
332
333 main_timer4: timer@2440000 {
334 compatible = "ti,am654-timer";
335 reg = <0x00 0x2440000 0x00 0x400>;
336 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&k3_clks 29 0>;
338 clock-names = "fck";
339 assigned-clocks = <&k3_clks 29 0>;
340 assigned-clock-parents = <&k3_clks 29 1>;
341 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
342 ti,timer-pwm;
343 };
344
345 main_timer5: timer@2450000 {
346 compatible = "ti,am654-timer";
347 reg = <0x00 0x2450000 0x00 0x400>;
348 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&k3_clks 30 0>;
350 clock-names = "fck";
351 assigned-clocks = <&k3_clks 30 0>;
352 assigned-clock-parents = <&k3_clks 30 1>;
353 power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>;
354 ti,timer-pwm;
355 };
356
357 main_timer6: timer@2460000 {
358 compatible = "ti,am654-timer";
359 reg = <0x00 0x2460000 0x00 0x400>;
360 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&k3_clks 31 0>;
362 assigned-clocks = <&k3_clks 31 0>;
363 assigned-clock-parents = <&k3_clks 31 1>;
364 clock-names = "fck";
365 power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>;
366 ti,timer-pwm;
367 };
368
369 main_timer7: timer@2470000 {
370 compatible = "ti,am654-timer";
371 reg = <0x00 0x2470000 0x00 0x400>;
372 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&k3_clks 32 0>;
374 clock-names = "fck";
375 assigned-clocks = <&k3_clks 32 0>;
376 assigned-clock-parents = <&k3_clks 32 1>;
377 power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>;
378 ti,timer-pwm;
379 };
380
381 main_timer8: timer@2480000 {
382 compatible = "ti,am654-timer";
383 reg = <0x00 0x2480000 0x00 0x400>;
384 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&k3_clks 33 0>;
386 clock-names = "fck";
387 assigned-clocks = <&k3_clks 33 0>;
388 assigned-clock-parents = <&k3_clks 33 1>;
389 power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>;
390 ti,timer-pwm;
391 };
392
393 main_timer9: timer@2490000 {
394 compatible = "ti,am654-timer";
395 reg = <0x00 0x2490000 0x00 0x400>;
396 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&k3_clks 34 0>;
398 clock-names = "fck";
399 assigned-clocks = <&k3_clks 34 0>;
400 assigned-clock-parents = <&k3_clks 34 1>;
401 power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>;
402 ti,timer-pwm;
403 };
404
405 main_timer10: timer@24a0000 {
406 compatible = "ti,am654-timer";
407 reg = <0x00 0x24a0000 0x00 0x400>;
408 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&k3_clks 25 0>;
410 clock-names = "fck";
411 assigned-clocks = <&k3_clks 25 0>;
412 assigned-clock-parents = <&k3_clks 25 1>;
413 power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>;
414 ti,timer-pwm;
415 };
416
417 main_timer11: timer@24b0000 {
418 compatible = "ti,am654-timer";
419 reg = <0x00 0x24b0000 0x00 0x400>;
420 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&k3_clks 26 0>;
422 clock-names = "fck";
423 assigned-clocks = <&k3_clks 26 0>;
424 assigned-clock-parents = <&k3_clks 26 1>;
425 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
426 ti,timer-pwm;
427 };
428
429 sdhci0: mmc@4f80000 {
430 compatible = "ti,am654-sdhci-5.1";
431 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
432 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
433 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
434 clock-names = "clk_ahb", "clk_xin";
435 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
436 mmc-ddr-1_8v;
437 mmc-hs200-1_8v;
438 ti,clkbuf-sel = <0x7>;
439 ti,trm-icp = <0x8>;
440 ti,otap-del-sel-legacy = <0x0>;
441 ti,otap-del-sel-mmc-hs = <0x0>;
442 ti,otap-del-sel-ddr52 = <0x5>;
443 ti,otap-del-sel-hs200 = <0x5>;
444 ti,itap-del-sel-ddr52 = <0x0>;
445 dma-coherent;
446 status = "disabled";
447 };
448
449 sdhci1: mmc@4fa0000 {
450 compatible = "ti,am654-sdhci-5.1";
451 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
452 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
453 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
454 clock-names = "clk_ahb", "clk_xin";
455 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
456 ti,clkbuf-sel = <0x7>;
457 ti,trm-icp = <0x8>;
458 ti,otap-del-sel-legacy = <0x0>;
459 ti,otap-del-sel-sd-hs = <0x0>;
460 ti,otap-del-sel-sdr12 = <0xf>;
461 ti,otap-del-sel-sdr25 = <0xf>;
462 ti,otap-del-sel-sdr50 = <0x8>;
463 ti,otap-del-sel-sdr104 = <0x7>;
464 ti,otap-del-sel-ddr50 = <0x4>;
465 ti,itap-del-sel-legacy = <0xa>;
466 ti,itap-del-sel-sd-hs = <0x1>;
467 ti,itap-del-sel-sdr12 = <0xa>;
468 ti,itap-del-sel-sdr25 = <0x1>;
469 dma-coherent;
470 status = "disabled";
471 };
472
473 scm_conf: scm-conf@100000 {
474 compatible = "syscon", "simple-mfd";
475 reg = <0 0x00100000 0 0x1c000>;
476 #address-cells = <1>;
477 #size-cells = <1>;
478 ranges = <0x0 0x0 0x00100000 0x1c000>;
479
480 serdes0_clk: clock@4080 {
481 compatible = "ti,am654-serdes-ctrl", "syscon";
482 reg = <0x4080 0x4>;
483
484 serdes0_mux: mux-controller {
485 compatible = "mmio-mux";
486 #mux-control-cells = <1>;
487 mux-reg-masks = <0x0 0x3>; /* lane select */
488 };
489 };
490
491 serdes1_clk: clock@4090 {
492 compatible = "ti,am654-serdes-ctrl", "syscon";
493 reg = <0x4090 0x4>;
494
495 serdes1_mux: mux-controller {
496 compatible = "mmio-mux";
497 #mux-control-cells = <1>;
498 mux-reg-masks = <0x0 0x3>; /* lane select */
499 };
500 };
501
502 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
503 compatible = "ti,am654-dss-oldi-io-ctrl", "syscon";
504 reg = <0x41e0 0x14>;
505 };
506
507 ehrpwm_tbclk: clock-controller@4140 {
508 compatible = "ti,am654-ehrpwm-tbclk";
509 reg = <0x4140 0x18>;
510 #clock-cells = <1>;
511 };
512 };
513
514 dwc3_0: dwc3@4000000 {
515 compatible = "ti,am654-dwc3";
516 reg = <0x0 0x4000000 0x0 0x4000>;
517 #address-cells = <1>;
518 #size-cells = <1>;
519 ranges = <0x0 0x0 0x4000000 0x20000>;
520 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
521 dma-coherent;
522 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
523 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
524 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
525 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
526 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
527
528 usb0: usb@10000 {
529 compatible = "snps,dwc3";
530 reg = <0x10000 0x10000>;
531 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
534 interrupt-names = "peripheral",
535 "host",
536 "otg";
537 maximum-speed = "high-speed";
538 dr_mode = "otg";
539 phys = <&usb0_phy>;
540 phy-names = "usb2-phy";
541 snps,dis_u3_susphy_quirk;
542 };
543 };
544
545 usb0_phy: phy@4100000 {
546 compatible = "ti,am654-usb2", "ti,omap-usb2";
547 reg = <0x0 0x4100000 0x0 0x54>;
548 syscon-phy-power = <&scm_conf 0x4000>;
549 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
550 clock-names = "wkupclk", "refclk";
551 #phy-cells = <0>;
552 };
553
554 dwc3_1: dwc3@4020000 {
555 compatible = "ti,am654-dwc3";
556 reg = <0x0 0x4020000 0x0 0x4000>;
557 #address-cells = <1>;
558 #size-cells = <1>;
559 ranges = <0x0 0x0 0x4020000 0x20000>;
560 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
561 dma-coherent;
562 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
563 clocks = <&k3_clks 152 2>;
564 assigned-clocks = <&k3_clks 152 2>;
565 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
566
567 usb1: usb@10000 {
568 compatible = "snps,dwc3";
569 reg = <0x10000 0x10000>;
570 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
573 interrupt-names = "peripheral",
574 "host",
575 "otg";
576 maximum-speed = "high-speed";
577 dr_mode = "otg";
578 phys = <&usb1_phy>;
579 phy-names = "usb2-phy";
580 };
581 };
582
583 usb1_phy: phy@4110000 {
584 compatible = "ti,am654-usb2", "ti,omap-usb2";
585 reg = <0x0 0x4110000 0x0 0x54>;
586 syscon-phy-power = <&scm_conf 0x4020>;
587 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
588 clock-names = "wkupclk", "refclk";
589 #phy-cells = <0>;
590 };
591
592 intr_main_gpio: interrupt-controller@a00000 {
593 compatible = "ti,sci-intr";
594 reg = <0x0 0x00a00000 0x0 0x400>;
595 ti,intr-trigger-type = <1>;
596 interrupt-controller;
597 interrupt-parent = <&gic500>;
598 #interrupt-cells = <1>;
599 ti,sci = <&dmsc>;
600 ti,sci-dev-id = <100>;
601 ti,interrupt-ranges = <0 392 32>;
602 };
603
604 main_navss: bus@30800000 {
605 compatible = "simple-bus";
606 #address-cells = <2>;
607 #size-cells = <2>;
608 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
609 dma-coherent;
610 dma-ranges;
611
612 ti,sci-dev-id = <118>;
613
614 intr_main_navss: interrupt-controller@310e0000 {
615 compatible = "ti,sci-intr";
616 reg = <0x0 0x310e0000 0x0 0x2000>;
617 ti,intr-trigger-type = <4>;
618 interrupt-controller;
619 interrupt-parent = <&gic500>;
620 #interrupt-cells = <1>;
621 ti,sci = <&dmsc>;
622 ti,sci-dev-id = <182>;
623 ti,interrupt-ranges = <0 64 64>,
624 <64 448 64>;
625 };
626
627 inta_main_udmass: interrupt-controller@33d00000 {
628 compatible = "ti,sci-inta";
629 reg = <0x0 0x33d00000 0x0 0x100000>;
630 interrupt-controller;
631 interrupt-parent = <&intr_main_navss>;
632 msi-controller;
633 #interrupt-cells = <0>;
634 ti,sci = <&dmsc>;
635 ti,sci-dev-id = <179>;
636 ti,interrupt-ranges = <0 0 256>;
637 };
638
639 secure_proxy_main: mailbox@32c00000 {
640 compatible = "ti,am654-secure-proxy";
641 #mbox-cells = <1>;
642 reg-names = "target_data", "rt", "scfg";
643 reg = <0x00 0x32c00000 0x00 0x100000>,
644 <0x00 0x32400000 0x00 0x100000>,
645 <0x00 0x32800000 0x00 0x100000>;
646 interrupt-names = "rx_011";
647 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
648 };
649
650 hwspinlock: spinlock@30e00000 {
651 compatible = "ti,am654-hwspinlock";
652 reg = <0x00 0x30e00000 0x00 0x1000>;
653 #hwlock-cells = <1>;
654 };
655
656 mailbox0_cluster0: mailbox@31f80000 {
657 compatible = "ti,am654-mailbox";
658 reg = <0x00 0x31f80000 0x00 0x200>;
659 #mbox-cells = <1>;
660 ti,mbox-num-users = <4>;
661 ti,mbox-num-fifos = <16>;
662 interrupt-parent = <&intr_main_navss>;
663 status = "disabled";
664 };
665
666 mailbox0_cluster1: mailbox@31f81000 {
667 compatible = "ti,am654-mailbox";
668 reg = <0x00 0x31f81000 0x00 0x200>;
669 #mbox-cells = <1>;
670 ti,mbox-num-users = <4>;
671 ti,mbox-num-fifos = <16>;
672 interrupt-parent = <&intr_main_navss>;
673 status = "disabled";
674 };
675
676 mailbox0_cluster2: mailbox@31f82000 {
677 compatible = "ti,am654-mailbox";
678 reg = <0x00 0x31f82000 0x00 0x200>;
679 #mbox-cells = <1>;
680 ti,mbox-num-users = <4>;
681 ti,mbox-num-fifos = <16>;
682 interrupt-parent = <&intr_main_navss>;
683 status = "disabled";
684 };
685
686 mailbox0_cluster3: mailbox@31f83000 {
687 compatible = "ti,am654-mailbox";
688 reg = <0x00 0x31f83000 0x00 0x200>;
689 #mbox-cells = <1>;
690 ti,mbox-num-users = <4>;
691 ti,mbox-num-fifos = <16>;
692 interrupt-parent = <&intr_main_navss>;
693 status = "disabled";
694 };
695
696 mailbox0_cluster4: mailbox@31f84000 {
697 compatible = "ti,am654-mailbox";
698 reg = <0x00 0x31f84000 0x00 0x200>;
699 #mbox-cells = <1>;
700 ti,mbox-num-users = <4>;
701 ti,mbox-num-fifos = <16>;
702 interrupt-parent = <&intr_main_navss>;
703 status = "disabled";
704 };
705
706 mailbox0_cluster5: mailbox@31f85000 {
707 compatible = "ti,am654-mailbox";
708 reg = <0x00 0x31f85000 0x00 0x200>;
709 #mbox-cells = <1>;
710 ti,mbox-num-users = <4>;
711 ti,mbox-num-fifos = <16>;
712 interrupt-parent = <&intr_main_navss>;
713 status = "disabled";
714 };
715
716 mailbox0_cluster6: mailbox@31f86000 {
717 compatible = "ti,am654-mailbox";
718 reg = <0x00 0x31f86000 0x00 0x200>;
719 #mbox-cells = <1>;
720 ti,mbox-num-users = <4>;
721 ti,mbox-num-fifos = <16>;
722 interrupt-parent = <&intr_main_navss>;
723 status = "disabled";
724 };
725
726 mailbox0_cluster7: mailbox@31f87000 {
727 compatible = "ti,am654-mailbox";
728 reg = <0x00 0x31f87000 0x00 0x200>;
729 #mbox-cells = <1>;
730 ti,mbox-num-users = <4>;
731 ti,mbox-num-fifos = <16>;
732 interrupt-parent = <&intr_main_navss>;
733 status = "disabled";
734 };
735
736 mailbox0_cluster8: mailbox@31f88000 {
737 compatible = "ti,am654-mailbox";
738 reg = <0x00 0x31f88000 0x00 0x200>;
739 #mbox-cells = <1>;
740 ti,mbox-num-users = <4>;
741 ti,mbox-num-fifos = <16>;
742 interrupt-parent = <&intr_main_navss>;
743 status = "disabled";
744 };
745
746 mailbox0_cluster9: mailbox@31f89000 {
747 compatible = "ti,am654-mailbox";
748 reg = <0x00 0x31f89000 0x00 0x200>;
749 #mbox-cells = <1>;
750 ti,mbox-num-users = <4>;
751 ti,mbox-num-fifos = <16>;
752 interrupt-parent = <&intr_main_navss>;
753 status = "disabled";
754 };
755
756 mailbox0_cluster10: mailbox@31f8a000 {
757 compatible = "ti,am654-mailbox";
758 reg = <0x00 0x31f8a000 0x00 0x200>;
759 #mbox-cells = <1>;
760 ti,mbox-num-users = <4>;
761 ti,mbox-num-fifos = <16>;
762 interrupt-parent = <&intr_main_navss>;
763 status = "disabled";
764 };
765
766 mailbox0_cluster11: mailbox@31f8b000 {
767 compatible = "ti,am654-mailbox";
768 reg = <0x00 0x31f8b000 0x00 0x200>;
769 #mbox-cells = <1>;
770 ti,mbox-num-users = <4>;
771 ti,mbox-num-fifos = <16>;
772 interrupt-parent = <&intr_main_navss>;
773 status = "disabled";
774 };
775
776 ringacc: ringacc@3c000000 {
777 compatible = "ti,am654-navss-ringacc";
778 reg = <0x0 0x3c000000 0x0 0x400000>,
779 <0x0 0x38000000 0x0 0x400000>,
780 <0x0 0x31120000 0x0 0x100>,
781 <0x0 0x33000000 0x0 0x40000>,
782 <0x0 0x31080000 0x0 0x40000>;
783 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
784 ti,num-rings = <818>;
785 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
786 ti,sci = <&dmsc>;
787 ti,sci-dev-id = <187>;
788 msi-parent = <&inta_main_udmass>;
789 };
790
791 main_udmap: dma-controller@31150000 {
792 compatible = "ti,am654-navss-main-udmap";
793 reg = <0x0 0x31150000 0x0 0x100>,
794 <0x0 0x34000000 0x0 0x100000>,
795 <0x0 0x35000000 0x0 0x100000>,
796 <0x0 0x30b00000 0x0 0x10000>,
797 <0x0 0x30c00000 0x0 0x10000>,
798 <0x0 0x30d00000 0x0 0x8000>;
799 reg-names = "gcfg", "rchanrt", "tchanrt",
800 "tchan", "rchan", "rflow";
801 msi-parent = <&inta_main_udmass>;
802 #dma-cells = <1>;
803
804 ti,sci = <&dmsc>;
805 ti,sci-dev-id = <188>;
806 ti,ringacc = <&ringacc>;
807
808 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
809 <0xd>; /* TX_CHAN */
810 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
811 <0xa>; /* RX_CHAN */
812 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
813 };
814
815 cpts@310d0000 {
816 compatible = "ti,am65-cpts";
817 reg = <0x0 0x310d0000 0x0 0x400>;
818 reg-names = "cpts";
819 clocks = <&main_cpts_mux>;
820 clock-names = "cpts";
821 interrupts-extended = <&intr_main_navss 391>;
822 interrupt-names = "cpts";
823 ti,cpts-periodic-outputs = <6>;
824 ti,cpts-ext-ts-inputs = <8>;
825
826 main_cpts_mux: refclk-mux {
827 #clock-cells = <0>;
828 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
829 <&k3_clks 118 6>, <&k3_clks 118 3>,
830 <&k3_clks 118 8>, <&k3_clks 118 14>,
831 <&k3_clks 120 3>, <&k3_clks 121 3>;
832 assigned-clocks = <&main_cpts_mux>;
833 assigned-clock-parents = <&k3_clks 118 5>;
834 };
835 };
836 };
837
838 main_gpio0: gpio@600000 {
839 compatible = "ti,am654-gpio", "ti,keystone-gpio";
840 reg = <0x0 0x600000 0x0 0x100>;
841 gpio-controller;
842 #gpio-cells = <2>;
843 interrupt-parent = <&intr_main_gpio>;
844 interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
845 interrupt-controller;
846 #interrupt-cells = <2>;
847 ti,ngpio = <96>;
848 ti,davinci-gpio-unbanked = <0>;
849 clocks = <&k3_clks 57 0>;
850 clock-names = "gpio";
851 };
852
853 main_gpio1: gpio@601000 {
854 compatible = "ti,am654-gpio", "ti,keystone-gpio";
855 reg = <0x0 0x601000 0x0 0x100>;
856 gpio-controller;
857 #gpio-cells = <2>;
858 interrupt-parent = <&intr_main_gpio>;
859 interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
860 interrupt-controller;
861 #interrupt-cells = <2>;
862 ti,ngpio = <90>;
863 ti,davinci-gpio-unbanked = <0>;
864 clocks = <&k3_clks 58 0>;
865 clock-names = "gpio";
866 };
867
868 pcie0_rc: pcie@5500000 {
869 compatible = "ti,am654-pcie-rc";
870 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
871 reg-names = "app", "dbics", "config", "atu";
872 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
873 #address-cells = <3>;
874 #size-cells = <2>;
875 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
876 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
877 ti,syscon-pcie-id = <&scm_conf 0x210>;
878 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
879 bus-range = <0x0 0xff>;
880 num-viewport = <16>;
881 max-link-speed = <2>;
882 dma-coherent;
883 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
884 msi-map = <0x0 &gic_its 0x0 0x10000>;
885 device_type = "pci";
886 status = "disabled";
887 };
888
889 pcie1_rc: pcie@5600000 {
890 compatible = "ti,am654-pcie-rc";
891 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
892 reg-names = "app", "dbics", "config", "atu";
893 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
894 #address-cells = <3>;
895 #size-cells = <2>;
896 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
897 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
898 ti,syscon-pcie-id = <&scm_conf 0x210>;
899 ti,syscon-pcie-mode = <&scm_conf 0x4070>;
900 bus-range = <0x0 0xff>;
901 num-viewport = <16>;
902 max-link-speed = <2>;
903 dma-coherent;
904 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
905 msi-map = <0x0 &gic_its 0x10000 0x10000>;
906 device_type = "pci";
907 status = "disabled";
908 };
909
910 mcasp0: mcasp@2b00000 {
911 compatible = "ti,am33xx-mcasp-audio";
912 reg = <0x0 0x02b00000 0x0 0x2000>,
913 <0x0 0x02b08000 0x0 0x1000>;
914 reg-names = "mpu","dat";
915 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
917 interrupt-names = "tx", "rx";
918
919 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
920 dma-names = "tx", "rx";
921
922 clocks = <&k3_clks 104 0>;
923 clock-names = "fck";
924 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
925 status = "disabled";
926 };
927
928 mcasp1: mcasp@2b10000 {
929 compatible = "ti,am33xx-mcasp-audio";
930 reg = <0x0 0x02b10000 0x0 0x2000>,
931 <0x0 0x02b18000 0x0 0x1000>;
932 reg-names = "mpu","dat";
933 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
935 interrupt-names = "tx", "rx";
936
937 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
938 dma-names = "tx", "rx";
939
940 clocks = <&k3_clks 105 0>;
941 clock-names = "fck";
942 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
943 status = "disabled";
944 };
945
946 mcasp2: mcasp@2b20000 {
947 compatible = "ti,am33xx-mcasp-audio";
948 reg = <0x0 0x02b20000 0x0 0x2000>,
949 <0x0 0x02b28000 0x0 0x1000>;
950 reg-names = "mpu","dat";
951 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
953 interrupt-names = "tx", "rx";
954
955 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
956 dma-names = "tx", "rx";
957
958 clocks = <&k3_clks 106 0>;
959 clock-names = "fck";
960 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
961 status = "disabled";
962 };
963
964 cal: cal@6f03000 {
965 compatible = "ti,am654-cal";
966 reg = <0x0 0x06f03000 0x0 0x400>,
967 <0x0 0x06f03800 0x0 0x40>;
968 reg-names = "cal_top",
969 "cal_rx_core0";
970 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
971 ti,camerrx-control = <&scm_conf 0x40c0>;
972 clock-names = "fck";
973 clocks = <&k3_clks 2 0>;
974 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
975
976 ports {
977 #address-cells = <1>;
978 #size-cells = <0>;
979
980 csi2_0: port@0 {
981 reg = <0>;
982 };
983 };
984 };
985
986 dss: dss@4a00000 {
987 compatible = "ti,am65x-dss";
988 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
989 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
990 <0x0 0x04a06000 0x0 0x1000>, /* vid */
991 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
992 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
993 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
994 <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */
995 <0x0 0x04a01000 0x0 0x1000>; /* common1 */
996 reg-names = "common", "vidl1", "vid",
997 "ovr1", "ovr2", "vp1", "vp2", "common1";
998
999 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
1000
1001 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1002
1003 clocks = <&k3_clks 67 1>,
1004 <&k3_clks 216 1>,
1005 <&k3_clks 67 2>;
1006 clock-names = "fck", "vp1", "vp2";
1007
1008 /*
1009 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
1010 * DIV1. See "Figure 12-3365. DSS Integration"
1011 * in AM65x TRM for details.
1012 */
1013 assigned-clocks = <&k3_clks 67 2>;
1014 assigned-clock-parents = <&k3_clks 67 5>;
1015
1016 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1017
1018 dma-coherent;
1019
1020 dss_ports: ports {
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023 };
1024 };
1025
1026 gpu: gpu@7000000 {
1027 compatible = "ti,am6548-gpu", "img,powervr-sgx544";
1028 reg = <0x0 0x7000000 0x0 0x10000>;
1029 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1030 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1031 };
1032
1033 ehrpwm0: pwm@3000000 {
1034 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1035 #pwm-cells = <3>;
1036 reg = <0x0 0x3000000 0x0 0x100>;
1037 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
1038 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
1039 clock-names = "tbclk", "fck";
1040 status = "disabled";
1041 };
1042
1043 ehrpwm1: pwm@3010000 {
1044 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1045 #pwm-cells = <3>;
1046 reg = <0x0 0x3010000 0x0 0x100>;
1047 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
1048 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
1049 clock-names = "tbclk", "fck";
1050 status = "disabled";
1051 };
1052
1053 ehrpwm2: pwm@3020000 {
1054 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1055 #pwm-cells = <3>;
1056 reg = <0x0 0x3020000 0x0 0x100>;
1057 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
1058 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
1059 clock-names = "tbclk", "fck";
1060 status = "disabled";
1061 };
1062
1063 ehrpwm3: pwm@3030000 {
1064 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1065 #pwm-cells = <3>;
1066 reg = <0x0 0x3030000 0x0 0x100>;
1067 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
1068 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
1069 clock-names = "tbclk", "fck";
1070 status = "disabled";
1071 };
1072
1073 ehrpwm4: pwm@3040000 {
1074 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1075 #pwm-cells = <3>;
1076 reg = <0x0 0x3040000 0x0 0x100>;
1077 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
1078 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
1079 clock-names = "tbclk", "fck";
1080 status = "disabled";
1081 };
1082
1083 ehrpwm5: pwm@3050000 {
1084 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
1085 #pwm-cells = <3>;
1086 reg = <0x0 0x3050000 0x0 0x100>;
1087 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
1088 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
1089 clock-names = "tbclk", "fck";
1090 status = "disabled";
1091 };
1092
1093 icssg0: icssg@b000000 {
1094 compatible = "ti,am654-icssg";
1095 reg = <0x00 0xb000000 0x00 0x80000>;
1096 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1097 #address-cells = <1>;
1098 #size-cells = <1>;
1099 ranges = <0x0 0x00 0xb000000 0x80000>;
1100
1101 icssg0_mem: memories@0 {
1102 reg = <0x0 0x2000>,
1103 <0x2000 0x2000>,
1104 <0x10000 0x10000>;
1105 reg-names = "dram0", "dram1",
1106 "shrdram2";
1107 };
1108
1109 icssg0_cfg: cfg@26000 {
1110 compatible = "ti,pruss-cfg", "syscon";
1111 reg = <0x26000 0x200>;
1112 #address-cells = <1>;
1113 #size-cells = <1>;
1114 ranges = <0x0 0x26000 0x2000>;
1115
1116 clocks {
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1119
1120 icssg0_coreclk_mux: coreclk-mux@3c {
1121 reg = <0x3c>;
1122 #clock-cells = <0>;
1123 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */
1124 <&k3_clks 62 3>; /* icssg0_iclk */
1125 assigned-clocks = <&icssg0_coreclk_mux>;
1126 assigned-clock-parents = <&k3_clks 62 3>;
1127 };
1128
1129 icssg0_iepclk_mux: iepclk-mux@30 {
1130 reg = <0x30>;
1131 #clock-cells = <0>;
1132 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */
1133 <&icssg0_coreclk_mux>; /* core_clk */
1134 assigned-clocks = <&icssg0_iepclk_mux>;
1135 assigned-clock-parents = <&icssg0_coreclk_mux>;
1136 };
1137 };
1138 };
1139
1140 icssg0_iep0: iep@2e000 {
1141 compatible = "ti,am654-icss-iep";
1142 reg = <0x2e000 0x1000>;
1143 clocks = <&icssg0_iepclk_mux>;
1144 };
1145
1146 icssg0_iep1: iep@2f000 {
1147 compatible = "ti,am654-icss-iep";
1148 reg = <0x2f000 0x1000>;
1149 clocks = <&icssg0_iepclk_mux>;
1150 };
1151
1152 icssg0_mii_rt: mii-rt@32000 {
1153 compatible = "ti,pruss-mii", "syscon";
1154 reg = <0x32000 0x100>;
1155 };
1156
1157 icssg0_mii_g_rt: mii-g-rt@33000 {
1158 compatible = "ti,pruss-mii-g", "syscon";
1159 reg = <0x33000 0x1000>;
1160 };
1161
1162 icssg0_intc: interrupt-controller@20000 {
1163 compatible = "ti,icssg-intc";
1164 reg = <0x20000 0x2000>;
1165 interrupt-controller;
1166 #interrupt-cells = <3>;
1167 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1175 interrupt-names = "host_intr0", "host_intr1",
1176 "host_intr2", "host_intr3",
1177 "host_intr4", "host_intr5",
1178 "host_intr6", "host_intr7";
1179 };
1180
1181 pru0_0: pru@34000 {
1182 compatible = "ti,am654-pru";
1183 reg = <0x34000 0x4000>,
1184 <0x22000 0x100>,
1185 <0x22400 0x100>;
1186 reg-names = "iram", "control", "debug";
1187 firmware-name = "am65x-pru0_0-fw";
1188 interrupt-parent = <&icssg0_intc>;
1189 interrupts = <16 2 2>;
1190 interrupt-names = "vring";
1191 };
1192
1193 rtu0_0: rtu@4000 {
1194 compatible = "ti,am654-rtu";
1195 reg = <0x4000 0x2000>,
1196 <0x23000 0x100>,
1197 <0x23400 0x100>;
1198 reg-names = "iram", "control", "debug";
1199 firmware-name = "am65x-rtu0_0-fw";
1200 interrupt-parent = <&icssg0_intc>;
1201 interrupts = <20 4 4>;
1202 interrupt-names = "vring";
1203 };
1204
1205 tx_pru0_0: txpru@a000 {
1206 compatible = "ti,am654-tx-pru";
1207 reg = <0xa000 0x1800>,
1208 <0x25000 0x100>,
1209 <0x25400 0x100>;
1210 reg-names = "iram", "control", "debug";
1211 firmware-name = "am65x-txpru0_0-fw";
1212 };
1213
1214 pru0_1: pru@38000 {
1215 compatible = "ti,am654-pru";
1216 reg = <0x38000 0x4000>,
1217 <0x24000 0x100>,
1218 <0x24400 0x100>;
1219 reg-names = "iram", "control", "debug";
1220 firmware-name = "am65x-pru0_1-fw";
1221 interrupt-parent = <&icssg0_intc>;
1222 interrupts = <18 3 3>;
1223 interrupt-names = "vring";
1224 };
1225
1226 rtu0_1: rtu@6000 {
1227 compatible = "ti,am654-rtu";
1228 reg = <0x6000 0x2000>,
1229 <0x23800 0x100>,
1230 <0x23c00 0x100>;
1231 reg-names = "iram", "control", "debug";
1232 firmware-name = "am65x-rtu0_1-fw";
1233 interrupt-parent = <&icssg0_intc>;
1234 interrupts = <22 5 5>;
1235 interrupt-names = "vring";
1236 };
1237
1238 tx_pru0_1: txpru@c000 {
1239 compatible = "ti,am654-tx-pru";
1240 reg = <0xc000 0x1800>,
1241 <0x25800 0x100>,
1242 <0x25c00 0x100>;
1243 reg-names = "iram", "control", "debug";
1244 firmware-name = "am65x-txpru0_1-fw";
1245 };
1246
1247 icssg0_mdio: mdio@32400 {
1248 compatible = "ti,davinci_mdio";
1249 reg = <0x32400 0x100>;
1250 clocks = <&k3_clks 62 3>;
1251 clock-names = "fck";
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254 bus_freq = <1000000>;
1255 status = "disabled";
1256 };
1257 };
1258
1259 icssg1: icssg@b100000 {
1260 compatible = "ti,am654-icssg";
1261 reg = <0x00 0xb100000 0x00 0x80000>;
1262 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1263 #address-cells = <1>;
1264 #size-cells = <1>;
1265 ranges = <0x0 0x00 0xb100000 0x80000>;
1266
1267 icssg1_mem: memories@0 {
1268 reg = <0x0 0x2000>,
1269 <0x2000 0x2000>,
1270 <0x10000 0x10000>;
1271 reg-names = "dram0", "dram1",
1272 "shrdram2";
1273 };
1274
1275 icssg1_cfg: cfg@26000 {
1276 compatible = "ti,pruss-cfg", "syscon";
1277 reg = <0x26000 0x200>;
1278 #address-cells = <1>;
1279 #size-cells = <1>;
1280 ranges = <0x0 0x26000 0x2000>;
1281
1282 clocks {
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1285
1286 icssg1_coreclk_mux: coreclk-mux@3c {
1287 reg = <0x3c>;
1288 #clock-cells = <0>;
1289 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */
1290 <&k3_clks 63 3>; /* icssg1_iclk */
1291 assigned-clocks = <&icssg1_coreclk_mux>;
1292 assigned-clock-parents = <&k3_clks 63 3>;
1293 };
1294
1295 icssg1_iepclk_mux: iepclk-mux@30 {
1296 reg = <0x30>;
1297 #clock-cells = <0>;
1298 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */
1299 <&icssg1_coreclk_mux>; /* core_clk */
1300 assigned-clocks = <&icssg1_iepclk_mux>;
1301 assigned-clock-parents = <&icssg1_coreclk_mux>;
1302 };
1303 };
1304 };
1305
1306 icssg1_iep0: iep@2e000 {
1307 compatible = "ti,am654-icss-iep";
1308 reg = <0x2e000 0x1000>;
1309 clocks = <&icssg1_iepclk_mux>;
1310 };
1311
1312 icssg1_iep1: iep@2f000 {
1313 compatible = "ti,am654-icss-iep";
1314 reg = <0x2f000 0x1000>;
1315 clocks = <&icssg1_iepclk_mux>;
1316 };
1317
1318 icssg1_mii_rt: mii-rt@32000 {
1319 compatible = "ti,pruss-mii", "syscon";
1320 reg = <0x32000 0x100>;
1321 };
1322
1323 icssg1_mii_g_rt: mii-g-rt@33000 {
1324 compatible = "ti,pruss-mii-g", "syscon";
1325 reg = <0x33000 0x1000>;
1326 };
1327
1328 icssg1_intc: interrupt-controller@20000 {
1329 compatible = "ti,icssg-intc";
1330 reg = <0x20000 0x2000>;
1331 interrupt-controller;
1332 #interrupt-cells = <3>;
1333 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1341 interrupt-names = "host_intr0", "host_intr1",
1342 "host_intr2", "host_intr3",
1343 "host_intr4", "host_intr5",
1344 "host_intr6", "host_intr7";
1345 };
1346
1347 pru1_0: pru@34000 {
1348 compatible = "ti,am654-pru";
1349 reg = <0x34000 0x4000>,
1350 <0x22000 0x100>,
1351 <0x22400 0x100>;
1352 reg-names = "iram", "control", "debug";
1353 firmware-name = "am65x-pru1_0-fw";
1354 interrupt-parent = <&icssg1_intc>;
1355 interrupts = <16 2 2>;
1356 interrupt-names = "vring";
1357 };
1358
1359 rtu1_0: rtu@4000 {
1360 compatible = "ti,am654-rtu";
1361 reg = <0x4000 0x2000>,
1362 <0x23000 0x100>,
1363 <0x23400 0x100>;
1364 reg-names = "iram", "control", "debug";
1365 firmware-name = "am65x-rtu1_0-fw";
1366 interrupt-parent = <&icssg1_intc>;
1367 interrupts = <20 4 4>;
1368 interrupt-names = "vring";
1369 };
1370
1371 tx_pru1_0: txpru@a000 {
1372 compatible = "ti,am654-tx-pru";
1373 reg = <0xa000 0x1800>,
1374 <0x25000 0x100>,
1375 <0x25400 0x100>;
1376 reg-names = "iram", "control", "debug";
1377 firmware-name = "am65x-txpru1_0-fw";
1378 };
1379
1380 pru1_1: pru@38000 {
1381 compatible = "ti,am654-pru";
1382 reg = <0x38000 0x4000>,
1383 <0x24000 0x100>,
1384 <0x24400 0x100>;
1385 reg-names = "iram", "control", "debug";
1386 firmware-name = "am65x-pru1_1-fw";
1387 interrupt-parent = <&icssg1_intc>;
1388 interrupts = <18 3 3>;
1389 interrupt-names = "vring";
1390 };
1391
1392 rtu1_1: rtu@6000 {
1393 compatible = "ti,am654-rtu";
1394 reg = <0x6000 0x2000>,
1395 <0x23800 0x100>,
1396 <0x23c00 0x100>;
1397 reg-names = "iram", "control", "debug";
1398 firmware-name = "am65x-rtu1_1-fw";
1399 interrupt-parent = <&icssg1_intc>;
1400 interrupts = <22 5 5>;
1401 interrupt-names = "vring";
1402 };
1403
1404 tx_pru1_1: txpru@c000 {
1405 compatible = "ti,am654-tx-pru";
1406 reg = <0xc000 0x1800>,
1407 <0x25800 0x100>,
1408 <0x25c00 0x100>;
1409 reg-names = "iram", "control", "debug";
1410 firmware-name = "am65x-txpru1_1-fw";
1411 };
1412
1413 icssg1_mdio: mdio@32400 {
1414 compatible = "ti,davinci_mdio";
1415 reg = <0x32400 0x100>;
1416 clocks = <&k3_clks 63 3>;
1417 clock-names = "fck";
1418 #address-cells = <1>;
1419 #size-cells = <0>;
1420 bus_freq = <1000000>;
1421 status = "disabled";
1422 };
1423 };
1424
1425 icssg2: icssg@b200000 {
1426 compatible = "ti,am654-icssg";
1427 reg = <0x00 0xb200000 0x00 0x80000>;
1428 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1429 #address-cells = <1>;
1430 #size-cells = <1>;
1431 ranges = <0x0 0x00 0xb200000 0x80000>;
1432
1433 icssg2_mem: memories@0 {
1434 reg = <0x0 0x2000>,
1435 <0x2000 0x2000>,
1436 <0x10000 0x10000>;
1437 reg-names = "dram0", "dram1",
1438 "shrdram2";
1439 };
1440
1441 icssg2_cfg: cfg@26000 {
1442 compatible = "ti,pruss-cfg", "syscon";
1443 reg = <0x26000 0x200>;
1444 #address-cells = <1>;
1445 #size-cells = <1>;
1446 ranges = <0x0 0x26000 0x2000>;
1447
1448 clocks {
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1451
1452 icssg2_coreclk_mux: coreclk-mux@3c {
1453 reg = <0x3c>;
1454 #clock-cells = <0>;
1455 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */
1456 <&k3_clks 64 3>; /* icssg1_iclk */
1457 assigned-clocks = <&icssg2_coreclk_mux>;
1458 assigned-clock-parents = <&k3_clks 64 3>;
1459 };
1460
1461 icssg2_iepclk_mux: iepclk-mux@30 {
1462 reg = <0x30>;
1463 #clock-cells = <0>;
1464 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */
1465 <&icssg2_coreclk_mux>; /* core_clk */
1466 assigned-clocks = <&icssg2_iepclk_mux>;
1467 assigned-clock-parents = <&icssg2_coreclk_mux>;
1468 };
1469 };
1470 };
1471
1472 icssg2_iep0: iep@2e000 {
1473 compatible = "ti,am654-icss-iep";
1474 reg = <0x2e000 0x1000>;
1475 clocks = <&icssg2_iepclk_mux>;
1476 };
1477
1478 icssg2_iep1: iep@2f000 {
1479 compatible = "ti,am654-icss-iep";
1480 reg = <0x2f000 0x1000>;
1481 clocks = <&icssg2_iepclk_mux>;
1482 };
1483
1484 icssg2_mii_rt: mii-rt@32000 {
1485 compatible = "ti,pruss-mii", "syscon";
1486 reg = <0x32000 0x100>;
1487 };
1488
1489 icssg2_mii_g_rt: mii-g-rt@33000 {
1490 compatible = "ti,pruss-mii-g", "syscon";
1491 reg = <0x33000 0x1000>;
1492 };
1493
1494 icssg2_intc: interrupt-controller@20000 {
1495 compatible = "ti,icssg-intc";
1496 reg = <0x20000 0x2000>;
1497 interrupt-controller;
1498 #interrupt-cells = <3>;
1499 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
1500 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
1501 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
1502 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
1503 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
1504 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
1505 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
1506 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
1507 interrupt-names = "host_intr0", "host_intr1",
1508 "host_intr2", "host_intr3",
1509 "host_intr4", "host_intr5",
1510 "host_intr6", "host_intr7";
1511 };
1512
1513 pru2_0: pru@34000 {
1514 compatible = "ti,am654-pru";
1515 reg = <0x34000 0x4000>,
1516 <0x22000 0x100>,
1517 <0x22400 0x100>;
1518 reg-names = "iram", "control", "debug";
1519 firmware-name = "am65x-pru2_0-fw";
1520 interrupt-parent = <&icssg2_intc>;
1521 interrupts = <16 2 2>;
1522 interrupt-names = "vring";
1523 };
1524
1525 rtu2_0: rtu@4000 {
1526 compatible = "ti,am654-rtu";
1527 reg = <0x4000 0x2000>,
1528 <0x23000 0x100>,
1529 <0x23400 0x100>;
1530 reg-names = "iram", "control", "debug";
1531 firmware-name = "am65x-rtu2_0-fw";
1532 interrupt-parent = <&icssg2_intc>;
1533 interrupts = <20 4 4>;
1534 interrupt-names = "vring";
1535 };
1536
1537 tx_pru2_0: txpru@a000 {
1538 compatible = "ti,am654-tx-pru";
1539 reg = <0xa000 0x1800>,
1540 <0x25000 0x100>,
1541 <0x25400 0x100>;
1542 reg-names = "iram", "control", "debug";
1543 firmware-name = "am65x-txpru2_0-fw";
1544 };
1545
1546 pru2_1: pru@38000 {
1547 compatible = "ti,am654-pru";
1548 reg = <0x38000 0x4000>,
1549 <0x24000 0x100>,
1550 <0x24400 0x100>;
1551 reg-names = "iram", "control", "debug";
1552 firmware-name = "am65x-pru2_1-fw";
1553 interrupt-parent = <&icssg2_intc>;
1554 interrupts = <18 3 3>;
1555 interrupt-names = "vring";
1556 };
1557
1558 rtu2_1: rtu@6000 {
1559 compatible = "ti,am654-rtu";
1560 reg = <0x6000 0x2000>,
1561 <0x23800 0x100>,
1562 <0x23c00 0x100>;
1563 reg-names = "iram", "control", "debug";
1564 firmware-name = "am65x-rtu2_1-fw";
1565 interrupt-parent = <&icssg2_intc>;
1566 interrupts = <22 5 5>;
1567 interrupt-names = "vring";
1568 };
1569
1570 tx_pru2_1: txpru@c000 {
1571 compatible = "ti,am654-tx-pru";
1572 reg = <0xc000 0x1800>,
1573 <0x25800 0x100>,
1574 <0x25c00 0x100>;
1575 reg-names = "iram", "control", "debug";
1576 firmware-name = "am65x-txpru2_1-fw";
1577 };
1578
1579 icssg2_mdio: mdio@32400 {
1580 compatible = "ti,davinci_mdio";
1581 reg = <0x32400 0x100>;
1582 clocks = <&k3_clks 64 3>;
1583 clock-names = "fck";
1584 #address-cells = <1>;
1585 #size-cells = <0>;
1586 bus_freq = <1000000>;
1587 status = "disabled";
1588 };
1589 };
1590 };
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