1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6 /dts-v1/;
7
8 #include "k3-j721s2.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10
11 / {
12 memory@80000000 {
13 device_type = "memory";
14 bootph-all;
15 /* 16 GB RAM */
16 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
17 <0x00000008 0x80000000 0x00000003 0x80000000>;
18 };
19
20 reserved_memory: reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
23 ranges;
24
25 secure_ddr: optee@9e800000 {
26 reg = <0x00 0x9e800000 0x00 0x01800000>;
27 no-map;
28 };
29
30 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
31 compatible = "shared-dma-pool";
32 reg = <0x00 0xa0000000 0x00 0x100000>;
33 no-map;
34 };
35
36 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
37 compatible = "shared-dma-pool";
38 reg = <0x00 0xa0100000 0x00 0xf00000>;
39 no-map;
40 };
41
42 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
43 compatible = "shared-dma-pool";
44 reg = <0x00 0xa1000000 0x00 0x100000>;
45 no-map;
46 };
47
48 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
49 compatible = "shared-dma-pool";
50 reg = <0x00 0xa1100000 0x00 0xf00000>;
51 no-map;
52 };
53
54 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
55 compatible = "shared-dma-pool";
56 reg = <0x00 0xa2000000 0x00 0x100000>;
57 no-map;
58 };
59
60 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
61 compatible = "shared-dma-pool";
62 reg = <0x00 0xa2100000 0x00 0xf00000>;
63 no-map;
64 };
65
66 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
67 compatible = "shared-dma-pool";
68 reg = <0x00 0xa3000000 0x00 0x100000>;
69 no-map;
70 };
71
72 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
73 compatible = "shared-dma-pool";
74 reg = <0x00 0xa3100000 0x00 0xf00000>;
75 no-map;
76 };
77
78 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
79 compatible = "shared-dma-pool";
80 reg = <0x00 0xa4000000 0x00 0x100000>;
81 no-map;
82 };
83
84 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
85 compatible = "shared-dma-pool";
86 reg = <0x00 0xa4100000 0x00 0xf00000>;
87 no-map;
88 };
89
90 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
91 compatible = "shared-dma-pool";
92 reg = <0x00 0xa5000000 0x00 0x100000>;
93 no-map;
94 };
95
96 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
97 compatible = "shared-dma-pool";
98 reg = <0x00 0xa5100000 0x00 0xf00000>;
99 no-map;
100 };
101
102 c71_0_dma_memory_region: c71-dma-memory@a6000000 {
103 compatible = "shared-dma-pool";
104 reg = <0x00 0xa6000000 0x00 0x100000>;
105 no-map;
106 };
107
108 c71_0_memory_region: c71-memory@a6100000 {
109 compatible = "shared-dma-pool";
110 reg = <0x00 0xa6100000 0x00 0xf00000>;
111 no-map;
112 };
113
114 c71_1_dma_memory_region: c71-dma-memory@a7000000 {
115 compatible = "shared-dma-pool";
116 reg = <0x00 0xa7000000 0x00 0x100000>;
117 no-map;
118 };
119
120 c71_1_memory_region: c71-memory@a7100000 {
121 compatible = "shared-dma-pool";
122 reg = <0x00 0xa7100000 0x00 0xf00000>;
123 no-map;
124 };
125
126 rtos_ipc_memory_region: ipc-memories@a8000000 {
127 reg = <0x00 0xa8000000 0x00 0x01c00000>;
128 alignment = <0x1000>;
129 no-map;
130 };
131 };
132 };
133
134 &wkup_pmx0 {
135 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins {
136 bootph-all;
137 pinctrl-single,pins = <
138 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
139 J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
140 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
141 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
142 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
143 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
144 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
145 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
146 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
147 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
148 J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
149 >;
150 };
151 };
152
153 &wkup_pmx2 {
154 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
155 pinctrl-single,pins = <
156 J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
157 J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
158 >;
159 };
160 };
161
162 &wkup_i2c0 {
163 status = "okay";
164 pinctrl-names = "default";
165 pinctrl-0 = <&wkup_i2c0_pins_default>;
166 clock-frequency = <400000>;
167
168 eeprom@51 {
169 /* AT24C512C-MAHM-T */
170 compatible = "atmel,24c512";
171 reg = <0x51>;
172 };
173 };
174
175 &ospi0 {
176 status = "okay";
177 pinctrl-names = "default";
178 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
179
180 flash@0 {
181 compatible = "jedec,spi-nor";
182 reg = <0x0>;
183 spi-tx-bus-width = <8>;
184 spi-rx-bus-width = <8>;
185 spi-max-frequency = <25000000>;
186 cdns,tshsl-ns = <60>;
187 cdns,tsd2d-ns = <60>;
188 cdns,tchsh-ns = <60>;
189 cdns,tslch-ns = <60>;
190 cdns,read-delay = <4>;
191
192 partitions {
193 bootph-all;
194 compatible = "fixed-partitions";
195 #address-cells = <1>;
196 #size-cells = <1>;
197
198 partition@0 {
199 label = "ospi.tiboot3";
200 reg = <0x0 0x80000>;
201 };
202
203 partition@80000 {
204 label = "ospi.tispl";
205 reg = <0x80000 0x200000>;
206 };
207
208 partition@280000 {
209 label = "ospi.u-boot";
210 reg = <0x280000 0x400000>;
211 };
212
213 partition@680000 {
214 label = "ospi.env";
215 reg = <0x680000 0x40000>;
216 };
217
218 partition@740000 {
219 label = "ospi.env.backup";
220 reg = <0x740000 0x40000>;
221 };
222
223 partition@800000 {
224 label = "ospi.rootfs";
225 reg = <0x800000 0x37c0000>;
226 };
227
228 partition@3fc0000 {
229 bootph-pre-ram;
230 label = "ospi.phypattern";
231 reg = <0x3fc0000 0x40000>;
232 };
233 };
234 };
235 };
236
237 &mailbox0_cluster0 {
238 status = "okay";
239 interrupts = <436>;
240 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
241 ti,mbox-rx = <0 0 0>;
242 ti,mbox-tx = <1 0 0>;
243 };
244
245 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
246 ti,mbox-rx = <2 0 0>;
247 ti,mbox-tx = <3 0 0>;
248 };
249 };
250
251 &mailbox0_cluster1 {
252 status = "okay";
253 interrupts = <432>;
254 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
255 ti,mbox-rx = <0 0 0>;
256 ti,mbox-tx = <1 0 0>;
257 };
258
259 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
260 ti,mbox-rx = <2 0 0>;
261 ti,mbox-tx = <3 0 0>;
262 };
263 };
264
265 &mailbox0_cluster2 {
266 status = "okay";
267 interrupts = <428>;
268 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
269 ti,mbox-rx = <0 0 0>;
270 ti,mbox-tx = <1 0 0>;
271 };
272
273 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
274 ti,mbox-rx = <2 0 0>;
275 ti,mbox-tx = <3 0 0>;
276 };
277 };
278
279 &mailbox0_cluster4 {
280 status = "okay";
281 interrupts = <420>;
282 mbox_c71_0: mbox-c71-0 {
283 ti,mbox-rx = <0 0 0>;
284 ti,mbox-tx = <1 0 0>;
285 };
286
287 mbox_c71_1: mbox-c71-1 {
288 ti,mbox-rx = <2 0 0>;
289 ti,mbox-tx = <3 0 0>;
290 };
291 };
292
293 &mcu_r5fss0_core0 {
294 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
295 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
296 <&mcu_r5fss0_core0_memory_region>;
297 };
298
299 &mcu_r5fss0_core1 {
300 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
301 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
302 <&mcu_r5fss0_core1_memory_region>;
303 };
304
305 &main_r5fss0_core0 {
306 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
307 memory-region = <&main_r5fss0_core0_dma_memory_region>,
308 <&main_r5fss0_core0_memory_region>;
309 };
310
311 &main_r5fss0_core1 {
312 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
313 memory-region = <&main_r5fss0_core1_dma_memory_region>,
314 <&main_r5fss0_core1_memory_region>;
315 };
316
317 &main_r5fss1_core0 {
318 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
319 memory-region = <&main_r5fss1_core0_dma_memory_region>,
320 <&main_r5fss1_core0_memory_region>;
321 };
322
323 &main_r5fss1_core1 {
324 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
325 memory-region = <&main_r5fss1_core1_dma_memory_region>,
326 <&main_r5fss1_core1_memory_region>;
327 };
328
329 &c71_0 {
330 status = "okay";
331 mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
332 memory-region = <&c71_0_dma_memory_region>,
333 <&c71_0_memory_region>;
334 };
335
336 &c71_1 {
337 status = "okay";
338 mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
339 memory-region = <&c71_1_dma_memory_region>,
340 <&c71_1_memory_region>;
341 };
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