1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6 /dts-v1/;
7
8 #include "k3-j7200-som-p0.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/phy/phy.h>
12
13 #include "k3-serdes.h"
14
15 / {
16 compatible = "ti,j7200-evm", "ti,j7200";
17 model = "Texas Instruments J7200 EVM";
18
19 aliases {
20 serial0 = &wkup_uart0;
21 serial1 = &mcu_uart0;
22 serial2 = &main_uart0;
23 serial3 = &main_uart1;
24 serial5 = &main_uart3;
25 mmc0 = &main_sdhci0;
26 mmc1 = &main_sdhci1;
27 };
28
29 chosen {
30 stdout-path = "serial2:115200n8";
31 };
32
33 evm_12v0: fixedregulator-evm12v0 {
34 /* main supply */
35 compatible = "regulator-fixed";
36 regulator-name = "evm_12v0";
37 regulator-min-microvolt = <12000000>;
38 regulator-max-microvolt = <12000000>;
39 regulator-always-on;
40 regulator-boot-on;
41 };
42
43 vsys_3v3: fixedregulator-vsys3v3 {
44 /* Output of LM5140 */
45 compatible = "regulator-fixed";
46 regulator-name = "vsys_3v3";
47 regulator-min-microvolt = <3300000>;
48 regulator-max-microvolt = <3300000>;
49 vin-supply = <&evm_12v0>;
50 regulator-always-on;
51 regulator-boot-on;
52 };
53
54 vsys_5v0: fixedregulator-vsys5v0 {
55 /* Output of LM5140 */
56 compatible = "regulator-fixed";
57 regulator-name = "vsys_5v0";
58 regulator-min-microvolt = <5000000>;
59 regulator-max-microvolt = <5000000>;
60 vin-supply = <&evm_12v0>;
61 regulator-always-on;
62 regulator-boot-on;
63 };
64
65 vdd_mmc1: fixedregulator-sd {
66 /* Output of TPS22918 */
67 compatible = "regulator-fixed";
68 regulator-name = "vdd_mmc1";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 regulator-boot-on;
72 enable-active-high;
73 vin-supply = <&vsys_3v3>;
74 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
75 };
76
77 vdd_sd_dv: gpio-regulator-TLV71033 {
78 /* Output of TLV71033 */
79 compatible = "regulator-gpio";
80 regulator-name = "tlv71033";
81 pinctrl-names = "default";
82 pinctrl-0 = <&vdd_sd_dv_pins_default>;
83 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <3300000>;
85 regulator-boot-on;
86 vin-supply = <&vsys_5v0>;
87 gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
88 states = <1800000 0x0>,
89 <3300000 0x1>;
90 };
91
92 transceiver1: can-phy1 {
93 compatible = "ti,tcan1043";
94 #phy-cells = <0>;
95 max-bitrate = <5000000>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
98 standby-gpios = <&wkup_gpio0 58 GPIO_ACTIVE_LOW>;
99 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
100 };
101
102 transceiver2: can-phy2 {
103 compatible = "ti,tcan1042";
104 #phy-cells = <0>;
105 max-bitrate = <5000000>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
108 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
109 };
110
111 transceiver3: can-phy3 {
112 compatible = "ti,tcan1043";
113 #phy-cells = <0>;
114 max-bitrate = <5000000>;
115 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
116 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
117 mux-states = <&mux0 1>;
118 };
119 };
120
121 &wkup_pmx0 {
122 };
123
124 &wkup_pmx2 {
125 mcu_uart0_pins_default: mcu-uart0-default-pins {
126 pinctrl-single,pins = <
127 J721E_WKUP_IOPAD(0x90, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */
128 J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */
129 J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
130 J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
131 >;
132 };
133
134 wkup_uart0_pins_default: wkup-uart0-default-pins {
135 pinctrl-single,pins = <
136 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
137 J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
138 >;
139 };
140
141 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
142 pinctrl-single,pins = <
143 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
144 J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
145 J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
146 J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
147 J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
148 J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
149 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
150 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
151 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
152 J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
153 J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
154 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
155 >;
156 };
157
158 wkup_gpio_pins_default: wkup-gpio-default-pins {
159 pinctrl-single,pins = <
160 J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
161 >;
162 };
163
164 mcu_mdio_pins_default: mcu-mdio1-default-pins {
165 pinctrl-single,pins = <
166 J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
167 J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
168 >;
169 };
170
171 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
172 pinctrl-single,pins = <
173 J721E_WKUP_IOPAD(0x54, PIN_INPUT, 0) /* (A17) MCU_MCAN0_RX */
174 J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (A16) MCU_MCAN0_TX */
175 >;
176 };
177
178 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
179 pinctrl-single,pins = <
180 J721E_WKUP_IOPAD(0x6c, PIN_INPUT, 0) /* (B16) WKUP_GPIO0_5.MCU_MCAN1_RX */
181 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (D13) WKUP_GPIO0_4.MCU_MCAN1_TX */
182 >;
183 };
184
185 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
186 pinctrl-single,pins = <
187 J721E_WKUP_IOPAD(0x58, PIN_INPUT, 7) /* (B18) WKUP_GPIO0_0 */
188 J721E_WKUP_IOPAD(0x40, PIN_INPUT, 7) /* (B17) MCU_SPI0_D1 */
189 >;
190 };
191
192 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
193 pinctrl-single,pins = <
194 J721E_WKUP_IOPAD(0x60, PIN_INPUT, 7) /* (D14) WKUP_GPIO0_2 */
195 >;
196 };
197 };
198
199 &main_pmx0 {
200 main_uart0_pins_default: main-uart0-default-pins {
201 pinctrl-single,pins = <
202 J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
203 J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
204 J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
205 J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
206 >;
207 };
208
209 main_uart1_pins_default: main-uart1-default-pins {
210 pinctrl-single,pins = <
211 J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */
212 J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */
213 >;
214 };
215
216 main_uart3_pins_default: main-uart3-default-pins {
217 pinctrl-single,pins = <
218 J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */
219 J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */
220 >;
221 };
222
223 main_i2c1_pins_default: main-i2c1-default-pins {
224 pinctrl-single,pins = <
225 J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
226 J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
227 >;
228 };
229
230 main_mmc1_pins_default: main-mmc1-default-pins {
231 pinctrl-single,pins = <
232 J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
233 J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
234 J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
235 J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
236 J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
237 J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
238 J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
239 J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
240 >;
241 };
242
243 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
244 pinctrl-single,pins = <
245 J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
246 >;
247 };
248
249 main_mcan3_pins_default: main-mcan3-default-pins {
250 pinctrl-single,pins = <
251 J721E_IOPAD(0x3c, PIN_INPUT, 0) /* (W16) MCAN3_RX */
252 J721E_IOPAD(0x38, PIN_OUTPUT, 0) /* (Y21) MCAN3_TX */
253 >;
254 };
255 };
256
257 &main_pmx1 {
258 main_usbss0_pins_default: main-usbss0-default-pins {
259 pinctrl-single,pins = <
260 J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
261 >;
262 };
263 };
264
265 &wkup_uart0 {
266 /* Wakeup UART is used by System firmware */
267 status = "reserved";
268 pinctrl-names = "default";
269 pinctrl-0 = <&wkup_uart0_pins_default>;
270 };
271
272 &mcu_uart0 {
273 status = "okay";
274 pinctrl-names = "default";
275 pinctrl-0 = <&mcu_uart0_pins_default>;
276 };
277
278 &main_uart0 {
279 status = "okay";
280 /* Shared with ATF on this platform */
281 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&main_uart0_pins_default>;
284 };
285
286 &main_uart1 {
287 status = "okay";
288 /* Default pinmux */
289 pinctrl-names = "default";
290 pinctrl-0 = <&main_uart1_pins_default>;
291 };
292
293 &main_uart2 {
294 /* MAIN UART 2 is used by R5F firmware */
295 status = "reserved";
296 };
297
298 &main_uart3 {
299 /* Shared with MCAN Interface */
300 status = "okay";
301 pinctrl-names = "default";
302 pinctrl-0 = <&main_uart3_pins_default>;
303 };
304
305 &main_gpio0 {
306 status = "okay";
307 };
308
309 &wkup_gpio0 {
310 status = "okay";
311 pinctrl-names = "default";
312 pinctrl-0 = <&wkup_gpio_pins_default>;
313 };
314
315 &mcu_cpsw {
316 pinctrl-names = "default";
317 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
318 };
319
320 &davinci_mdio {
321 phy0: ethernet-phy@0 {
322 reg = <0>;
323 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
324 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
325 };
326 };
327
328 &cpsw_port1 {
329 phy-mode = "rgmii-rxid";
330 phy-handle = <&phy0>;
331 };
332
333 &main_i2c0 {
334 status = "okay";
335 pinctrl-names = "default";
336 pinctrl-0 = <&main_i2c0_pins_default>;
337 clock-frequency = <400000>;
338
339 exp1: gpio@20 {
340 compatible = "ti,tca6416";
341 reg = <0x20>;
342 gpio-controller;
343 #gpio-cells = <2>;
344 };
345
346 exp2: gpio@22 {
347 compatible = "ti,tca6424";
348 reg = <0x22>;
349 gpio-controller;
350 #gpio-cells = <2>;
351 };
352 };
353
354 /*
355 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
356 * swapped on the CPB.
357 *
358 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
359 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
360 */
361 &main_i2c1 {
362 status = "okay";
363 pinctrl-names = "default";
364 pinctrl-0 = <&main_i2c1_pins_default>;
365 clock-frequency = <400000>;
366
367 exp3: gpio@20 {
368 compatible = "ti,tca6408";
369 reg = <0x20>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
373 "UB926_LOCK", "UB926_PWR_SW_CNTRL",
374 "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
375 };
376 };
377
378 &main_sdhci0 {
379 /* eMMC */
380 status = "okay";
381 non-removable;
382 ti,driver-strength-ohm = <50>;
383 disable-wp;
384 };
385
386 &main_sdhci1 {
387 /* SD card */
388 status = "okay";
389 pinctrl-0 = <&main_mmc1_pins_default>;
390 pinctrl-names = "default";
391 vmmc-supply = <&vdd_mmc1>;
392 vqmmc-supply = <&vdd_sd_dv>;
393 ti,driver-strength-ohm = <50>;
394 disable-wp;
395 };
396
397 &serdes_ln_ctrl {
398 idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
399 <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
400 };
401
402 &usb_serdes_mux {
403 idle-states = <1>; /* USB0 to SERDES lane 3 */
404 };
405
406 &usbss0 {
407 pinctrl-names = "default";
408 pinctrl-0 = <&main_usbss0_pins_default>;
409 ti,vbus-divider;
410 ti,usb2-only;
411 };
412
413 &usb0 {
414 dr_mode = "otg";
415 maximum-speed = "high-speed";
416 };
417
418 &tscadc0 {
419 adc {
420 ti,adc-channels = <0 1 2 3 4 5 6 7>;
421 };
422 };
423
424 &serdes_refclk {
425 clock-frequency = <100000000>;
426 };
427
428 &serdes0 {
429 serdes0_pcie_link: phy@0 {
430 reg = <0>;
431 cdns,num-lanes = <2>;
432 #phy-cells = <0>;
433 cdns,phy-type = <PHY_TYPE_PCIE>;
434 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
435 };
436
437 serdes0_qsgmii_link: phy@1 {
438 reg = <2>;
439 cdns,num-lanes = <1>;
440 #phy-cells = <0>;
441 cdns,phy-type = <PHY_TYPE_QSGMII>;
442 resets = <&serdes_wiz0 3>;
443 };
444 };
445
446 &pcie1_rc {
447 status = "okay";
448 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
449 phys = <&serdes0_pcie_link>;
450 phy-names = "pcie-phy";
451 num-lanes = <2>;
452 };
453
454 &mcu_mcan0 {
455 status = "okay";
456 pinctrl-names = "default";
457 pinctrl-0 = <&mcu_mcan0_pins_default>;
458 phys = <&transceiver1>;
459 };
460
461 &mcu_mcan1 {
462 status = "okay";
463 pinctrl-names = "default";
464 pinctrl-0 = <&mcu_mcan1_pins_default>;
465 phys = <&transceiver2>;
466 };
467
468 &main_mcan3 {
469 status = "okay";
470 pinctrl-names = "default";
471 pinctrl-0 = <&main_mcan3_pins_default>;
472 phys = <&transceiver3>;
473 };
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