1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
4 *
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8 &cbass_mcu_wakeup {
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
12
13 mbox-names = "rx", "tx";
14
15 mboxes = <&secure_proxy_main 11>,
16 <&secure_proxy_main 13>;
17
18 reg-names = "debug_messages";
19 reg = <0x00 0x44083000 0x00 0x1000>;
20
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
24 };
25
26 k3_clks: clock-controller {
27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
29 };
30
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
33 #reset-cells = <2>;
34 };
35 };
36
37 mcu_timer0: timer@40400000 {
38 status = "reserved";
39 compatible = "ti,am654-timer";
40 reg = <0x00 0x40400000 0x00 0x400>;
41 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
42 clocks = <&k3_clks 35 1>;
43 clock-names = "fck";
44 assigned-clocks = <&k3_clks 35 1>;
45 assigned-clock-parents = <&k3_clks 35 2>;
46 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
47 ti,timer-pwm;
48 };
49
50 mcu_timer1: timer@40410000 {
51 status = "reserved";
52 compatible = "ti,am654-timer";
53 reg = <0x00 0x40410000 0x00 0x400>;
54 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&k3_clks 71 1>;
56 clock-names = "fck";
57 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
58 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
59 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
60 ti,timer-pwm;
61 };
62
63 mcu_timer2: timer@40420000 {
64 status = "reserved";
65 compatible = "ti,am654-timer";
66 reg = <0x00 0x40420000 0x00 0x400>;
67 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&k3_clks 72 1>;
69 clock-names = "fck";
70 assigned-clocks = <&k3_clks 72 1>;
71 assigned-clock-parents = <&k3_clks 72 2>;
72 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
73 ti,timer-pwm;
74 };
75
76 mcu_timer3: timer@40430000 {
77 status = "reserved";
78 compatible = "ti,am654-timer";
79 reg = <0x00 0x40430000 0x00 0x400>;
80 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
81 clocks = <&k3_clks 73 1>;
82 clock-names = "fck";
83 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
84 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>;
85 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
86 ti,timer-pwm;
87 };
88
89 mcu_timer4: timer@40440000 {
90 status = "reserved";
91 compatible = "ti,am654-timer";
92 reg = <0x00 0x40440000 0x00 0x400>;
93 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&k3_clks 74 1>;
95 clock-names = "fck";
96 assigned-clocks = <&k3_clks 74 1>;
97 assigned-clock-parents = <&k3_clks 74 2>;
98 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
99 ti,timer-pwm;
100 };
101
102 mcu_timer5: timer@40450000 {
103 status = "reserved";
104 compatible = "ti,am654-timer";
105 reg = <0x00 0x40450000 0x00 0x400>;
106 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&k3_clks 75 1>;
108 clock-names = "fck";
109 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
110 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>;
111 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
112 ti,timer-pwm;
113 };
114
115 mcu_timer6: timer@40460000 {
116 status = "reserved";
117 compatible = "ti,am654-timer";
118 reg = <0x00 0x40460000 0x00 0x400>;
119 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&k3_clks 76 1>;
121 clock-names = "fck";
122 assigned-clocks = <&k3_clks 76 1>;
123 assigned-clock-parents = <&k3_clks 76 2>;
124 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
125 ti,timer-pwm;
126 };
127
128 mcu_timer7: timer@40470000 {
129 status = "reserved";
130 compatible = "ti,am654-timer";
131 reg = <0x00 0x40470000 0x00 0x400>;
132 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&k3_clks 77 1>;
134 clock-names = "fck";
135 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>;
136 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>;
137 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
138 ti,timer-pwm;
139 };
140
141 mcu_timer8: timer@40480000 {
142 status = "reserved";
143 compatible = "ti,am654-timer";
144 reg = <0x00 0x40480000 0x00 0x400>;
145 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&k3_clks 78 1>;
147 clock-names = "fck";
148 assigned-clocks = <&k3_clks 78 1>;
149 assigned-clock-parents = <&k3_clks 78 2>;
150 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
151 ti,timer-pwm;
152 };
153
154 mcu_timer9: timer@40490000 {
155 status = "reserved";
156 compatible = "ti,am654-timer";
157 reg = <0x00 0x40490000 0x00 0x400>;
158 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&k3_clks 79 1>;
160 clock-names = "fck";
161 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>;
162 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>;
163 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
164 ti,timer-pwm;
165 };
166
167 mcu_conf: bus@40f00000 {
168 compatible = "simple-bus";
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0x0 0x0 0x40f00000 0x20000>;
172
173 cpsw_mac_syscon: ethernet-mac-syscon@200 {
174 compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
175 reg = <0x200 0x8>;
176 };
177
178 phy_gmii_sel: phy@4040 {
179 compatible = "ti,am654-phy-gmii-sel";
180 reg = <0x4040 0x4>;
181 #phy-cells = <1>;
182 };
183 };
184
185 wkup_conf: bus@43000000 {
186 compatible = "simple-bus";
187 #address-cells = <1>;
188 #size-cells = <1>;
189 ranges = <0x0 0x00 0x43000000 0x20000>;
190
191 chipid: chipid@14 {
192 compatible = "ti,am654-chipid";
193 reg = <0x14 0x4>;
194 };
195 };
196
197 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
198 mcu_timerio_input: pinctrl@40f04200 {
199 compatible = "ti,j7200-padconf", "pinctrl-single";
200 reg = <0x0 0x40f04200 0x0 0x28>;
201 #pinctrl-cells = <1>;
202 pinctrl-single,register-width = <32>;
203 pinctrl-single,function-mask = <0x0000000F>;
204 status = "reserved";
205 };
206
207 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
208 mcu_timerio_output: pinctrl@40f04280 {
209 compatible = "ti,j7200-padconf", "pinctrl-single";
210 reg = <0x0 0x40f04280 0x0 0x28>;
211 #pinctrl-cells = <1>;
212 pinctrl-single,register-width = <32>;
213 pinctrl-single,function-mask = <0x0000000F>;
214 status = "reserved";
215 };
216
217 wkup_pmx0: pinctrl@4301c000 {
218 compatible = "ti,j7200-padconf", "pinctrl-single";
219 /* Proxy 0 addressing */
220 reg = <0x00 0x4301c000 0x00 0x34>;
221 #pinctrl-cells = <1>;
222 pinctrl-single,register-width = <32>;
223 pinctrl-single,function-mask = <0xffffffff>;
224 };
225
226 wkup_pmx1: pinctrl@4301c038 {
227 compatible = "ti,j7200-padconf", "pinctrl-single";
228 /* Proxy 0 addressing */
229 reg = <0x00 0x4301c038 0x00 0x8>;
230 #pinctrl-cells = <1>;
231 pinctrl-single,register-width = <32>;
232 pinctrl-single,function-mask = <0xffffffff>;
233 };
234
235 wkup_pmx2: pinctrl@4301c068 {
236 compatible = "ti,j7200-padconf", "pinctrl-single";
237 /* Proxy 0 addressing */
238 reg = <0x00 0x4301c068 0x00 0xec>;
239 #pinctrl-cells = <1>;
240 pinctrl-single,register-width = <32>;
241 pinctrl-single,function-mask = <0xffffffff>;
242 };
243
244 wkup_pmx3: pinctrl@4301c174 {
245 compatible = "ti,j7200-padconf", "pinctrl-single";
246 /* Proxy 0 addressing */
247 reg = <0x00 0x4301c174 0x00 0x20>;
248 #pinctrl-cells = <1>;
249 pinctrl-single,register-width = <32>;
250 pinctrl-single,function-mask = <0xffffffff>;
251 };
252
253 mcu_ram: sram@41c00000 {
254 compatible = "mmio-sram";
255 reg = <0x00 0x41c00000 0x00 0x100000>;
256 ranges = <0x00 0x00 0x41c00000 0x100000>;
257 #address-cells = <1>;
258 #size-cells = <1>;
259 };
260
261 wkup_uart0: serial@42300000 {
262 compatible = "ti,j721e-uart", "ti,am654-uart";
263 reg = <0x00 0x42300000 0x00 0x100>;
264 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
265 clock-frequency = <48000000>;
266 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
267 clocks = <&k3_clks 287 2>;
268 clock-names = "fclk";
269 status = "disabled";
270 };
271
272 mcu_uart0: serial@40a00000 {
273 compatible = "ti,j721e-uart", "ti,am654-uart";
274 reg = <0x00 0x40a00000 0x00 0x100>;
275 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
276 clock-frequency = <96000000>;
277 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
278 clocks = <&k3_clks 149 2>;
279 clock-names = "fclk";
280 status = "disabled";
281 };
282
283 wkup_gpio_intr: interrupt-controller@42200000 {
284 compatible = "ti,sci-intr";
285 reg = <0x00 0x42200000 0x00 0x400>;
286 ti,intr-trigger-type = <1>;
287 interrupt-controller;
288 interrupt-parent = <&gic500>;
289 #interrupt-cells = <1>;
290 ti,sci = <&dmsc>;
291 ti,sci-dev-id = <137>;
292 ti,interrupt-ranges = <16 960 16>;
293 };
294
295 wkup_gpio0: gpio@42110000 {
296 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
297 reg = <0x00 0x42110000 0x00 0x100>;
298 gpio-controller;
299 #gpio-cells = <2>;
300 interrupt-parent = <&wkup_gpio_intr>;
301 interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
304 ti,ngpio = <85>;
305 ti,davinci-gpio-unbanked = <0>;
306 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
307 clocks = <&k3_clks 113 0>;
308 clock-names = "gpio";
309 status = "disabled";
310 };
311
312 wkup_gpio1: gpio@42100000 {
313 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
314 reg = <0x00 0x42100000 0x00 0x100>;
315 gpio-controller;
316 #gpio-cells = <2>;
317 interrupt-parent = <&wkup_gpio_intr>;
318 interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 ti,ngpio = <85>;
322 ti,davinci-gpio-unbanked = <0>;
323 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
324 clocks = <&k3_clks 114 0>;
325 clock-names = "gpio";
326 status = "disabled";
327 };
328
329 mcu_navss: bus@28380000 {
330 compatible = "simple-bus";
331 #address-cells = <2>;
332 #size-cells = <2>;
333 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
334 dma-coherent;
335 dma-ranges;
336 ti,sci-dev-id = <232>;
337
338 mcu_ringacc: ringacc@2b800000 {
339 compatible = "ti,am654-navss-ringacc";
340 reg = <0x00 0x2b800000 0x00 0x400000>,
341 <0x00 0x2b000000 0x00 0x400000>,
342 <0x00 0x28590000 0x00 0x100>,
343 <0x00 0x2a500000 0x00 0x40000>,
344 <0x00 0x28440000 0x00 0x40000>;
345 reg-names = "rt", "fifos", "proxy_gcfg",
346 "proxy_target", "cfg";
347 ti,num-rings = <286>;
348 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
349 ti,sci = <&dmsc>;
350 ti,sci-dev-id = <235>;
351 msi-parent = <&main_udmass_inta>;
352 };
353
354 mcu_udmap: dma-controller@285c0000 {
355 compatible = "ti,j721e-navss-mcu-udmap";
356 reg = <0x00 0x285c0000 0x00 0x100>,
357 <0x00 0x2a800000 0x00 0x40000>,
358 <0x00 0x2aa00000 0x00 0x40000>,
359 <0x00 0x284a0000 0x00 0x4000>,
360 <0x00 0x284c0000 0x00 0x4000>,
361 <0x00 0x28400000 0x00 0x2000>;
362 reg-names = "gcfg", "rchanrt", "tchanrt",
363 "tchan", "rchan", "rflow";
364 msi-parent = <&main_udmass_inta>;
365 #dma-cells = <1>;
366
367 ti,sci = <&dmsc>;
368 ti,sci-dev-id = <236>;
369 ti,ringacc = <&mcu_ringacc>;
370
371 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
372 <0x0f>; /* TX_HCHAN */
373 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
374 <0x0b>; /* RX_HCHAN */
375 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
376 };
377 };
378
379 secure_proxy_mcu: mailbox@2a480000 {
380 compatible = "ti,am654-secure-proxy";
381 #mbox-cells = <1>;
382 reg-names = "target_data", "rt", "scfg";
383 reg = <0x0 0x2a480000 0x0 0x80000>,
384 <0x0 0x2a380000 0x0 0x80000>,
385 <0x0 0x2a400000 0x0 0x80000>;
386 /*
387 * Marked Disabled:
388 * Node is incomplete as it is meant for bootloaders and
389 * firmware on non-MPU processors
390 */
391 status = "disabled";
392 };
393
394 mcu_cpsw: ethernet@46000000 {
395 compatible = "ti,j721e-cpsw-nuss";
396 #address-cells = <2>;
397 #size-cells = <2>;
398 reg = <0x00 0x46000000 0x00 0x200000>;
399 reg-names = "cpsw_nuss";
400 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
401 dma-coherent;
402 clocks = <&k3_clks 18 21>;
403 clock-names = "fck";
404 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
405
406 dmas = <&mcu_udmap 0xf000>,
407 <&mcu_udmap 0xf001>,
408 <&mcu_udmap 0xf002>,
409 <&mcu_udmap 0xf003>,
410 <&mcu_udmap 0xf004>,
411 <&mcu_udmap 0xf005>,
412 <&mcu_udmap 0xf006>,
413 <&mcu_udmap 0xf007>,
414 <&mcu_udmap 0x7000>;
415 dma-names = "tx0", "tx1", "tx2", "tx3",
416 "tx4", "tx5", "tx6", "tx7",
417 "rx";
418
419 ethernet-ports {
420 #address-cells = <1>;
421 #size-cells = <0>;
422
423 cpsw_port1: port@1 {
424 reg = <1>;
425 ti,mac-only;
426 label = "port1";
427 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
428 phys = <&phy_gmii_sel 1>;
429 };
430 };
431
432 davinci_mdio: mdio@f00 {
433 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
434 reg = <0x00 0xf00 0x00 0x100>;
435 #address-cells = <1>;
436 #size-cells = <0>;
437 clocks = <&k3_clks 18 21>;
438 clock-names = "fck";
439 bus_freq = <1000000>;
440 };
441
442 cpts@3d000 {
443 compatible = "ti,am65-cpts";
444 reg = <0x00 0x3d000 0x00 0x400>;
445 clocks = <&k3_clks 18 2>;
446 clock-names = "cpts";
447 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
448 interrupt-names = "cpts";
449 ti,cpts-ext-ts-inputs = <4>;
450 ti,cpts-periodic-outputs = <2>;
451 };
452 };
453
454 mcu_i2c0: i2c@40b00000 {
455 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
456 reg = <0x00 0x40b00000 0x00 0x100>;
457 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
458 #address-cells = <1>;
459 #size-cells = <0>;
460 clock-names = "fck";
461 clocks = <&k3_clks 194 1>;
462 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
463 status = "disabled";
464 };
465
466 mcu_i2c1: i2c@40b10000 {
467 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
468 reg = <0x00 0x40b10000 0x00 0x100>;
469 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
470 #address-cells = <1>;
471 #size-cells = <0>;
472 clock-names = "fck";
473 clocks = <&k3_clks 195 1>;
474 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
475 status = "disabled";
476 };
477
478 wkup_i2c0: i2c@42120000 {
479 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
480 reg = <0x00 0x42120000 0x00 0x100>;
481 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
482 #address-cells = <1>;
483 #size-cells = <0>;
484 clock-names = "fck";
485 clocks = <&k3_clks 197 1>;
486 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
487 status = "disabled";
488 };
489
490 mcu_spi0: spi@40300000 {
491 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
492 reg = <0x00 0x040300000 0x00 0x400>;
493 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
494 #address-cells = <1>;
495 #size-cells = <0>;
496 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
497 clocks = <&k3_clks 274 0>;
498 status = "disabled";
499 };
500
501 mcu_spi1: spi@40310000 {
502 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
503 reg = <0x00 0x040310000 0x00 0x400>;
504 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
508 clocks = <&k3_clks 275 0>;
509 status = "disabled";
510 };
511
512 mcu_spi2: spi@40320000 {
513 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
514 reg = <0x00 0x040320000 0x00 0x400>;
515 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
516 #address-cells = <1>;
517 #size-cells = <0>;
518 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
519 clocks = <&k3_clks 276 0>;
520 status = "disabled";
521 };
522
523 fss: bus@47000000 {
524 compatible = "simple-bus";
525 #address-cells = <2>;
526 #size-cells = <2>;
527 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */
528 <0x0 0x47034000 0x0 0x47040000 0x0 0x100>, /* HBMC Control */
529 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */
530 <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>; /* HBMC/OSPI0 Memory */
531
532 hbmc_mux: mux-controller@47000004 {
533 compatible = "reg-mux";
534 reg = <0x00 0x47000004 0x00 0x4>;
535 #mux-control-cells = <1>;
536 mux-reg-masks = <0x0 0x2>; /* HBMC select */
537 };
538
539 hbmc: hyperbus@47034000 {
540 compatible = "ti,am654-hbmc";
541 reg = <0x00 0x47034000 0x00 0x100>,
542 <0x05 0x00000000 0x01 0x0000000>;
543 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
544 clocks = <&k3_clks 102 0>;
545 assigned-clocks = <&k3_clks 102 5>;
546 assigned-clock-rates = <333333333>;
547 #address-cells = <2>;
548 #size-cells = <1>;
549 mux-controls = <&hbmc_mux 0>;
550 };
551
552 ospi0: spi@47040000 {
553 compatible = "ti,am654-ospi", "cdns,qspi-nor";
554 reg = <0x0 0x47040000 0x0 0x100>,
555 <0x5 0x00000000 0x1 0x0000000>;
556 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
557 cdns,fifo-depth = <256>;
558 cdns,fifo-width = <4>;
559 cdns,trigger-address = <0x0>;
560 clocks = <&k3_clks 103 0>;
561 assigned-clocks = <&k3_clks 103 0>;
562 assigned-clock-parents = <&k3_clks 103 2>;
563 assigned-clock-rates = <166666666>;
564 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
565 #address-cells = <1>;
566 #size-cells = <0>;
567 status = "disabled";
568 };
569 };
570
571 tscadc0: tscadc@40200000 {
572 compatible = "ti,am3359-tscadc";
573 reg = <0x00 0x40200000 0x00 0x1000>;
574 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
575 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
576 clocks = <&k3_clks 0 1>;
577 assigned-clocks = <&k3_clks 0 3>;
578 assigned-clock-rates = <60000000>;
579 clock-names = "fck";
580 dmas = <&main_udmap 0x7400>,
581 <&main_udmap 0x7401>;
582 dma-names = "fifo0", "fifo1";
583
584 adc {
585 #io-channel-cells = <1>;
586 compatible = "ti,am3359-adc";
587 };
588 };
589
590 mcu_r5fss0: r5fss@41000000 {
591 compatible = "ti,j7200-r5fss";
592 ti,cluster-mode = <1>;
593 #address-cells = <1>;
594 #size-cells = <1>;
595 ranges = <0x41000000 0x00 0x41000000 0x20000>,
596 <0x41400000 0x00 0x41400000 0x20000>;
597 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
598
599 mcu_r5fss0_core0: r5f@41000000 {
600 compatible = "ti,j7200-r5f";
601 reg = <0x41000000 0x00010000>,
602 <0x41010000 0x00010000>;
603 reg-names = "atcm", "btcm";
604 ti,sci = <&dmsc>;
605 ti,sci-dev-id = <250>;
606 ti,sci-proc-ids = <0x01 0xff>;
607 resets = <&k3_reset 250 1>;
608 firmware-name = "j7200-mcu-r5f0_0-fw";
609 ti,atcm-enable = <1>;
610 ti,btcm-enable = <1>;
611 ti,loczrama = <1>;
612 };
613
614 mcu_r5fss0_core1: r5f@41400000 {
615 compatible = "ti,j7200-r5f";
616 reg = <0x41400000 0x00008000>,
617 <0x41410000 0x00008000>;
618 reg-names = "atcm", "btcm";
619 ti,sci = <&dmsc>;
620 ti,sci-dev-id = <251>;
621 ti,sci-proc-ids = <0x02 0xff>;
622 resets = <&k3_reset 251 1>;
623 firmware-name = "j7200-mcu-r5f0_1-fw";
624 ti,atcm-enable = <1>;
625 ti,btcm-enable = <1>;
626 ti,loczrama = <1>;
627 };
628 };
629
630 mcu_crypto: crypto@40900000 {
631 compatible = "ti,j721e-sa2ul";
632 reg = <0x00 0x40900000 0x00 0x1200>;
633 power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
634 #address-cells = <2>;
635 #size-cells = <2>;
636 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
637 dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
638 <&mcu_udmap 0x7503>;
639 dma-names = "tx", "rx1", "rx2";
640
641 rng: rng@40910000 {
642 compatible = "inside-secure,safexcel-eip76";
643 reg = <0x00 0x40910000 0x00 0x7d>;
644 interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
645 status = "disabled"; /* Used by OP-TEE */
646 };
647 };
648
649 wkup_vtm0: temperature-sensor@42040000 {
650 compatible = "ti,j7200-vtm";
651 reg = <0x00 0x42040000 0x00 0x350>,
652 <0x00 0x42050000 0x00 0x350>;
653 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
654 #thermal-sensor-cells = <1>;
655 };
656
657 mcu_esm: esm@40800000 {
658 compatible = "ti,j721e-esm";
659 reg = <0x00 0x40800000 0x00 0x1000>;
660 ti,esm-pins = <95>;
661 bootph-pre-ram;
662 };
663
664 mcu_mcan0: can@40528000 {
665 compatible = "bosch,m_can";
666 reg = <0x00 0x40528000 0x00 0x200>,
667 <0x00 0x40500000 0x00 0x8000>;
668 reg-names = "m_can", "message_ram";
669 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
670 clocks = <&k3_clks 172 0>, <&k3_clks 172 2>;
671 clock-names = "hclk", "cclk";
672 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
674 interrupt-names = "int0", "int1";
675 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
676 status = "disabled";
677 };
678
679 mcu_mcan1: can@40568000 {
680 compatible = "bosch,m_can";
681 reg = <0x00 0x40568000 0x00 0x200>,
682 <0x00 0x40540000 0x00 0x8000>;
683 reg-names = "m_can", "message_ram";
684 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
685 clocks = <&k3_clks 173 0>, <&k3_clks 173 2>;
686 clock-names = "hclk", "cclk";
687 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
689 interrupt-names = "int0", "int1";
690 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
691 status = "disabled";
692 };
693 };
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