1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree Source for J721S2 SoC Family
4 *
5 * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28
6 *
7 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 *
9 */
10
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/ti,sci_pm_domain.h>
14
15 #include "k3-pinctrl.h"
16
17 / {
18
19 model = "Texas Instruments K3 J721S2 SoC";
20 compatible = "ti,j721s2";
21 interrupt-parent = <&gic500>;
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 chosen { };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30 cpu-map {
31 cluster0: cluster0 {
32 core0 {
33 cpu = <&cpu0>;
34 };
35
36 core1 {
37 cpu = <&cpu1>;
38 };
39 };
40 };
41
42 cpu0: cpu@0 {
43 compatible = "arm,cortex-a72";
44 reg = <0x000>;
45 device_type = "cpu";
46 enable-method = "psci";
47 i-cache-size = <0xc000>;
48 i-cache-line-size = <64>;
49 i-cache-sets = <256>;
50 d-cache-size = <0x8000>;
51 d-cache-line-size = <64>;
52 d-cache-sets = <256>;
53 next-level-cache = <&L2_0>;
54 };
55
56 cpu1: cpu@1 {
57 compatible = "arm,cortex-a72";
58 reg = <0x001>;
59 device_type = "cpu";
60 enable-method = "psci";
61 i-cache-size = <0xc000>;
62 i-cache-line-size = <64>;
63 i-cache-sets = <256>;
64 d-cache-size = <0x8000>;
65 d-cache-line-size = <64>;
66 d-cache-sets = <256>;
67 next-level-cache = <&L2_0>;
68 };
69 };
70
71 L2_0: l2-cache0 {
72 compatible = "cache";
73 cache-unified;
74 cache-level = <2>;
75 cache-size = <0x100000>;
76 cache-line-size = <64>;
77 cache-sets = <1024>;
78 next-level-cache = <&msmc_l3>;
79 };
80
81 msmc_l3: l3-cache0 {
82 compatible = "cache";
83 cache-level = <3>;
84 cache-unified;
85 };
86
87 firmware {
88 optee {
89 compatible = "linaro,optee-tz";
90 method = "smc";
91 };
92
93 psci: psci {
94 compatible = "arm,psci-1.0";
95 method = "smc";
96 };
97 };
98
99 a72_timer0: timer-cl0-cpu0 {
100 compatible = "arm,armv8-timer";
101 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
102 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
103 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
104 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
105
106 };
107
108 pmu: pmu {
109 compatible = "arm,cortex-a72-pmu";
110 /* Recommendation from GIC500 TRM Table A.3 */
111 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
112 };
113
114 cbass_main: bus@100000 {
115 compatible = "simple-bus";
116 #address-cells = <2>;
117 #size-cells = <2>;
118 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
119 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
120 <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
121 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
122 <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/
123 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
124 <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
125 <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
126 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
127 <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
128 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
129 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
130 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
131
132 /* MCUSS_WKUP Range */
133 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
134 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
135 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
136 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
137 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
138 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
139 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
140 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
141 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
142 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
143 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
144 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
145 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
146
147 cbass_mcu_wakeup: bus@28380000 {
148 compatible = "simple-bus";
149 #address-cells = <2>;
150 #size-cells = <2>;
151 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
152 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
153 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
154 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
155 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
156 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
157 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
158 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
159 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
160 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
161 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
162 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
163 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
164
165 };
166
167 };
168
169 thermal_zones: thermal-zones {
170 #include "k3-j721s2-thermal.dtsi"
171 };
172 };
173
174 /* Now include peripherals from each bus segment */
175 #include "k3-j721s2-main.dtsi"
176 #include "k3-j721s2-mcu-wakeup.dtsi"
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