1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /*
3 * Device Tree file for the J722S MAIN domain peripherals
4 *
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
10
11 / {
12 serdes_refclk: clk-0 {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <0>;
16 };
17 };
18
19 &cbass_main {
20 serdes_wiz0: phy@f000000 {
21 compatible = "ti,am64-wiz-10g";
22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
23 #address-cells = <1>;
24 #size-cells = <1>;
25 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
27 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
28 num-lanes = <1>;
29 #reset-cells = <1>;
30 #clock-cells = <1>;
31
32 assigned-clocks = <&k3_clks 279 1>;
33 assigned-clock-parents = <&k3_clks 279 5>;
34
35 serdes0: serdes@f000000 {
36 compatible = "ti,j721e-serdes-10g";
37 reg = <0x0f000000 0x00010000>;
38 reg-names = "torrent_phy";
39 resets = <&serdes_wiz0 0>;
40 reset-names = "torrent_reset";
41 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
42 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
43 clock-names = "refclk", "phy_en_refclk";
44 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
45 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
46 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
47 assigned-clock-parents = <&k3_clks 279 1>,
48 <&k3_clks 279 1>,
49 <&k3_clks 279 1>;
50 #address-cells = <1>;
51 #size-cells = <0>;
52 #clock-cells = <1>;
53
54 status = "disabled"; /* Needs lane config */
55 };
56 };
57
58 serdes_wiz1: phy@f010000 {
59 compatible = "ti,am64-wiz-10g";
60 ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
61 #address-cells = <1>;
62 #size-cells = <1>;
63 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
65 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
66 num-lanes = <1>;
67 #reset-cells = <1>;
68 #clock-cells = <1>;
69
70 assigned-clocks = <&k3_clks 280 1>;
71 assigned-clock-parents = <&k3_clks 280 5>;
72
73 serdes1: serdes@f010000 {
74 compatible = "ti,j721e-serdes-10g";
75 reg = <0x0f010000 0x00010000>;
76 reg-names = "torrent_phy";
77 resets = <&serdes_wiz1 0>;
78 reset-names = "torrent_reset";
79 clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
80 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
81 clock-names = "refclk", "phy_en_refclk";
82 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
83 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
84 <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
85 assigned-clock-parents = <&k3_clks 280 1>,
86 <&k3_clks 280 1>,
87 <&k3_clks 280 1>;
88 #address-cells = <1>;
89 #size-cells = <0>;
90 #clock-cells = <1>;
91
92 status = "disabled"; /* Needs lane config */
93 };
94 };
95
96 pcie0_rc: pcie@f102000 {
97 compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
98 reg = <0x00 0x0f102000 0x00 0x1000>,
99 <0x00 0x0f100000 0x00 0x400>,
100 <0x00 0x0d000000 0x00 0x00800000>,
101 <0x00 0x68000000 0x00 0x00001000>;
102 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
103 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
104 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
105 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
106 interrupt-names = "link_state";
107 interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
108 device_type = "pci";
109 max-link-speed = <3>;
110 num-lanes = <1>;
111 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
112 clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
113 clock-names = "fck", "pcie_refclk";
114 #address-cells = <3>;
115 #size-cells = <2>;
116 bus-range = <0x0 0xff>;
117 vendor-id = <0x104c>;
118 device-id = <0xb010>;
119 cdns,no-bar-match-nbits = <64>;
120 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
121 msi-map = <0x0 &gic_its 0x0 0x10000>;
122 status = "disabled";
123 };
124
125 usbss1: usb@f920000 {
126 compatible = "ti,j721e-usb";
127 reg = <0x00 0x0f920000 0x00 0x100>;
128 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
129 clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
130 clock-names = "ref", "lpm";
131 assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
132 assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
133 #address-cells = <2>;
134 #size-cells = <2>;
135 ranges;
136 status = "disabled";
137
138 usb1: usb@31200000{
139 compatible = "cdns,usb3";
140 reg = <0x00 0x31200000 0x00 0x10000>,
141 <0x00 0x31210000 0x00 0x10000>,
142 <0x00 0x31220000 0x00 0x10000>;
143 reg-names = "otg",
144 "xhci",
145 "dev";
146 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
147 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
148 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
149 interrupt-names = "host",
150 "peripheral",
151 "otg";
152 maximum-speed = "super-speed";
153 dr_mode = "otg";
154 };
155 };
156 };
157
158 &main_conf {
159 serdes_ln_ctrl: mux-controller@4080 {
160 compatible = "reg-mux";
161 reg = <0x4080 0x14>;
162 #mux-control-cells = <1>;
163 mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
164 <0x10 0x3>; /* SERDES1 lane0 select */
165 };
166
167 audio_refclk1: clock@82e4 {
168 compatible = "ti,am62-audio-refclk";
169 reg = <0x82e4 0x4>;
170 clocks = <&k3_clks 157 18>;
171 assigned-clocks = <&k3_clks 157 18>;
172 assigned-clock-parents = <&k3_clks 157 33>;
173 #clock-cells = <0>;
174 };
175 };
176
177 &wkup_conf {
178 pcie0_ctrl: pcie0-ctrl@4070 {
179 compatible = "ti,j784s4-pcie-ctrl", "syscon";
180 reg = <0x4070 0x4>;
181 };
182 };
183
184 &oc_sram {
185 reg = <0x00 0x70000000 0x00 0x40000>;
186 ranges = <0x00 0x00 0x70000000 0x40000>;
187 };
188
189 &inta_main_dmss {
190 ti,interrupt-ranges = <7 71 21>;
191 };
192
193 &main_pmx0 {
194 pinctrl-single,gpio-range =
195 <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>,
196 <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>,
197 <&main_pmx0_range 72 17 PIN_GPIO_RANGE_IOPAD>,
198 <&main_pmx0_range 101 25 PIN_GPIO_RANGE_IOPAD>,
199 <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>,
200 <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>,
201 <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>;
202
203 main_pmx0_range: gpio-range {
204 #pinctrl-single,gpio-range-cells = <3>;
205 };
206 };
207
208 &main_gpio0 {
209 gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
210 <&main_pmx0 70 72 17>;
211 ti,ngpio = <87>;
212 };
213
214 &main_gpio1 {
215 gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>,
216 <&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
217 ti,ngpio = <73>;
218 };
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