1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Clock specification for Xilinx ZynqMP
4 *
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
12 / {
13 pss_ref_clk: pss_ref_clk {
14 bootph-all;
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <33333333>;
18 };
19
20 video_clk: video_clk {
21 bootph-all;
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <27000000>;
25 };
26
27 pss_alt_ref_clk: pss_alt_ref_clk {
28 bootph-all;
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <0>;
32 };
33
34 gt_crx_ref_clk: gt_crx_ref_clk {
35 bootph-all;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <108000000>;
39 };
40
41 aux_ref_clk: aux_ref_clk {
42 bootph-all;
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <27000000>;
46 };
47 };
48
49 &zynqmp_firmware {
50 zynqmp_clk: clock-controller {
51 bootph-all;
52 #clock-cells = <1>;
53 compatible = "xlnx,zynqmp-clk";
54 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
55 <&aux_ref_clk>, <>_crx_ref_clk>;
56 clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
57 "aux_ref_clk", "gt_crx_ref_clk";
58 };
59 };
60
61 &can0 {
62 clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
63 };
64
65 &can1 {
66 clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
67 };
68
69 &cpu0 {
70 clocks = <&zynqmp_clk ACPU>;
71 };
72
73 &cpu0_debug {
74 clocks = <&zynqmp_clk DBF_FPD>;
75 };
76
77 &cpu1_debug {
78 clocks = <&zynqmp_clk DBF_FPD>;
79 };
80
81 &cpu2_debug {
82 clocks = <&zynqmp_clk DBF_FPD>;
83 };
84
85 &cpu3_debug {
86 clocks = <&zynqmp_clk DBF_FPD>;
87 };
88
89 &fpd_dma_chan1 {
90 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
91 };
92
93 &fpd_dma_chan2 {
94 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
95 };
96
97 &fpd_dma_chan3 {
98 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
99 };
100
101 &fpd_dma_chan4 {
102 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
103 };
104
105 &fpd_dma_chan5 {
106 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
107 };
108
109 &fpd_dma_chan6 {
110 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
111 };
112
113 &fpd_dma_chan7 {
114 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
115 };
116
117 &fpd_dma_chan8 {
118 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
119 };
120
121 &gpu {
122 clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
123 };
124
125 &lpd_dma_chan1 {
126 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
127 };
128
129 &lpd_dma_chan2 {
130 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
131 };
132
133 &lpd_dma_chan3 {
134 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
135 };
136
137 &lpd_dma_chan4 {
138 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
139 };
140
141 &lpd_dma_chan5 {
142 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
143 };
144
145 &lpd_dma_chan6 {
146 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
147 };
148
149 &lpd_dma_chan7 {
150 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
151 };
152
153 &lpd_dma_chan8 {
154 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
155 };
156
157 &nand0 {
158 clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
159 };
160
161 &gem0 {
162 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
163 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
164 <&zynqmp_clk GEM_TSU>;
165 assigned-clocks = <&zynqmp_clk GEM_TSU>;
166 };
167
168 &gem1 {
169 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
170 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
171 <&zynqmp_clk GEM_TSU>;
172 assigned-clocks = <&zynqmp_clk GEM_TSU>;
173 };
174
175 &gem2 {
176 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
177 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
178 <&zynqmp_clk GEM_TSU>;
179 assigned-clocks = <&zynqmp_clk GEM_TSU>;
180 };
181
182 &gem3 {
183 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
184 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
185 <&zynqmp_clk GEM_TSU>;
186 assigned-clocks = <&zynqmp_clk GEM_TSU>;
187 };
188
189 &gpio {
190 clocks = <&zynqmp_clk LPD_LSBUS>;
191 };
192
193 &i2c0 {
194 clocks = <&zynqmp_clk I2C0_REF>;
195 };
196
197 &i2c1 {
198 clocks = <&zynqmp_clk I2C1_REF>;
199 };
200
201 &pcie {
202 clocks = <&zynqmp_clk PCIE_REF>;
203 };
204
205 &qspi {
206 clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
207 };
208
209 &sata {
210 clocks = <&zynqmp_clk SATA_REF>;
211 };
212
213 &sdhci0 {
214 clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
215 assigned-clocks = <&zynqmp_clk SDIO0_REF>;
216 };
217
218 &sdhci1 {
219 clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
220 assigned-clocks = <&zynqmp_clk SDIO1_REF>;
221 };
222
223 &spi0 {
224 clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
225 };
226
227 &spi1 {
228 clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
229 };
230
231 &ttc0 {
232 clocks = <&zynqmp_clk LPD_LSBUS>;
233 };
234
235 &ttc1 {
236 clocks = <&zynqmp_clk LPD_LSBUS>;
237 };
238
239 &ttc2 {
240 clocks = <&zynqmp_clk LPD_LSBUS>;
241 };
242
243 &ttc3 {
244 clocks = <&zynqmp_clk LPD_LSBUS>;
245 };
246
247 &uart0 {
248 clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
249 assigned-clocks = <&zynqmp_clk UART0_REF>;
250 };
251
252 &uart1 {
253 clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
254 assigned-clocks = <&zynqmp_clk UART1_REF>;
255 };
256
257 &usb0 {
258 clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
259 assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
260 };
261
262 &dwc3_0 {
263 clocks = <&zynqmp_clk USB3_DUAL_REF>;
264 };
265
266 &usb1 {
267 clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
268 assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
269 };
270
271 &dwc3_1 {
272 clocks = <&zynqmp_clk USB3_DUAL_REF>;
273 };
274
275 &watchdog0 {
276 clocks = <&zynqmp_clk WDT>;
277 };
278
279 &lpd_watchdog {
280 clocks = <&zynqmp_clk LPD_WDT>;
281 };
282
283 &xilinx_ams {
284 clocks = <&zynqmp_clk AMS_REF>;
285 };
286
287 &zynqmp_dpdma {
288 clocks = <&zynqmp_clk DPDMA_REF>;
289 assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
290 };
291
292 &zynqmp_dpsub {
293 clocks = <&zynqmp_clk TOPSW_LSBUS>,
294 <&zynqmp_clk DP_AUDIO_REF>,
295 <&zynqmp_clk DP_VIDEO_REF>;
296 assigned-clocks = <&zynqmp_clk DP_STC_REF>,
297 <&zynqmp_clk DP_AUDIO_REF>,
298 <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */
299 };
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