1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
4 *
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11 /dts-v1/;
12
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17
18 / {
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
21
22 aliases {
23 ethernet0 = &gem2;
24 i2c0 = &i2c0;
25 rtc0 = &rtc;
26 serial0 = &uart0;
27 serial1 = &uart1;
28 spi0 = &spi0;
29 spi1 = &spi1;
30 usb0 = &usb1;
31 };
32
33 chosen {
34 bootargs = "earlycon";
35 stdout-path = "serial0:115200n8";
36 };
37
38 memory@0 {
39 device_type = "memory";
40 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
41 };
42 };
43
44 &can0 {
45 status = "okay";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_can0_default>;
48 };
49
50 &can1 {
51 status = "okay";
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_can1_default>;
54 };
55
56 &fpd_dma_chan1 {
57 status = "okay";
58 };
59
60 &fpd_dma_chan2 {
61 status = "okay";
62 };
63
64 &fpd_dma_chan3 {
65 status = "okay";
66 };
67
68 &fpd_dma_chan4 {
69 status = "okay";
70 };
71
72 &fpd_dma_chan5 {
73 status = "okay";
74 };
75
76 &fpd_dma_chan6 {
77 status = "okay";
78 };
79
80 &fpd_dma_chan7 {
81 status = "okay";
82 };
83
84 &fpd_dma_chan8 {
85 status = "okay";
86 };
87
88 &gem2 {
89 status = "okay";
90 phy-handle = <&phy0>;
91 phy-mode = "rgmii-id";
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_gem2_default>;
94 mdio: mdio {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 phy0: ethernet-phy@5 {
98 reg = <5>;
99 ti,rx-internal-delay = <0x8>;
100 ti,tx-internal-delay = <0xa>;
101 ti,fifo-depth = <0x1>;
102 ti,dp83867-rxctrl-strap-quirk;
103 };
104 };
105 };
106
107 &gpio {
108 status = "okay";
109 };
110
111 &i2c0 {
112 status = "okay";
113 clock-frequency = <400000>;
114 pinctrl-names = "default", "gpio";
115 pinctrl-0 = <&pinctrl_i2c0_default>;
116 pinctrl-1 = <&pinctrl_i2c0_gpio>;
117 scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
118 sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
119
120 tca6416_u26: gpio@20 {
121 compatible = "ti,tca6416";
122 reg = <0x20>;
123 gpio-controller;
124 #gpio-cells = <2>;
125 /* IRQ not connected */
126 };
127
128 rtc@68 {
129 compatible = "dallas,ds1339";
130 reg = <0x68>;
131 };
132 };
133
134 &nand0 {
135 status = "okay";
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_nand0_default>;
138 arasan,has-mdma;
139
140 nand@0 {
141 reg = <0x0>;
142 #address-cells = <0x2>;
143 #size-cells = <0x1>;
144 nand-ecc-mode = "soft";
145 nand-ecc-algo = "bch";
146 nand-rb = <0>;
147 label = "main-storage-0";
148 };
149 nand@1 {
150 reg = <0x1>;
151 #address-cells = <0x2>;
152 #size-cells = <0x1>;
153 nand-ecc-mode = "soft";
154 nand-ecc-algo = "bch";
155 nand-rb = <0>;
156 label = "main-storage-1";
157 };
158 };
159
160 &pinctrl0 {
161 status = "okay";
162 pinctrl_can0_default: can0-default {
163 mux {
164 function = "can0";
165 groups = "can0_9_grp";
166 };
167
168 conf {
169 groups = "can0_9_grp";
170 slew-rate = <SLEW_RATE_SLOW>;
171 power-source = <IO_STANDARD_LVCMOS18>;
172 };
173
174 conf-rx {
175 pins = "MIO38";
176 bias-high-impedance;
177 };
178
179 conf-tx {
180 pins = "MIO39";
181 bias-disable;
182 };
183 };
184
185 pinctrl_can1_default: can1-default {
186 mux {
187 function = "can1";
188 groups = "can1_8_grp";
189 };
190
191 conf {
192 groups = "can1_8_grp";
193 slew-rate = <SLEW_RATE_SLOW>;
194 power-source = <IO_STANDARD_LVCMOS18>;
195 };
196
197 conf-rx {
198 pins = "MIO33";
199 bias-high-impedance;
200 };
201
202 conf-tx {
203 pins = "MIO32";
204 bias-disable;
205 };
206 };
207
208 pinctrl_i2c0_default: i2c0-default {
209 mux {
210 groups = "i2c0_1_grp";
211 function = "i2c0";
212 };
213
214 conf {
215 groups = "i2c0_1_grp";
216 bias-pull-up;
217 slew-rate = <SLEW_RATE_SLOW>;
218 power-source = <IO_STANDARD_LVCMOS18>;
219 };
220 };
221
222 pinctrl_i2c0_gpio: i2c0-gpio-grp {
223 mux {
224 groups = "gpio0_6_grp", "gpio0_7_grp";
225 function = "gpio0";
226 };
227
228 conf {
229 groups = "gpio0_6_grp", "gpio0_7_grp";
230 slew-rate = <SLEW_RATE_SLOW>;
231 power-source = <IO_STANDARD_LVCMOS18>;
232 };
233 };
234
235 pinctrl_uart0_default: uart0-default {
236 mux {
237 groups = "uart0_10_grp";
238 function = "uart0";
239 };
240
241 conf {
242 groups = "uart0_10_grp";
243 slew-rate = <SLEW_RATE_SLOW>;
244 power-source = <IO_STANDARD_LVCMOS18>;
245 };
246
247 conf-rx {
248 pins = "MIO42";
249 bias-high-impedance;
250 };
251
252 conf-tx {
253 pins = "MIO43";
254 bias-disable;
255 };
256 };
257
258 pinctrl_uart1_default: uart1-default {
259 mux {
260 groups = "uart1_10_grp";
261 function = "uart1";
262 };
263
264 conf {
265 groups = "uart1_10_grp";
266 slew-rate = <SLEW_RATE_SLOW>;
267 power-source = <IO_STANDARD_LVCMOS18>;
268 };
269
270 conf-rx {
271 pins = "MIO41";
272 bias-high-impedance;
273 };
274
275 conf-tx {
276 pins = "MIO40";
277 bias-disable;
278 };
279 };
280
281 pinctrl_usb1_default: usb1-default {
282 mux {
283 groups = "usb1_0_grp";
284 function = "usb1";
285 };
286
287 conf {
288 groups = "usb1_0_grp";
289 power-source = <IO_STANDARD_LVCMOS18>;
290 };
291
292 conf-rx {
293 pins = "MIO64", "MIO65", "MIO67";
294 bias-high-impedance;
295 drive-strength = <12>;
296 slew-rate = <SLEW_RATE_FAST>;
297 };
298
299 conf-tx {
300 pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
301 "MIO72", "MIO73", "MIO74", "MIO75";
302 bias-disable;
303 drive-strength = <4>;
304 slew-rate = <SLEW_RATE_SLOW>;
305 };
306 };
307
308 pinctrl_gem2_default: gem2-default {
309 mux {
310 function = "ethernet2";
311 groups = "ethernet2_0_grp";
312 };
313
314 conf {
315 groups = "ethernet2_0_grp";
316 slew-rate = <SLEW_RATE_SLOW>;
317 power-source = <IO_STANDARD_LVCMOS18>;
318 };
319
320 conf-rx {
321 pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
322 "MIO63";
323 bias-high-impedance;
324 low-power-disable;
325 };
326
327 conf-tx {
328 pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
329 "MIO57";
330 bias-disable;
331 low-power-enable;
332 };
333
334 mux-mdio {
335 function = "mdio2";
336 groups = "mdio2_0_grp";
337 };
338
339 conf-mdio {
340 groups = "mdio2_0_grp";
341 slew-rate = <SLEW_RATE_SLOW>;
342 power-source = <IO_STANDARD_LVCMOS18>;
343 bias-disable;
344 };
345 };
346
347 pinctrl_nand0_default: nand0-default {
348 mux {
349 groups = "nand0_0_grp";
350 function = "nand0";
351 };
352
353 conf {
354 groups = "nand0_0_grp";
355 bias-pull-up;
356 };
357
358 mux-ce {
359 groups = "nand0_ce_0_grp";
360 function = "nand0_ce";
361 };
362
363 conf-ce {
364 groups = "nand0_ce_0_grp";
365 bias-pull-up;
366 };
367
368 mux-rb {
369 groups = "nand0_rb_0_grp";
370 function = "nand0_rb";
371 };
372
373 conf-rb {
374 groups = "nand0_rb_0_grp";
375 bias-pull-up;
376 };
377
378 mux-dqs {
379 groups = "nand0_dqs_0_grp";
380 function = "nand0_dqs";
381 };
382
383 conf-dqs {
384 groups = "nand0_dqs_0_grp";
385 bias-pull-up;
386 };
387 };
388
389 pinctrl_spi0_default: spi0-default {
390 mux {
391 groups = "spi0_0_grp";
392 function = "spi0";
393 };
394
395 conf {
396 groups = "spi0_0_grp";
397 bias-disable;
398 slew-rate = <SLEW_RATE_SLOW>;
399 power-source = <IO_STANDARD_LVCMOS18>;
400 };
401
402 mux-cs {
403 groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
404 "spi0_ss_2_grp";
405 function = "spi0_ss";
406 };
407
408 conf-cs {
409 groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
410 "spi0_ss_2_grp";
411 bias-disable;
412 };
413 };
414
415 pinctrl_spi1_default: spi1-default {
416 mux {
417 groups = "spi1_3_grp";
418 function = "spi1";
419 };
420
421 conf {
422 groups = "spi1_3_grp";
423 bias-disable;
424 slew-rate = <SLEW_RATE_SLOW>;
425 power-source = <IO_STANDARD_LVCMOS18>;
426 };
427
428 mux-cs {
429 groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
430 "spi1_ss_11_grp";
431 function = "spi1_ss";
432 };
433
434 conf-cs {
435 groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
436 "spi1_ss_11_grp";
437 bias-disable;
438 };
439 };
440 };
441
442 &rtc {
443 status = "okay";
444 };
445
446 &spi0 {
447 status = "okay";
448 num-cs = <1>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_spi0_default>;
451
452 spi0_flash0: flash@0 {
453 #address-cells = <1>;
454 #size-cells = <1>;
455 compatible = "sst,sst25wf080", "jedec,spi-nor";
456 spi-max-frequency = <50000000>;
457 reg = <0>;
458
459 partition@0 {
460 label = "spi0-data";
461 reg = <0x0 0x100000>;
462 };
463 };
464 };
465
466 &spi1 {
467 status = "okay";
468 num-cs = <1>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_spi1_default>;
471
472 spi1_flash0: flash@0 {
473 #address-cells = <1>;
474 #size-cells = <1>;
475 compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
476 spi-max-frequency = <20000000>;
477 reg = <0>;
478
479 partition@0 {
480 label = "spi1-data";
481 reg = <0x0 0x84000>;
482 };
483 };
484 };
485
486 /* ULPI SMSC USB3320 */
487 &usb1 {
488 status = "okay";
489 pinctrl-names = "default";
490 pinctrl-0 = <&pinctrl_usb1_default>;
491 };
492
493 &dwc3_1 {
494 status = "okay";
495 dr_mode = "host";
496 };
497
498 &uart0 {
499 status = "okay";
500 pinctrl-names = "default";
501 pinctrl-0 = <&pinctrl_uart0_default>;
502 };
503
504 &uart1 {
505 status = "okay";
506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_uart1_default>;
508 };
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