1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
4 *
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@amd.com>
8 */
9
10 /dts-v1/;
11
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14
15 / {
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
18
19 aliases {
20 ethernet0 = &gem0;
21 ethernet1 = &gem1;
22 ethernet2 = &gem2;
23 ethernet3 = &gem3;
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 rtc0 = &rtc;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 spi0 = &qspi;
30 };
31
32 chosen {
33 bootargs = "earlycon";
34 stdout-path = "serial0:115200n8";
35 };
36
37 memory@0 {
38 device_type = "memory";
39 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
40 };
41 };
42
43 &can0 {
44 status = "okay";
45 };
46
47 &can1 {
48 status = "okay";
49 };
50
51 &fpd_dma_chan1 {
52 status = "okay";
53 };
54
55 &fpd_dma_chan2 {
56 status = "okay";
57 };
58
59 &fpd_dma_chan3 {
60 status = "okay";
61 };
62
63 &fpd_dma_chan4 {
64 status = "okay";
65 };
66
67 &fpd_dma_chan5 {
68 status = "okay";
69 };
70
71 &fpd_dma_chan6 {
72 status = "okay";
73 };
74
75 &fpd_dma_chan7 {
76 status = "okay";
77 };
78
79 &fpd_dma_chan8 {
80 status = "okay";
81 };
82
83 &lpd_dma_chan1 {
84 status = "okay";
85 };
86
87 &lpd_dma_chan2 {
88 status = "okay";
89 };
90
91 &lpd_dma_chan3 {
92 status = "okay";
93 };
94
95 &lpd_dma_chan4 {
96 status = "okay";
97 };
98
99 &lpd_dma_chan5 {
100 status = "okay";
101 };
102
103 &lpd_dma_chan6 {
104 status = "okay";
105 };
106
107 &lpd_dma_chan7 {
108 status = "okay";
109 };
110
111 &lpd_dma_chan8 {
112 status = "okay";
113 };
114
115 &gem0 {
116 status = "okay";
117 phy-mode = "rgmii-id";
118 phy-handle = <ðernet_phy0>;
119 mdio: mdio {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
123 reg = <0>;
124 };
125 ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
126 reg = <7>;
127 };
128 ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
129 reg = <3>;
130 };
131 ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
132 reg = <8>;
133 };
134 };
135 };
136
137 &gem1 {
138 status = "okay";
139 phy-mode = "rgmii-id";
140 phy-handle = <ðernet_phy7>;
141 };
142
143 &gem2 {
144 status = "okay";
145 phy-mode = "rgmii-id";
146 phy-handle = <ðernet_phy3>;
147 };
148
149 &gem3 {
150 status = "okay";
151 phy-mode = "rgmii-id";
152 phy-handle = <ðernet_phy8>;
153 };
154
155 &gpio {
156 status = "okay";
157 };
158
159 &gpu {
160 status = "okay";
161 };
162
163 &i2c0 {
164 clock-frequency = <400000>;
165 status = "okay";
166 };
167
168 &i2c1 {
169 clock-frequency = <400000>;
170 status = "okay";
171 };
172
173 &qspi {
174 status = "okay";
175 flash@0 {
176 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
177 #address-cells = <1>;
178 #size-cells = <1>;
179 reg = <0x0>;
180 spi-tx-bus-width = <4>;
181 spi-rx-bus-width = <4>; /* also DUAL configuration possible */
182 spi-max-frequency = <108000000>; /* Based on DC1 spec */
183 };
184 };
185
186 &rtc {
187 status = "okay";
188 };
189
190 &uart0 {
191 status = "okay";
192 };
193
194 &uart1 {
195 status = "okay";
196 };
197
198 &watchdog0 {
199 status = "okay";
200 };
201
202 &zynqmp_dpdma {
203 status = "okay";
204 };
205
206 &zynqmp_dpsub {
207 status = "okay";
208 };
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