1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * dts file for Xilinx ZynqMP ZCU106
4 *
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11 /dts-v1/;
12
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
19
20 / {
21 model = "ZynqMP ZCU106 RevA";
22 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
23
24 aliases {
25 ethernet0 = &gem3;
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 mmc0 = &sdhci1;
29 nvmem0 = &eeprom;
30 rtc0 = &rtc;
31 serial0 = &uart0;
32 serial1 = &uart1;
33 serial2 = &dcc;
34 spi0 = &qspi;
35 usb0 = &usb0;
36 };
37
38 chosen {
39 bootargs = "earlycon";
40 stdout-path = "serial0:115200n8";
41 };
42
43 memory@0 {
44 device_type = "memory";
45 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
46 };
47
48 gpio-keys {
49 compatible = "gpio-keys";
50 autorepeat;
51 switch-19 {
52 label = "sw19";
53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54 linux,code = <KEY_DOWN>;
55 wakeup-source;
56 autorepeat;
57 };
58 };
59
60 leds {
61 compatible = "gpio-leds";
62 heartbeat-led {
63 label = "heartbeat";
64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "heartbeat";
66 };
67 };
68
69 ina226-u76 {
70 compatible = "iio-hwmon";
71 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
72 };
73 ina226-u77 {
74 compatible = "iio-hwmon";
75 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
76 };
77 ina226-u78 {
78 compatible = "iio-hwmon";
79 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
80 };
81 ina226-u87 {
82 compatible = "iio-hwmon";
83 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
84 };
85 ina226-u85 {
86 compatible = "iio-hwmon";
87 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
88 };
89 ina226-u86 {
90 compatible = "iio-hwmon";
91 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
92 };
93 ina226-u93 {
94 compatible = "iio-hwmon";
95 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
96 };
97 ina226-u88 {
98 compatible = "iio-hwmon";
99 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
100 };
101 ina226-u15 {
102 compatible = "iio-hwmon";
103 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
104 };
105 ina226-u92 {
106 compatible = "iio-hwmon";
107 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
108 };
109 ina226-u79 {
110 compatible = "iio-hwmon";
111 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
112 };
113 ina226-u81 {
114 compatible = "iio-hwmon";
115 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
116 };
117 ina226-u80 {
118 compatible = "iio-hwmon";
119 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
120 };
121 ina226-u84 {
122 compatible = "iio-hwmon";
123 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
124 };
125 ina226-u16 {
126 compatible = "iio-hwmon";
127 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
128 };
129 ina226-u65 {
130 compatible = "iio-hwmon";
131 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
132 };
133 ina226-u74 {
134 compatible = "iio-hwmon";
135 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
136 };
137 ina226-u75 {
138 compatible = "iio-hwmon";
139 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
140 };
141
142 /* 48MHz reference crystal */
143 ref48: ref48M {
144 compatible = "fixed-clock";
145 #clock-cells = <0>;
146 clock-frequency = <48000000>;
147 };
148
149 refhdmi: refhdmi {
150 compatible = "fixed-clock";
151 #clock-cells = <0>;
152 clock-frequency = <114285000>;
153 };
154
155 dpcon {
156 compatible = "dp-connector";
157 label = "P11";
158 type = "full-size";
159
160 port {
161 dpcon_in: endpoint {
162 remote-endpoint = <&dpsub_dp_out>;
163 };
164 };
165 };
166 };
167
168 &can1 {
169 status = "okay";
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_can1_default>;
172 };
173
174 &dcc {
175 status = "okay";
176 };
177
178 &fpd_dma_chan1 {
179 status = "okay";
180 };
181
182 &fpd_dma_chan2 {
183 status = "okay";
184 };
185
186 &fpd_dma_chan3 {
187 status = "okay";
188 };
189
190 &fpd_dma_chan4 {
191 status = "okay";
192 };
193
194 &fpd_dma_chan5 {
195 status = "okay";
196 };
197
198 &fpd_dma_chan6 {
199 status = "okay";
200 };
201
202 &fpd_dma_chan7 {
203 status = "okay";
204 };
205
206 &fpd_dma_chan8 {
207 status = "okay";
208 };
209
210 &gem3 {
211 status = "okay";
212 phy-handle = <&phy0>;
213 phy-mode = "rgmii-id";
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_gem3_default>;
216 mdio: mdio {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 phy0: ethernet-phy@c {
220 #phy-cells = <1>;
221 reg = <0xc>;
222 compatible = "ethernet-phy-id2000.a231";
223 ti,rx-internal-delay = <0x8>;
224 ti,tx-internal-delay = <0xa>;
225 ti,fifo-depth = <0x1>;
226 ti,dp83867-rxctrl-strap-quirk;
227 reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
228 };
229 };
230 };
231
232 &gpio {
233 status = "okay";
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_gpio_default>;
236 };
237
238 &gpu {
239 status = "okay";
240 };
241
242 &i2c0 {
243 status = "okay";
244 clock-frequency = <400000>;
245 pinctrl-names = "default", "gpio";
246 pinctrl-0 = <&pinctrl_i2c0_default>;
247 pinctrl-1 = <&pinctrl_i2c0_gpio>;
248 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
249 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
250
251 tca6416_u97: gpio@20 {
252 compatible = "ti,tca6416";
253 reg = <0x20>;
254 gpio-controller; /* interrupt not connected */
255 #gpio-cells = <2>;
256 /*
257 * IRQ not connected
258 * Lines:
259 * 0 - SFP_SI5328_INT_ALM
260 * 1 - HDMI_SI5328_INT_ALM
261 * 5 - IIC_MUX_RESET_B
262 * 6 - GEM3_EXP_RESET_B
263 * 10 - FMC_HPC0_PRSNT_M2C_B
264 * 11 - FMC_HPC1_PRSNT_M2C_B
265 * 2-4, 7, 12-17 - not connected
266 */
267 };
268
269 tca6416_u61: gpio@21 {
270 compatible = "ti,tca6416";
271 reg = <0x21>;
272 gpio-controller;
273 #gpio-cells = <2>;
274 /*
275 * IRQ not connected
276 * Lines:
277 * 0 - VCCPSPLL_EN
278 * 1 - MGTRAVCC_EN
279 * 2 - MGTRAVTT_EN
280 * 3 - VCCPSDDRPLL_EN
281 * 4 - MIO26_PMU_INPUT_LS
282 * 5 - PL_PMBUS_ALERT
283 * 6 - PS_PMBUS_ALERT
284 * 7 - MAXIM_PMBUS_ALERT
285 * 10 - PL_DDR4_VTERM_EN
286 * 11 - PL_DDR4_VPP_2V5_EN
287 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
288 * 13 - PS_DIMM_SUSPEND_EN
289 * 14 - PS_DDR4_VTERM_EN
290 * 15 - PS_DDR4_VPP_2V5_EN
291 * 16 - 17 - not connected
292 */
293 };
294
295 i2c-mux@75 { /* u60 */
296 compatible = "nxp,pca9544";
297 #address-cells = <1>;
298 #size-cells = <0>;
299 reg = <0x75>;
300 i2c@0 {
301 #address-cells = <1>;
302 #size-cells = <0>;
303 reg = <0>;
304 /* PS_PMBUS */
305 u76: ina226@40 { /* u76 */
306 compatible = "ti,ina226";
307 #io-channel-cells = <1>;
308 label = "ina226-u76";
309 reg = <0x40>;
310 shunt-resistor = <5000>;
311 };
312 u77: ina226@41 { /* u77 */
313 compatible = "ti,ina226";
314 #io-channel-cells = <1>;
315 label = "ina226-u77";
316 reg = <0x41>;
317 shunt-resistor = <5000>;
318 };
319 u78: ina226@42 { /* u78 */
320 compatible = "ti,ina226";
321 #io-channel-cells = <1>;
322 label = "ina226-u78";
323 reg = <0x42>;
324 shunt-resistor = <5000>;
325 };
326 u87: ina226@43 { /* u87 */
327 compatible = "ti,ina226";
328 #io-channel-cells = <1>;
329 label = "ina226-u87";
330 reg = <0x43>;
331 shunt-resistor = <5000>;
332 };
333 u85: ina226@44 { /* u85 */
334 compatible = "ti,ina226";
335 #io-channel-cells = <1>;
336 label = "ina226-u85";
337 reg = <0x44>;
338 shunt-resistor = <5000>;
339 };
340 u86: ina226@45 { /* u86 */
341 compatible = "ti,ina226";
342 #io-channel-cells = <1>;
343 label = "ina226-u86";
344 reg = <0x45>;
345 shunt-resistor = <5000>;
346 };
347 u93: ina226@46 { /* u93 */
348 compatible = "ti,ina226";
349 #io-channel-cells = <1>;
350 label = "ina226-u93";
351 reg = <0x46>;
352 shunt-resistor = <5000>;
353 };
354 u88: ina226@47 { /* u88 */
355 compatible = "ti,ina226";
356 #io-channel-cells = <1>;
357 label = "ina226-u88";
358 reg = <0x47>;
359 shunt-resistor = <5000>;
360 };
361 u15: ina226@4a { /* u15 */
362 compatible = "ti,ina226";
363 #io-channel-cells = <1>;
364 label = "ina226-u15";
365 reg = <0x4a>;
366 shunt-resistor = <5000>;
367 };
368 u92: ina226@4b { /* u92 */
369 compatible = "ti,ina226";
370 #io-channel-cells = <1>;
371 label = "ina226-u92";
372 reg = <0x4b>;
373 shunt-resistor = <5000>;
374 };
375 };
376 i2c@1 {
377 #address-cells = <1>;
378 #size-cells = <0>;
379 reg = <1>;
380 /* PL_PMBUS */
381 u79: ina226@40 { /* u79 */
382 compatible = "ti,ina226";
383 #io-channel-cells = <1>;
384 label = "ina226-u79";
385 reg = <0x40>;
386 shunt-resistor = <2000>;
387 };
388 u81: ina226@41 { /* u81 */
389 compatible = "ti,ina226";
390 #io-channel-cells = <1>;
391 label = "ina226-u81";
392 reg = <0x41>;
393 shunt-resistor = <5000>;
394 };
395 u80: ina226@42 { /* u80 */
396 compatible = "ti,ina226";
397 #io-channel-cells = <1>;
398 label = "ina226-u80";
399 reg = <0x42>;
400 shunt-resistor = <5000>;
401 };
402 u84: ina226@43 { /* u84 */
403 compatible = "ti,ina226";
404 #io-channel-cells = <1>;
405 label = "ina226-u84";
406 reg = <0x43>;
407 shunt-resistor = <5000>;
408 };
409 u16: ina226@44 { /* u16 */
410 compatible = "ti,ina226";
411 #io-channel-cells = <1>;
412 label = "ina226-u16";
413 reg = <0x44>;
414 shunt-resistor = <5000>;
415 };
416 u65: ina226@45 { /* u65 */
417 compatible = "ti,ina226";
418 #io-channel-cells = <1>;
419 label = "ina226-u65";
420 reg = <0x45>;
421 shunt-resistor = <5000>;
422 };
423 u74: ina226@46 { /* u74 */
424 compatible = "ti,ina226";
425 #io-channel-cells = <1>;
426 label = "ina226-u74";
427 reg = <0x46>;
428 shunt-resistor = <5000>;
429 };
430 u75: ina226@47 { /* u75 */
431 compatible = "ti,ina226";
432 #io-channel-cells = <1>;
433 label = "ina226-u75";
434 reg = <0x47>;
435 shunt-resistor = <5000>;
436 };
437 };
438 i2c@2 {
439 #address-cells = <1>;
440 #size-cells = <0>;
441 reg = <2>;
442 /* MAXIM_PMBUS - 00 */
443 max15301@a { /* u46 */
444 compatible = "maxim,max15301";
445 reg = <0xa>;
446 };
447 max15303@b { /* u4 */
448 compatible = "maxim,max15303";
449 reg = <0xb>;
450 };
451 max15303@10 { /* u13 */
452 compatible = "maxim,max15303";
453 reg = <0x10>;
454 };
455 max15301@13 { /* u47 */
456 compatible = "maxim,max15301";
457 reg = <0x13>;
458 };
459 max15303@14 { /* u7 */
460 compatible = "maxim,max15303";
461 reg = <0x14>;
462 };
463 max15303@15 { /* u6 */
464 compatible = "maxim,max15303";
465 reg = <0x15>;
466 };
467 max15303@16 { /* u10 */
468 compatible = "maxim,max15303";
469 reg = <0x16>;
470 };
471 max15303@17 { /* u9 */
472 compatible = "maxim,max15303";
473 reg = <0x17>;
474 };
475 max15301@18 { /* u63 */
476 compatible = "maxim,max15301";
477 reg = <0x18>;
478 };
479 max15303@1a { /* u49 */
480 compatible = "maxim,max15303";
481 reg = <0x1a>;
482 };
483 max15303@1b { /* u8 */
484 compatible = "maxim,max15303";
485 reg = <0x1b>;
486 };
487 max15303@1d { /* u18 */
488 compatible = "maxim,max15303";
489 reg = <0x1d>;
490 };
491
492 max20751@72 { /* u95 */
493 compatible = "maxim,max20751";
494 reg = <0x72>;
495 };
496 max20751@73 { /* u96 */
497 compatible = "maxim,max20751";
498 reg = <0x73>;
499 };
500 };
501 /* Bus 3 is not connected */
502 };
503 };
504
505 &i2c1 {
506 status = "okay";
507 clock-frequency = <400000>;
508 pinctrl-names = "default", "gpio";
509 pinctrl-0 = <&pinctrl_i2c1_default>;
510 pinctrl-1 = <&pinctrl_i2c1_gpio>;
511 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
512 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
513
514 /* PL i2c via PCA9306 - u45 */
515 i2c-mux@74 { /* u34 */
516 compatible = "nxp,pca9548";
517 #address-cells = <1>;
518 #size-cells = <0>;
519 reg = <0x74>;
520 i2c@0 {
521 #address-cells = <1>;
522 #size-cells = <0>;
523 reg = <0>;
524 /*
525 * IIC_EEPROM 1kB memory which uses 256B blocks
526 * where every block has different address.
527 * 0 - 256B address 0x54
528 * 256B - 512B address 0x55
529 * 512B - 768B address 0x56
530 * 768B - 1024B address 0x57
531 */
532 eeprom: eeprom@54 { /* u23 */
533 compatible = "atmel,24c08";
534 reg = <0x54>;
535 };
536 };
537 i2c@1 {
538 #address-cells = <1>;
539 #size-cells = <0>;
540 reg = <1>;
541 si5341: clock-generator@36 { /* SI5341 - u69 */
542 compatible = "silabs,si5341";
543 reg = <0x36>;
544 #clock-cells = <2>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 clocks = <&ref48>;
548 clock-names = "xtal";
549 clock-output-names = "si5341";
550
551 si5341_0: out@0 {
552 /* refclk0 for PS-GT, used for DP */
553 reg = <0>;
554 always-on;
555 };
556 si5341_2: out@2 {
557 /* refclk2 for PS-GT, used for USB3 */
558 reg = <2>;
559 always-on;
560 };
561 si5341_3: out@3 {
562 /* refclk3 for PS-GT, used for SATA */
563 reg = <3>;
564 always-on;
565 };
566 si5341_6: out@6 {
567 /* refclk6 PL CLK125 */
568 reg = <6>;
569 always-on;
570 };
571 si5341_7: out@7 {
572 /* refclk7 PL CLK74 */
573 reg = <7>;
574 always-on;
575 };
576 si5341_9: out@9 {
577 /* refclk9 used for PS_REF_CLK 33.3 MHz */
578 reg = <9>;
579 always-on;
580 };
581 };
582
583 };
584 i2c@2 {
585 #address-cells = <1>;
586 #size-cells = <0>;
587 reg = <2>;
588 si570_1: clock-generator@5d { /* USER SI570 - u42 */
589 #clock-cells = <0>;
590 compatible = "silabs,si570";
591 reg = <0x5d>;
592 temperature-stability = <50>;
593 factory-fout = <300000000>;
594 clock-frequency = <300000000>;
595 clock-output-names = "si570_user";
596 };
597 };
598 i2c@3 {
599 #address-cells = <1>;
600 #size-cells = <0>;
601 reg = <3>;
602 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
603 #clock-cells = <0>;
604 compatible = "silabs,si570";
605 reg = <0x5d>;
606 temperature-stability = <50>; /* copy from zc702 */
607 factory-fout = <156250000>;
608 clock-frequency = <156250000>;
609 clock-output-names = "si570_mgt";
610 };
611 };
612 i2c@4 {
613 #address-cells = <1>;
614 #size-cells = <0>;
615 reg = <4>;
616 /* SI5328 - u20 */
617 };
618 i2c@5 {
619 #address-cells = <1>;
620 #size-cells = <0>;
621 reg = <5>; /* FAN controller */
622 temp@4c {/* lm96163 - u128 */
623 compatible = "national,lm96163";
624 reg = <0x4c>;
625 };
626 };
627 /* 6 - 7 unconnected */
628 };
629
630 i2c-mux@75 {
631 compatible = "nxp,pca9548"; /* u135 */
632 #address-cells = <1>;
633 #size-cells = <0>;
634 reg = <0x75>;
635
636 i2c@0 {
637 #address-cells = <1>;
638 #size-cells = <0>;
639 reg = <0>;
640 /* HPC0_IIC */
641 };
642 i2c@1 {
643 #address-cells = <1>;
644 #size-cells = <0>;
645 reg = <1>;
646 /* HPC1_IIC */
647 };
648 i2c@2 {
649 #address-cells = <1>;
650 #size-cells = <0>;
651 reg = <2>;
652 /* SYSMON */
653 };
654 i2c@3 {
655 #address-cells = <1>;
656 #size-cells = <0>;
657 reg = <3>;
658 /* DDR4 SODIMM */
659 };
660 i2c@4 {
661 #address-cells = <1>;
662 #size-cells = <0>;
663 reg = <4>;
664 /* SEP 3 */
665 };
666 i2c@5 {
667 #address-cells = <1>;
668 #size-cells = <0>;
669 reg = <5>;
670 /* SEP 2 */
671 };
672 i2c@6 {
673 #address-cells = <1>;
674 #size-cells = <0>;
675 reg = <6>;
676 /* SEP 1 */
677 };
678 i2c@7 {
679 #address-cells = <1>;
680 #size-cells = <0>;
681 reg = <7>;
682 /* SEP 0 */
683 };
684 };
685 };
686
687 &pinctrl0 {
688 status = "okay";
689 pinctrl_i2c0_default: i2c0-default {
690 mux {
691 groups = "i2c0_3_grp";
692 function = "i2c0";
693 };
694
695 conf {
696 groups = "i2c0_3_grp";
697 bias-pull-up;
698 slew-rate = <SLEW_RATE_SLOW>;
699 power-source = <IO_STANDARD_LVCMOS18>;
700 };
701 };
702
703 pinctrl_i2c0_gpio: i2c0-gpio-grp {
704 mux {
705 groups = "gpio0_14_grp", "gpio0_15_grp";
706 function = "gpio0";
707 };
708
709 conf {
710 groups = "gpio0_14_grp", "gpio0_15_grp";
711 slew-rate = <SLEW_RATE_SLOW>;
712 power-source = <IO_STANDARD_LVCMOS18>;
713 };
714 };
715
716 pinctrl_i2c1_default: i2c1-default {
717 mux {
718 groups = "i2c1_4_grp";
719 function = "i2c1";
720 };
721
722 conf {
723 groups = "i2c1_4_grp";
724 bias-pull-up;
725 slew-rate = <SLEW_RATE_SLOW>;
726 power-source = <IO_STANDARD_LVCMOS18>;
727 };
728 };
729
730 pinctrl_i2c1_gpio: i2c1-gpio-grp {
731 mux {
732 groups = "gpio0_16_grp", "gpio0_17_grp";
733 function = "gpio0";
734 };
735
736 conf {
737 groups = "gpio0_16_grp", "gpio0_17_grp";
738 slew-rate = <SLEW_RATE_SLOW>;
739 power-source = <IO_STANDARD_LVCMOS18>;
740 };
741 };
742
743 pinctrl_uart0_default: uart0-default {
744 mux {
745 groups = "uart0_4_grp";
746 function = "uart0";
747 };
748
749 conf {
750 groups = "uart0_4_grp";
751 slew-rate = <SLEW_RATE_SLOW>;
752 power-source = <IO_STANDARD_LVCMOS18>;
753 };
754
755 conf-rx {
756 pins = "MIO18";
757 bias-high-impedance;
758 };
759
760 conf-tx {
761 pins = "MIO19";
762 bias-disable;
763 };
764 };
765
766 pinctrl_uart1_default: uart1-default {
767 mux {
768 groups = "uart1_5_grp";
769 function = "uart1";
770 };
771
772 conf {
773 groups = "uart1_5_grp";
774 slew-rate = <SLEW_RATE_SLOW>;
775 power-source = <IO_STANDARD_LVCMOS18>;
776 };
777
778 conf-rx {
779 pins = "MIO21";
780 bias-high-impedance;
781 };
782
783 conf-tx {
784 pins = "MIO20";
785 bias-disable;
786 };
787 };
788
789 pinctrl_usb0_default: usb0-default {
790 mux {
791 groups = "usb0_0_grp";
792 function = "usb0";
793 };
794
795 conf {
796 groups = "usb0_0_grp";
797 power-source = <IO_STANDARD_LVCMOS18>;
798 };
799
800 conf-rx {
801 pins = "MIO52", "MIO53", "MIO55";
802 bias-high-impedance;
803 drive-strength = <12>;
804 slew-rate = <SLEW_RATE_FAST>;
805 };
806
807 conf-tx {
808 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
809 "MIO60", "MIO61", "MIO62", "MIO63";
810 bias-disable;
811 drive-strength = <4>;
812 slew-rate = <SLEW_RATE_SLOW>;
813 };
814 };
815
816 pinctrl_gem3_default: gem3-default {
817 mux {
818 function = "ethernet3";
819 groups = "ethernet3_0_grp";
820 };
821
822 conf {
823 groups = "ethernet3_0_grp";
824 slew-rate = <SLEW_RATE_SLOW>;
825 power-source = <IO_STANDARD_LVCMOS18>;
826 };
827
828 conf-rx {
829 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
830 "MIO75";
831 bias-high-impedance;
832 low-power-disable;
833 };
834
835 conf-tx {
836 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
837 "MIO69";
838 bias-disable;
839 low-power-enable;
840 };
841
842 mux-mdio {
843 function = "mdio3";
844 groups = "mdio3_0_grp";
845 };
846
847 conf-mdio {
848 groups = "mdio3_0_grp";
849 slew-rate = <SLEW_RATE_SLOW>;
850 power-source = <IO_STANDARD_LVCMOS18>;
851 bias-disable;
852 };
853 };
854
855 pinctrl_can1_default: can1-default {
856 mux {
857 function = "can1";
858 groups = "can1_6_grp";
859 };
860
861 conf {
862 groups = "can1_6_grp";
863 slew-rate = <SLEW_RATE_SLOW>;
864 power-source = <IO_STANDARD_LVCMOS18>;
865 };
866
867 conf-rx {
868 pins = "MIO25";
869 bias-high-impedance;
870 };
871
872 conf-tx {
873 pins = "MIO24";
874 bias-disable;
875 };
876 };
877
878 pinctrl_sdhci1_default: sdhci1-default {
879 mux {
880 groups = "sdio1_0_grp";
881 function = "sdio1";
882 };
883
884 conf {
885 groups = "sdio1_0_grp";
886 slew-rate = <SLEW_RATE_SLOW>;
887 power-source = <IO_STANDARD_LVCMOS18>;
888 bias-disable;
889 };
890
891 mux-cd {
892 groups = "sdio1_cd_0_grp";
893 function = "sdio1_cd";
894 };
895
896 conf-cd {
897 groups = "sdio1_cd_0_grp";
898 bias-high-impedance;
899 bias-pull-up;
900 slew-rate = <SLEW_RATE_SLOW>;
901 power-source = <IO_STANDARD_LVCMOS18>;
902 };
903
904 mux-wp {
905 groups = "sdio1_wp_0_grp";
906 function = "sdio1_wp";
907 };
908
909 conf-wp {
910 groups = "sdio1_wp_0_grp";
911 bias-high-impedance;
912 bias-pull-up;
913 slew-rate = <SLEW_RATE_SLOW>;
914 power-source = <IO_STANDARD_LVCMOS18>;
915 };
916 };
917
918 pinctrl_gpio_default: gpio-default {
919 mux {
920 function = "gpio0";
921 groups = "gpio0_22_grp", "gpio0_23_grp";
922 };
923
924 conf {
925 groups = "gpio0_22_grp", "gpio0_23_grp";
926 slew-rate = <SLEW_RATE_SLOW>;
927 power-source = <IO_STANDARD_LVCMOS18>;
928 };
929
930 mux-msp {
931 function = "gpio0";
932 groups = "gpio0_13_grp", "gpio0_38_grp";
933 };
934
935 conf-msp {
936 groups = "gpio0_13_grp", "gpio0_38_grp";
937 slew-rate = <SLEW_RATE_SLOW>;
938 power-source = <IO_STANDARD_LVCMOS18>;
939 };
940
941 conf-pull-up {
942 pins = "MIO22";
943 bias-pull-up;
944 };
945
946 conf-pull-none {
947 pins = "MIO13", "MIO23", "MIO38";
948 bias-disable;
949 };
950 };
951 };
952
953 &psgtr {
954 status = "okay";
955 /* nc, sata, usb3, dp */
956 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
957 clock-names = "ref1", "ref2", "ref3";
958 };
959
960 &qspi {
961 status = "okay";
962 flash@0 {
963 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
964 #address-cells = <1>;
965 #size-cells = <1>;
966 reg = <0x0>;
967 spi-tx-bus-width = <4>;
968 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
969 spi-max-frequency = <108000000>; /* Based on DC1 spec */
970 };
971 };
972
973 &rtc {
974 status = "okay";
975 };
976
977 &sata {
978 status = "okay";
979 /* SATA OOB timing settings */
980 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
981 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
982 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
983 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
984 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
985 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
986 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
987 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
988 phy-names = "sata-phy";
989 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
990 };
991
992 /* SD1 with level shifter */
993 &sdhci1 {
994 status = "okay";
995 /*
996 * This property should be removed for supporting UHS mode
997 */
998 no-1-8-v;
999 pinctrl-names = "default";
1000 pinctrl-0 = <&pinctrl_sdhci1_default>;
1001 xlnx,mio-bank = <1>;
1002 };
1003
1004 &uart0 {
1005 status = "okay";
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&pinctrl_uart0_default>;
1008 };
1009
1010 &uart1 {
1011 status = "okay";
1012 pinctrl-names = "default";
1013 pinctrl-0 = <&pinctrl_uart1_default>;
1014 };
1015
1016 /* ULPI SMSC USB3320 */
1017 &usb0 {
1018 status = "okay";
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&pinctrl_usb0_default>;
1021 phy-names = "usb3-phy";
1022 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
1023 };
1024
1025 &dwc3_0 {
1026 status = "okay";
1027 dr_mode = "host";
1028 snps,usb3_lpm_capable;
1029 maximum-speed = "super-speed";
1030 };
1031
1032 &watchdog0 {
1033 status = "okay";
1034 };
1035
1036 &zynqmp_dpdma {
1037 status = "okay";
1038 };
1039
1040 &zynqmp_dpsub {
1041 status = "okay";
1042 phy-names = "dp-phy0", "dp-phy1";
1043 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
1044 <&psgtr 0 PHY_TYPE_DP 1 3>;
1045
1046 ports {
1047 port@5 {
1048 dpsub_dp_out: endpoint {
1049 remote-endpoint = <&dpcon_in>;
1050 };
1051 };
1052 };
1053 };
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