1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ARM64_KVM_ARM_H__
8 #define __ARM64_KVM_ARM_H__
9
10 #include <asm/esr.h>
11 #include <asm/memory.h>
12 #include <asm/sysreg.h>
13 #include <asm/types.h>
14
15 /* Hyp Configuration Register (HCR) bits */
16
17 #define HCR_TID5 (UL(1) << 58)
18 #define HCR_DCT (UL(1) << 57)
19 #define HCR_ATA_SHIFT 56
20 #define HCR_ATA (UL(1) << HCR_ATA_SHIFT)
21 #define HCR_TTLBOS (UL(1) << 55)
22 #define HCR_TTLBIS (UL(1) << 54)
23 #define HCR_ENSCXT (UL(1) << 53)
24 #define HCR_TOCU (UL(1) << 52)
25 #define HCR_AMVOFFEN (UL(1) << 51)
26 #define HCR_TICAB (UL(1) << 50)
27 #define HCR_TID4 (UL(1) << 49)
28 #define HCR_FIEN (UL(1) << 47)
29 #define HCR_FWB (UL(1) << 46)
30 #define HCR_NV2 (UL(1) << 45)
31 #define HCR_AT (UL(1) << 44)
32 #define HCR_NV1 (UL(1) << 43)
33 #define HCR_NV (UL(1) << 42)
34 #define HCR_API (UL(1) << 41)
35 #define HCR_APK (UL(1) << 40)
36 #define HCR_TEA (UL(1) << 37)
37 #define HCR_TERR (UL(1) << 36)
38 #define HCR_TLOR (UL(1) << 35)
39 #define HCR_E2H (UL(1) << 34)
40 #define HCR_ID (UL(1) << 33)
41 #define HCR_CD (UL(1) << 32)
42 #define HCR_RW_SHIFT 31
43 #define HCR_RW (UL(1) << HCR_RW_SHIFT)
44 #define HCR_TRVM (UL(1) << 30)
45 #define HCR_HCD (UL(1) << 29)
46 #define HCR_TDZ (UL(1) << 28)
47 #define HCR_TGE (UL(1) << 27)
48 #define HCR_TVM (UL(1) << 26)
49 #define HCR_TTLB (UL(1) << 25)
50 #define HCR_TPU (UL(1) << 24)
51 #define HCR_TPC (UL(1) << 23) /* HCR_TPCP if FEAT_DPB */
52 #define HCR_TSW (UL(1) << 22)
53 #define HCR_TACR (UL(1) << 21)
54 #define HCR_TIDCP (UL(1) << 20)
55 #define HCR_TSC (UL(1) << 19)
56 #define HCR_TID3 (UL(1) << 18)
57 #define HCR_TID2 (UL(1) << 17)
58 #define HCR_TID1 (UL(1) << 16)
59 #define HCR_TID0 (UL(1) << 15)
60 #define HCR_TWE (UL(1) << 14)
61 #define HCR_TWI (UL(1) << 13)
62 #define HCR_DC (UL(1) << 12)
63 #define HCR_BSU (3 << 10)
64 #define HCR_BSU_IS (UL(1) << 10)
65 #define HCR_FB (UL(1) << 9)
66 #define HCR_VSE (UL(1) << 8)
67 #define HCR_VI (UL(1) << 7)
68 #define HCR_VF (UL(1) << 6)
69 #define HCR_AMO (UL(1) << 5)
70 #define HCR_IMO (UL(1) << 4)
71 #define HCR_FMO (UL(1) << 3)
72 #define HCR_PTW (UL(1) << 2)
73 #define HCR_SWIO (UL(1) << 1)
74 #define HCR_VM (UL(1) << 0)
75 #define HCR_RES0 ((UL(1) << 48) | (UL(1) << 39))
76
77 /*
78 * The bits we set in HCR:
79 * TLOR: Trap LORegion register accesses
80 * RW: 64bit by default, can be overridden for 32bit VMs
81 * TACR: Trap ACTLR
82 * TSC: Trap SMC
83 * TSW: Trap cache operations by set/way
84 * TWE: Trap WFE
85 * TWI: Trap WFI
86 * TIDCP: Trap L2CTLR/L2ECTLR
87 * BSU_IS: Upgrade barriers to the inner shareable domain
88 * FB: Force broadcast of all maintenance operations
89 * AMO: Override CPSR.A and enable signaling with VA
90 * IMO: Override CPSR.I and enable signaling with VI
91 * FMO: Override CPSR.F and enable signaling with VF
92 * SWIO: Turn set/way invalidates into set/way clean+invalidate
93 * PTW: Take a stage2 fault if a stage1 walk steps in device memory
94 * TID3: Trap EL1 reads of group 3 ID registers
95 * TID2: Trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1
96 */
97 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
98 HCR_BSU_IS | HCR_FB | HCR_TACR | \
99 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
100 HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3)
101 #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA)
102 #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)
103 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
104
105 #define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM)
106
107 /* TCR_EL2 Registers bits */
108 #define TCR_EL2_DS (1UL << 32)
109 #define TCR_EL2_RES1 ((1U << 31) | (1 << 23))
110 #define TCR_EL2_TBI (1 << 20)
111 #define TCR_EL2_PS_SHIFT 16
112 #define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT)
113 #define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT)
114 #define TCR_EL2_TG0_MASK TCR_TG0_MASK
115 #define TCR_EL2_SH0_MASK TCR_SH0_MASK
116 #define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
117 #define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
118 #define TCR_EL2_T0SZ_MASK 0x3f
119 #define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
120 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
121
122 /* VTCR_EL2 Registers bits */
123 #define VTCR_EL2_DS TCR_EL2_DS
124 #define VTCR_EL2_RES1 (1U << 31)
125 #define VTCR_EL2_HD (1 << 22)
126 #define VTCR_EL2_HA (1 << 21)
127 #define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT
128 #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK
129 #define VTCR_EL2_TG0_MASK TCR_TG0_MASK
130 #define VTCR_EL2_TG0_4K TCR_TG0_4K
131 #define VTCR_EL2_TG0_16K TCR_TG0_16K
132 #define VTCR_EL2_TG0_64K TCR_TG0_64K
133 #define VTCR_EL2_SH0_MASK TCR_SH0_MASK
134 #define VTCR_EL2_SH0_INNER TCR_SH0_INNER
135 #define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
136 #define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA
137 #define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
138 #define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA
139 #define VTCR_EL2_SL0_SHIFT 6
140 #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT)
141 #define VTCR_EL2_T0SZ_MASK 0x3f
142 #define VTCR_EL2_VS_SHIFT 19
143 #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT)
144 #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT)
145
146 #define VTCR_EL2_T0SZ(x) TCR_T0SZ(x)
147
148 /*
149 * We configure the Stage-2 page tables to always restrict the IPA space to be
150 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
151 * not known to exist and will break with this configuration.
152 *
153 * The VTCR_EL2 is configured per VM and is initialised in kvm_init_stage2_mmu.
154 *
155 * Note that when using 4K pages, we concatenate two first level page tables
156 * together. With 16K pages, we concatenate 16 first level page tables.
157 *
158 */
159
160 #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
161 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
162
163 /*
164 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation.
165 * Interestingly, it depends on the page size.
166 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
167 *
168 * -----------------------------------------
169 * | Entry level | 4K | 16K/64K |
170 * ------------------------------------------
171 * | Level: 0 | 2 | - |
172 * ------------------------------------------
173 * | Level: 1 | 1 | 2 |
174 * ------------------------------------------
175 * | Level: 2 | 0 | 1 |
176 * ------------------------------------------
177 * | Level: 3 | - | 0 |
178 * ------------------------------------------
179 *
180 * The table roughly translates to :
181 *
182 * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
183 *
184 * Where TGRAN_SL0_BASE is a magic number depending on the page size:
185 * TGRAN_SL0_BASE(4K) = 2
186 * TGRAN_SL0_BASE(16K) = 3
187 * TGRAN_SL0_BASE(64K) = 3
188 * provided we take care of ruling out the unsupported cases and
189 * Entry_Level = 4 - Number_of_levels.
190 *
191 */
192 #ifdef CONFIG_ARM64_64K_PAGES
193
194 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K
195 #define VTCR_EL2_TGRAN_SL0_BASE 3UL
196
197 #elif defined(CONFIG_ARM64_16K_PAGES)
198
199 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K
200 #define VTCR_EL2_TGRAN_SL0_BASE 3UL
201
202 #else /* 4K */
203
204 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K
205 #define VTCR_EL2_TGRAN_SL0_BASE 2UL
206
207 #endif
208
209 #define VTCR_EL2_LVLS_TO_SL0(levels) \
210 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
211 #define VTCR_EL2_SL0_TO_LVLS(sl0) \
212 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
213 #define VTCR_EL2_LVLS(vtcr) \
214 VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT)
215
216 #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN)
217 #define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
218
219 /*
220 * ARM VMSAv8-64 defines an algorithm for finding the translation table
221 * descriptors in section D4.2.8 in ARM DDI 0487C.a.
222 *
223 * The algorithm defines the expectations on the translation table
224 * addresses for each level, based on PAGE_SIZE, entry level
225 * and the translation table size (T0SZ). The variable "x" in the
226 * algorithm determines the alignment of a table base address at a given
227 * level and thus determines the alignment of VTTBR:BADDR for stage2
228 * page table entry level.
229 * Since the number of bits resolved at the entry level could vary
230 * depending on the T0SZ, the value of "x" is defined based on a
231 * Magic constant for a given PAGE_SIZE and Entry Level. The
232 * intermediate levels must be always aligned to the PAGE_SIZE (i.e,
233 * x = PAGE_SHIFT).
234 *
235 * The value of "x" for entry level is calculated as :
236 * x = Magic_N - T0SZ
237 *
238 * where Magic_N is an integer depending on the page size and the entry
239 * level of the page table as below:
240 *
241 * --------------------------------------------
242 * | Entry level | 4K 16K 64K |
243 * --------------------------------------------
244 * | Level: 0 (4 levels) | 28 | - | - |
245 * --------------------------------------------
246 * | Level: 1 (3 levels) | 37 | 31 | 25 |
247 * --------------------------------------------
248 * | Level: 2 (2 levels) | 46 | 42 | 38 |
249 * --------------------------------------------
250 * | Level: 3 (1 level) | - | 53 | 51 |
251 * --------------------------------------------
252 *
253 * We have a magic formula for the Magic_N below:
254 *
255 * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
256 *
257 * where Number_of_levels = (4 - Level). We are only interested in the
258 * value for Entry_Level for the stage2 page table.
259 *
260 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
261 *
262 * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
263 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
264 *
265 * Here is one way to explain the Magic Formula:
266 *
267 * x = log2(Size_of_Entry_Level_Table)
268 *
269 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
270 * PAGE_SHIFT bits in the PTE, we have :
271 *
272 * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
273 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
274 * where n = number of levels, and since each pointer is 8bytes, we have:
275 *
276 * x = Bits_Entry_Level + 3
277 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n
278 *
279 * The only constraint here is that, we have to find the number of page table
280 * levels for a given IPA size (which we do, see stage2_pt_levels())
281 */
282 #define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3)))
283
284 #define VTTBR_CNP_BIT (UL(1))
285 #define VTTBR_VMID_SHIFT (UL(48))
286 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
287
288 /* Hyp System Trap Register */
289 #define HSTR_EL2_T(x) (1 << x)
290
291 /* Hyp Coprocessor Trap Register Shifts */
292 #define CPTR_EL2_TFP_SHIFT 10
293
294 /* Hyp Coprocessor Trap Register */
295 #define CPTR_EL2_TCPAC (1U << 31)
296 #define CPTR_EL2_TAM (1 << 30)
297 #define CPTR_EL2_TTA (1 << 20)
298 #define CPTR_EL2_TSM (1 << 12)
299 #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT)
300 #define CPTR_EL2_TZ (1 << 8)
301 #define CPTR_NVHE_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */
302 #define CPTR_NVHE_EL2_RES0 (GENMASK(63, 32) | \
303 GENMASK(29, 21) | \
304 GENMASK(19, 14) | \
305 BIT(11))
306
307 #define CPTR_VHE_EL2_RES0 (GENMASK(63, 32) | \
308 GENMASK(27, 26) | \
309 GENMASK(23, 22) | \
310 GENMASK(19, 18) | \
311 GENMASK(15, 0))
312
313 /* Hyp Debug Configuration Register bits */
314 #define MDCR_EL2_E2TB_MASK (UL(0x3))
315 #define MDCR_EL2_E2TB_SHIFT (UL(24))
316 #define MDCR_EL2_HPMFZS (UL(1) << 36)
317 #define MDCR_EL2_HPMFZO (UL(1) << 29)
318 #define MDCR_EL2_MTPME (UL(1) << 28)
319 #define MDCR_EL2_TDCC (UL(1) << 27)
320 #define MDCR_EL2_HLP (UL(1) << 26)
321 #define MDCR_EL2_HCCD (UL(1) << 23)
322 #define MDCR_EL2_TTRF (UL(1) << 19)
323 #define MDCR_EL2_HPMD (UL(1) << 17)
324 #define MDCR_EL2_TPMS (UL(1) << 14)
325 #define MDCR_EL2_E2PB_MASK (UL(0x3))
326 #define MDCR_EL2_E2PB_SHIFT (UL(12))
327 #define MDCR_EL2_TDRA (UL(1) << 11)
328 #define MDCR_EL2_TDOSA (UL(1) << 10)
329 #define MDCR_EL2_TDA (UL(1) << 9)
330 #define MDCR_EL2_TDE (UL(1) << 8)
331 #define MDCR_EL2_HPME (UL(1) << 7)
332 #define MDCR_EL2_TPM (UL(1) << 6)
333 #define MDCR_EL2_TPMCR (UL(1) << 5)
334 #define MDCR_EL2_HPMN_MASK (UL(0x1F))
335 #define MDCR_EL2_RES0 (GENMASK(63, 37) | \
336 GENMASK(35, 30) | \
337 GENMASK(25, 24) | \
338 GENMASK(22, 20) | \
339 BIT(18) | \
340 GENMASK(16, 15))
341
342 /*
343 * FGT register definitions
344 *
345 * RES0 and polarity masks as of DDI0487J.a, to be updated as needed.
346 * We're not using the generated masks as they are usually ahead of
347 * the published ARM ARM, which we use as a reference.
348 *
349 * Once we get to a point where the two describe the same thing, we'll
350 * merge the definitions. One day.
351 */
352 #define __HFGRTR_EL2_RES0 HFGxTR_EL2_RES0
353 #define __HFGRTR_EL2_MASK GENMASK(49, 0)
354 #define __HFGRTR_EL2_nMASK ~(__HFGRTR_EL2_RES0 | __HFGRTR_EL2_MASK)
355
356 /*
357 * The HFGWTR bits are a subset of HFGRTR bits. To ensure we don't miss any
358 * future additions, define __HFGWTR* macros relative to __HFGRTR* ones.
359 */
360 #define __HFGRTR_ONLY_MASK (BIT(46) | BIT(42) | BIT(40) | BIT(28) | \
361 GENMASK(26, 25) | BIT(21) | BIT(18) | \
362 GENMASK(15, 14) | GENMASK(10, 9) | BIT(2))
363 #define __HFGWTR_EL2_RES0 (__HFGRTR_EL2_RES0 | __HFGRTR_ONLY_MASK)
364 #define __HFGWTR_EL2_MASK (__HFGRTR_EL2_MASK & ~__HFGRTR_ONLY_MASK)
365 #define __HFGWTR_EL2_nMASK ~(__HFGWTR_EL2_RES0 | __HFGWTR_EL2_MASK)
366
367 #define __HFGITR_EL2_RES0 HFGITR_EL2_RES0
368 #define __HFGITR_EL2_MASK (BIT(62) | BIT(60) | GENMASK(54, 0))
369 #define __HFGITR_EL2_nMASK ~(__HFGITR_EL2_RES0 | __HFGITR_EL2_MASK)
370
371 #define __HDFGRTR_EL2_RES0 HDFGRTR_EL2_RES0
372 #define __HDFGRTR_EL2_MASK (BIT(63) | GENMASK(58, 50) | GENMASK(48, 43) | \
373 GENMASK(41, 40) | GENMASK(37, 22) | \
374 GENMASK(19, 9) | GENMASK(7, 0))
375 #define __HDFGRTR_EL2_nMASK ~(__HDFGRTR_EL2_RES0 | __HDFGRTR_EL2_MASK)
376
377 #define __HDFGWTR_EL2_RES0 HDFGWTR_EL2_RES0
378 #define __HDFGWTR_EL2_MASK (GENMASK(57, 52) | GENMASK(50, 48) | \
379 GENMASK(46, 44) | GENMASK(42, 41) | \
380 GENMASK(37, 35) | GENMASK(33, 31) | \
381 GENMASK(29, 23) | GENMASK(21, 10) | \
382 GENMASK(8, 7) | GENMASK(5, 0))
383 #define __HDFGWTR_EL2_nMASK ~(__HDFGWTR_EL2_RES0 | __HDFGWTR_EL2_MASK)
384
385 #define __HAFGRTR_EL2_RES0 HAFGRTR_EL2_RES0
386 #define __HAFGRTR_EL2_MASK (GENMASK(49, 17) | GENMASK(4, 0))
387 #define __HAFGRTR_EL2_nMASK ~(__HAFGRTR_EL2_RES0 | __HAFGRTR_EL2_MASK)
388
389 /* Similar definitions for HCRX_EL2 */
390 #define __HCRX_EL2_RES0 HCRX_EL2_RES0
391 #define __HCRX_EL2_MASK (BIT(6))
392 #define __HCRX_EL2_nMASK ~(__HCRX_EL2_RES0 | __HCRX_EL2_MASK)
393
394 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
395 #define HPFAR_MASK (~UL(0xf))
396 /*
397 * We have
398 * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12]
399 * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12]
400 *
401 * Always assume 52 bit PA since at this point, we don't know how many PA bits
402 * the page table has been set up for. This should be safe since unused address
403 * bits in PAR are res0.
404 */
405 #define PAR_TO_HPFAR(par) \
406 (((par) & GENMASK_ULL(52 - 1, 12)) >> 8)
407
408 #define ECN(x) { ESR_ELx_EC_##x, #x }
409
410 #define kvm_arm_exception_class \
411 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
412 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \
413 ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \
414 ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \
415 ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
416 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
417 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
418 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
419 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64), ECN(ERET)
420
421 #define CPACR_EL1_TTA (1 << 28)
422
423 #define kvm_mode_names \
424 { PSR_MODE_EL0t, "EL0t" }, \
425 { PSR_MODE_EL1t, "EL1t" }, \
426 { PSR_MODE_EL1h, "EL1h" }, \
427 { PSR_MODE_EL2t, "EL2t" }, \
428 { PSR_MODE_EL2h, "EL2h" }, \
429 { PSR_MODE_EL3t, "EL3t" }, \
430 { PSR_MODE_EL3h, "EL3h" }, \
431 { PSR_AA32_MODE_USR, "32-bit USR" }, \
432 { PSR_AA32_MODE_FIQ, "32-bit FIQ" }, \
433 { PSR_AA32_MODE_IRQ, "32-bit IRQ" }, \
434 { PSR_AA32_MODE_SVC, "32-bit SVC" }, \
435 { PSR_AA32_MODE_ABT, "32-bit ABT" }, \
436 { PSR_AA32_MODE_HYP, "32-bit HYP" }, \
437 { PSR_AA32_MODE_UND, "32-bit UND" }, \
438 { PSR_AA32_MODE_SYS, "32-bit SYS" }
439
440 #endif /* __ARM64_KVM_ARM_H__ */
441
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