1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 *
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
11 *
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
21 *
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
28 *
29 * Some implementation details worth remembering:
30 *
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
33 *
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
37 *
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
42 *
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
45 *
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
49 *
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
55 * details.
56 *
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
60 * KVM guests.
61 */
62
63 #define pr_fmt(fmt) "CPU features: " fmt
64
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/kstrtox.h>
69 #include <linux/sort.h>
70 #include <linux/stop_machine.h>
71 #include <linux/sysfs.h>
72 #include <linux/types.h>
73 #include <linux/minmax.h>
74 #include <linux/mm.h>
75 #include <linux/cpu.h>
76 #include <linux/kasan.h>
77 #include <linux/percpu.h>
78
79 #include <asm/cpu.h>
80 #include <asm/cpufeature.h>
81 #include <asm/cpu_ops.h>
82 #include <asm/fpsimd.h>
83 #include <asm/hwcap.h>
84 #include <asm/insn.h>
85 #include <asm/kvm_host.h>
86 #include <asm/mmu_context.h>
87 #include <asm/mte.h>
88 #include <asm/processor.h>
89 #include <asm/smp.h>
90 #include <asm/sysreg.h>
91 #include <asm/traps.h>
92 #include <asm/vectors.h>
93 #include <asm/virt.h>
94
95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly;
97
98 #ifdef CONFIG_COMPAT
99 #define COMPAT_ELF_HWCAP_DEFAULT \
100 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
101 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
102 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
103 COMPAT_HWCAP_LPAE)
104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
105 unsigned int compat_elf_hwcap2 __read_mostly;
106 #endif
107
108 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS);
109 EXPORT_SYMBOL(system_cpucaps);
110 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS];
111
112 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS);
113
114 bool arm64_use_ng_mappings = false;
115 EXPORT_SYMBOL(arm64_use_ng_mappings);
116
117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
118
119 /*
120 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
121 * support it?
122 */
123 static bool __read_mostly allow_mismatched_32bit_el0;
124
125 /*
126 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have
127 * seen at least one CPU capable of 32-bit EL0.
128 */
129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
130
131 /*
132 * Mask of CPUs supporting 32-bit EL0.
133 * Only valid if arm64_mismatched_32bit_el0 is enabled.
134 */
135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
136
137 void dump_cpu_features(void)
138 {
139 /* file-wide pr_fmt adds "CPU features: " prefix */
140 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps);
141 }
142
143 #define __ARM64_MAX_POSITIVE(reg, field) \
144 ((reg##_##field##_SIGNED ? \
145 BIT(reg##_##field##_WIDTH - 1) : \
146 BIT(reg##_##field##_WIDTH)) - 1)
147
148 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1)
149
150 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \
151 .sys_reg = SYS_##reg, \
152 .field_pos = reg##_##field##_SHIFT, \
153 .field_width = reg##_##field##_WIDTH, \
154 .sign = reg##_##field##_SIGNED, \
155 .min_field_value = min_value, \
156 .max_field_value = max_value,
157
158 /*
159 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to
160 * an implicit maximum that depends on the sign-ess of the field.
161 *
162 * An unsigned field will be capped at all ones, while a signed field
163 * will be limited to the positive half only.
164 */
165 #define ARM64_CPUID_FIELDS(reg, field, min_value) \
166 __ARM64_CPUID_FIELDS(reg, field, \
167 SYS_FIELD_VALUE(reg, field, min_value), \
168 __ARM64_MAX_POSITIVE(reg, field))
169
170 /*
171 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an
172 * implicit minimal value to max_value. This should be used when
173 * matching a non-implemented property.
174 */
175 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \
176 __ARM64_CPUID_FIELDS(reg, field, \
177 __ARM64_MIN_NEGATIVE(reg, field), \
178 SYS_FIELD_VALUE(reg, field, max_value))
179
180 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
181 { \
182 .sign = SIGNED, \
183 .visible = VISIBLE, \
184 .strict = STRICT, \
185 .type = TYPE, \
186 .shift = SHIFT, \
187 .width = WIDTH, \
188 .safe_val = SAFE_VAL, \
189 }
190
191 /* Define a feature with unsigned values */
192 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
193 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
194
195 /* Define a feature with a signed value */
196 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
197 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
198
199 #define ARM64_FTR_END \
200 { \
201 .width = 0, \
202 }
203
204 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
205
206 static bool __system_matches_cap(unsigned int n);
207
208 /*
209 * NOTE: Any changes to the visibility of features should be kept in
210 * sync with the documentation of the CPU feature register ABI.
211 */
212 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0),
214 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0),
215 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0),
216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0),
219 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0),
220 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0),
221 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0),
222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0),
223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0),
225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0),
226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0),
227 ARM64_FTR_END,
228 };
229
230 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0),
232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0),
233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0),
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0),
236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0),
237 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
238 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0),
239 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
240 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0),
241 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0),
244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
245 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0),
246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
247 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0),
248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0),
249 ARM64_FTR_END,
250 };
251
252 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0),
254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0),
257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
258 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0),
259 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
260 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
261 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
262 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0),
263 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0),
264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0),
265 ARM64_FTR_END,
266 };
267
268 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = {
269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0),
270 ARM64_FTR_END,
271 };
272
273 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
274 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0),
275 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0),
276 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0),
277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0),
278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0),
279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0),
280 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
281 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0),
282 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0),
283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0),
284 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI),
285 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI),
286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0),
287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0),
288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP),
289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP),
290 ARM64_FTR_END,
291 };
292
293 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
294 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
295 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0),
296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0),
297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0),
298 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
299 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI),
300 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI),
301 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
302 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0),
303 ARM64_FTR_END,
304 };
305
306 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = {
307 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0),
308 ARM64_FTR_END,
309 };
310
311 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
312 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
313 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0),
314 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
315 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0),
316 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
317 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0),
318 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
319 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0),
320 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
321 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0),
322 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
323 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0),
324 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
325 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0),
326 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
327 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0),
328 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
329 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0),
330 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
331 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0),
332 ARM64_FTR_END,
333 };
334
335 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
336 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
337 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0),
338 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
339 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0),
340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
341 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0),
342 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
343 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0),
344 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
345 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0),
346 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
347 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0),
348 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
349 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0),
350 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
351 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0),
352 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
353 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0),
354 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
355 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0),
356 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
357 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0),
358 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
359 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0),
360 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
361 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0),
362 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
363 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0),
364 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
365 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0),
366 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
367 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0),
368 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
369 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0),
370 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
371 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0),
372 ARM64_FTR_END,
373 };
374
375 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = {
376 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0),
377 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0),
378 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0),
379 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0),
380 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0),
381 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0),
382 ARM64_FTR_END,
383 };
384
385 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
386 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0),
387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0),
388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0),
389 /*
390 * Page size not being supported at Stage-2 is not fatal. You
391 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
392 * your favourite nesting hypervisor.
393 *
394 * There is a small corner case where the hypervisor explicitly
395 * advertises a given granule size at Stage-2 (value 2) on some
396 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
397 * vCPUs. Although this is not forbidden by the architecture, it
398 * indicates that the hypervisor is being silly (or buggy).
399 *
400 * We make no effort to cope with this and pretend that if these
401 * fields are inconsistent across vCPUs, then it isn't worth
402 * trying to bring KVM up.
403 */
404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1),
405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1),
406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1),
407 /*
408 * We already refuse to boot CPUs that don't support our configured
409 * page size, so we can only detect mismatches for a page size other
410 * than the one we're currently using. Unfortunately, SoCs like this
411 * exist in the wild so, even though we don't like it, we'll have to go
412 * along with it and treat them as non-strict.
413 */
414 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI),
415 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI),
416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI),
417
418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0),
419 /* Linux shouldn't care about secure memory */
420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0),
421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0),
422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0),
423 /*
424 * Differing PARange is fine as long as all peripherals and memory are mapped
425 * within the minimum PARange of all CPUs
426 */
427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0),
428 ARM64_FTR_END,
429 };
430
431 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0),
433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0),
434 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0),
435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0),
436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0),
437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0),
438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0),
439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0),
440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0),
441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0),
442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0),
443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0),
444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0),
445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0),
446 ARM64_FTR_END,
447 };
448
449 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0),
451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0),
452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0),
453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0),
454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0),
455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0),
456 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0),
457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0),
458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0),
459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0),
460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0),
461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0),
462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0),
463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0),
464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0),
465 ARM64_FTR_END,
466 };
467
468 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {
469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0),
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0),
471 ARM64_FTR_END,
472 };
473
474 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = {
475 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0),
476 ARM64_FTR_END,
477 };
478
479 static const struct arm64_ftr_bits ftr_ctr[] = {
480 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
481 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1),
482 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1),
483 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0),
484 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0),
485 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1),
486 /*
487 * Linux can handle differing I-cache policies. Userspace JITs will
488 * make use of *minLine.
489 * If we have differing I-cache policies, report it as the weakest - VIPT.
490 */
491 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */
492 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0),
493 ARM64_FTR_END,
494 };
495
496 static struct arm64_ftr_override __ro_after_init no_override = { };
497
498 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
499 .name = "SYS_CTR_EL0",
500 .ftr_bits = ftr_ctr,
501 .override = &no_override,
502 };
503
504 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
505 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf),
506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0),
507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0),
508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0),
509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0),
510 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf),
511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0),
512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0),
513 ARM64_FTR_END,
514 };
515
516 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
517 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0),
518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0),
519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0),
520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0),
521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0),
522 /*
523 * We can instantiate multiple PMU instances with different levels
524 * of support.
525 */
526 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0),
527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6),
528 ARM64_FTR_END,
529 };
530
531 static const struct arm64_ftr_bits ftr_mvfr0[] = {
532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0),
533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0),
534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0),
535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0),
536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0),
537 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0),
538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0),
539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0),
540 ARM64_FTR_END,
541 };
542
543 static const struct arm64_ftr_bits ftr_mvfr1[] = {
544 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0),
545 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0),
546 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0),
547 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0),
548 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0),
549 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0),
550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0),
551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0),
552 ARM64_FTR_END,
553 };
554
555 static const struct arm64_ftr_bits ftr_mvfr2[] = {
556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0),
557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0),
558 ARM64_FTR_END,
559 };
560
561 static const struct arm64_ftr_bits ftr_dczid[] = {
562 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1),
563 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0),
564 ARM64_FTR_END,
565 };
566
567 static const struct arm64_ftr_bits ftr_gmid[] = {
568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0),
569 ARM64_FTR_END,
570 };
571
572 static const struct arm64_ftr_bits ftr_id_isar0[] = {
573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0),
574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0),
575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0),
576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0),
577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0),
578 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0),
579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0),
580 ARM64_FTR_END,
581 };
582
583 static const struct arm64_ftr_bits ftr_id_isar5[] = {
584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0),
585 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0),
586 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0),
587 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0),
588 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0),
589 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0),
590 ARM64_FTR_END,
591 };
592
593 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
594 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0),
595 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0),
596 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0),
597 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0),
598 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0),
599 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0),
600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0),
601
602 /*
603 * SpecSEI = 1 indicates that the PE might generate an SError on an
604 * external abort on speculative read. It is safe to assume that an
605 * SError might be generated than it will not be. Hence it has been
606 * classified as FTR_HIGHER_SAFE.
607 */
608 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0),
609 ARM64_FTR_END,
610 };
611
612 static const struct arm64_ftr_bits ftr_id_isar4[] = {
613 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0),
614 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0),
615 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0),
616 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0),
617 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0),
618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0),
619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0),
620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0),
621 ARM64_FTR_END,
622 };
623
624 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0),
626 ARM64_FTR_END,
627 };
628
629 static const struct arm64_ftr_bits ftr_id_isar6[] = {
630 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0),
631 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0),
632 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0),
633 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0),
634 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0),
635 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0),
636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0),
637 ARM64_FTR_END,
638 };
639
640 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
641 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0),
642 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0),
643 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0),
644 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0),
645 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0),
646 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0),
647 ARM64_FTR_END,
648 };
649
650 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
651 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0),
652 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0),
653 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0),
654 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0),
655 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0),
656 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0),
657 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0),
658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0),
659 ARM64_FTR_END,
660 };
661
662 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
663 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0),
664 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0),
665 ARM64_FTR_END,
666 };
667
668 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
669 /* [31:28] TraceFilt */
670 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0),
671 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0),
672 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0),
673 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0),
674 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0),
675 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0),
676 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0),
677 ARM64_FTR_END,
678 };
679
680 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
681 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0),
682 ARM64_FTR_END,
683 };
684
685 /*
686 * Common ftr bits for a 32bit register with all hidden, strict
687 * attributes, with 4bit feature fields and a default safe value of
688 * 0. Covers the following 32bit registers:
689 * id_isar[1-3], id_mmfr[1-3]
690 */
691 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
696 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
697 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
698 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
699 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
700 ARM64_FTR_END,
701 };
702
703 /* Table for a single 32bit feature value */
704 static const struct arm64_ftr_bits ftr_single32[] = {
705 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
706 ARM64_FTR_END,
707 };
708
709 static const struct arm64_ftr_bits ftr_raz[] = {
710 ARM64_FTR_END,
711 };
712
713 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \
714 .sys_id = id, \
715 .reg = &(struct arm64_ftr_reg){ \
716 .name = id_str, \
717 .override = (ovr), \
718 .ftr_bits = &((table)[0]), \
719 }}
720
721 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \
722 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr)
723
724 #define ARM64_FTR_REG(id, table) \
725 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override)
726
727 struct arm64_ftr_override id_aa64mmfr0_override;
728 struct arm64_ftr_override id_aa64mmfr1_override;
729 struct arm64_ftr_override id_aa64mmfr2_override;
730 struct arm64_ftr_override id_aa64pfr0_override;
731 struct arm64_ftr_override id_aa64pfr1_override;
732 struct arm64_ftr_override id_aa64zfr0_override;
733 struct arm64_ftr_override id_aa64smfr0_override;
734 struct arm64_ftr_override id_aa64isar1_override;
735 struct arm64_ftr_override id_aa64isar2_override;
736
737 struct arm64_ftr_override arm64_sw_feature_override;
738
739 static const struct __ftr_reg_entry {
740 u32 sys_id;
741 struct arm64_ftr_reg *reg;
742 } arm64_ftr_regs[] = {
743
744 /* Op1 = 0, CRn = 0, CRm = 1 */
745 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
746 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
747 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
748 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
749 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
750 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
751 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
752
753 /* Op1 = 0, CRn = 0, CRm = 2 */
754 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
755 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
756 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
757 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
758 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
759 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
760 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
761 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
762
763 /* Op1 = 0, CRn = 0, CRm = 3 */
764 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0),
765 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1),
766 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
767 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
768 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
769 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
770
771 /* Op1 = 0, CRn = 0, CRm = 4 */
772 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0,
773 &id_aa64pfr0_override),
774 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
775 &id_aa64pfr1_override),
776 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2),
777 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0,
778 &id_aa64zfr0_override),
779 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0,
780 &id_aa64smfr0_override),
781 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0),
782
783 /* Op1 = 0, CRn = 0, CRm = 5 */
784 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
785 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
786
787 /* Op1 = 0, CRn = 0, CRm = 6 */
788 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
789 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
790 &id_aa64isar1_override),
791 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2,
792 &id_aa64isar2_override),
793 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3),
794
795 /* Op1 = 0, CRn = 0, CRm = 7 */
796 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0,
797 &id_aa64mmfr0_override),
798 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
799 &id_aa64mmfr1_override),
800 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2,
801 &id_aa64mmfr2_override),
802 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3),
803 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4),
804
805 /* Op1 = 1, CRn = 0, CRm = 0 */
806 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
807
808 /* Op1 = 3, CRn = 0, CRm = 0 */
809 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
810 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
811
812 /* Op1 = 3, CRn = 14, CRm = 0 */
813 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
814 };
815
816 static int search_cmp_ftr_reg(const void *id, const void *regp)
817 {
818 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
819 }
820
821 /*
822 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
823 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
824 * ascending order of sys_id, we use binary search to find a matching
825 * entry.
826 *
827 * returns - Upon success, matching ftr_reg entry for id.
828 * - NULL on failure. It is upto the caller to decide
829 * the impact of a failure.
830 */
831 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
832 {
833 const struct __ftr_reg_entry *ret;
834
835 ret = bsearch((const void *)(unsigned long)sys_id,
836 arm64_ftr_regs,
837 ARRAY_SIZE(arm64_ftr_regs),
838 sizeof(arm64_ftr_regs[0]),
839 search_cmp_ftr_reg);
840 if (ret)
841 return ret->reg;
842 return NULL;
843 }
844
845 /*
846 * get_arm64_ftr_reg - Looks up a feature register entry using
847 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
848 *
849 * returns - Upon success, matching ftr_reg entry for id.
850 * - NULL on failure but with an WARN_ON().
851 */
852 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
853 {
854 struct arm64_ftr_reg *reg;
855
856 reg = get_arm64_ftr_reg_nowarn(sys_id);
857
858 /*
859 * Requesting a non-existent register search is an error. Warn
860 * and let the caller handle it.
861 */
862 WARN_ON(!reg);
863 return reg;
864 }
865
866 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
867 s64 ftr_val)
868 {
869 u64 mask = arm64_ftr_mask(ftrp);
870
871 reg &= ~mask;
872 reg |= (ftr_val << ftrp->shift) & mask;
873 return reg;
874 }
875
876 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
877 s64 cur)
878 {
879 s64 ret = 0;
880
881 switch (ftrp->type) {
882 case FTR_EXACT:
883 ret = ftrp->safe_val;
884 break;
885 case FTR_LOWER_SAFE:
886 ret = min(new, cur);
887 break;
888 case FTR_HIGHER_OR_ZERO_SAFE:
889 if (!cur || !new)
890 break;
891 fallthrough;
892 case FTR_HIGHER_SAFE:
893 ret = max(new, cur);
894 break;
895 default:
896 BUG();
897 }
898
899 return ret;
900 }
901
902 static void __init sort_ftr_regs(void)
903 {
904 unsigned int i;
905
906 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
907 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
908 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
909 unsigned int j = 0;
910
911 /*
912 * Features here must be sorted in descending order with respect
913 * to their shift values and should not overlap with each other.
914 */
915 for (; ftr_bits->width != 0; ftr_bits++, j++) {
916 unsigned int width = ftr_reg->ftr_bits[j].width;
917 unsigned int shift = ftr_reg->ftr_bits[j].shift;
918 unsigned int prev_shift;
919
920 WARN((shift + width) > 64,
921 "%s has invalid feature at shift %d\n",
922 ftr_reg->name, shift);
923
924 /*
925 * Skip the first feature. There is nothing to
926 * compare against for now.
927 */
928 if (j == 0)
929 continue;
930
931 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
932 WARN((shift + width) > prev_shift,
933 "%s has feature overlap at shift %d\n",
934 ftr_reg->name, shift);
935 }
936
937 /*
938 * Skip the first register. There is nothing to
939 * compare against for now.
940 */
941 if (i == 0)
942 continue;
943 /*
944 * Registers here must be sorted in ascending order with respect
945 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
946 * to work correctly.
947 */
948 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id);
949 }
950 }
951
952 /*
953 * Initialise the CPU feature register from Boot CPU values.
954 * Also initiliases the strict_mask for the register.
955 * Any bits that are not covered by an arm64_ftr_bits entry are considered
956 * RES0 for the system-wide value, and must strictly match.
957 */
958 static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
959 {
960 u64 val = 0;
961 u64 strict_mask = ~0x0ULL;
962 u64 user_mask = 0;
963 u64 valid_mask = 0;
964
965 const struct arm64_ftr_bits *ftrp;
966 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
967
968 if (!reg)
969 return;
970
971 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
972 u64 ftr_mask = arm64_ftr_mask(ftrp);
973 s64 ftr_new = arm64_ftr_value(ftrp, new);
974 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
975
976 if ((ftr_mask & reg->override->mask) == ftr_mask) {
977 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
978 char *str = NULL;
979
980 if (ftr_ovr != tmp) {
981 /* Unsafe, remove the override */
982 reg->override->mask &= ~ftr_mask;
983 reg->override->val &= ~ftr_mask;
984 tmp = ftr_ovr;
985 str = "ignoring override";
986 } else if (ftr_new != tmp) {
987 /* Override was valid */
988 ftr_new = tmp;
989 str = "forced";
990 } else if (ftr_ovr == tmp) {
991 /* Override was the safe value */
992 str = "already set";
993 }
994
995 if (str)
996 pr_warn("%s[%d:%d]: %s to %llx\n",
997 reg->name,
998 ftrp->shift + ftrp->width - 1,
999 ftrp->shift, str,
1000 tmp & (BIT(ftrp->width) - 1));
1001 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
1002 reg->override->val &= ~ftr_mask;
1003 pr_warn("%s[%d:%d]: impossible override, ignored\n",
1004 reg->name,
1005 ftrp->shift + ftrp->width - 1,
1006 ftrp->shift);
1007 }
1008
1009 val = arm64_ftr_set_value(ftrp, val, ftr_new);
1010
1011 valid_mask |= ftr_mask;
1012 if (!ftrp->strict)
1013 strict_mask &= ~ftr_mask;
1014 if (ftrp->visible)
1015 user_mask |= ftr_mask;
1016 else
1017 reg->user_val = arm64_ftr_set_value(ftrp,
1018 reg->user_val,
1019 ftrp->safe_val);
1020 }
1021
1022 val &= valid_mask;
1023
1024 reg->sys_val = val;
1025 reg->strict_mask = strict_mask;
1026 reg->user_mask = user_mask;
1027 }
1028
1029 extern const struct arm64_cpu_capabilities arm64_errata[];
1030 static const struct arm64_cpu_capabilities arm64_features[];
1031
1032 static void __init
1033 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
1034 {
1035 for (; caps->matches; caps++) {
1036 if (WARN(caps->capability >= ARM64_NCAPS,
1037 "Invalid capability %d\n", caps->capability))
1038 continue;
1039 if (WARN(cpucap_ptrs[caps->capability],
1040 "Duplicate entry for capability %d\n",
1041 caps->capability))
1042 continue;
1043 cpucap_ptrs[caps->capability] = caps;
1044 }
1045 }
1046
1047 static void __init init_cpucap_indirect_list(void)
1048 {
1049 init_cpucap_indirect_list_from_array(arm64_features);
1050 init_cpucap_indirect_list_from_array(arm64_errata);
1051 }
1052
1053 static void __init setup_boot_cpu_capabilities(void);
1054
1055 static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
1056 {
1057 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
1058 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
1059 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
1060 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
1061 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
1062 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
1063 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
1064 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
1065 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
1066 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
1067 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
1068 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
1069 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
1070 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
1071 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
1072 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
1073 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
1074 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
1075 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
1076 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
1077 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
1078 }
1079
1080 #ifdef CONFIG_ARM64_PSEUDO_NMI
1081 static bool enable_pseudo_nmi;
1082
1083 static int __init early_enable_pseudo_nmi(char *p)
1084 {
1085 return kstrtobool(p, &enable_pseudo_nmi);
1086 }
1087 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1088
1089 static __init void detect_system_supports_pseudo_nmi(void)
1090 {
1091 struct device_node *np;
1092
1093 if (!enable_pseudo_nmi)
1094 return;
1095
1096 /*
1097 * Detect broken MediaTek firmware that doesn't properly save and
1098 * restore GIC priorities.
1099 */
1100 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3");
1101 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) {
1102 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n");
1103 enable_pseudo_nmi = false;
1104 }
1105 of_node_put(np);
1106 }
1107 #else /* CONFIG_ARM64_PSEUDO_NMI */
1108 static inline void detect_system_supports_pseudo_nmi(void) { }
1109 #endif
1110
1111 void __init init_cpu_features(struct cpuinfo_arm64 *info)
1112 {
1113 /* Before we start using the tables, make sure it is sorted */
1114 sort_ftr_regs();
1115
1116 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
1117 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
1118 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
1119 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
1120 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
1121 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
1122 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
1123 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
1124 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3);
1125 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
1126 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
1127 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
1128 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3);
1129 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4);
1130 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
1131 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
1132 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2);
1133 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
1134 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0);
1135 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0);
1136
1137 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
1138 init_32bit_cpu_features(&info->aarch32);
1139
1140 if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1141 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1142 unsigned long cpacr = cpacr_save_enable_kernel_sve();
1143
1144 vec_init_vq_map(ARM64_VEC_SVE);
1145
1146 cpacr_restore(cpacr);
1147 }
1148
1149 if (IS_ENABLED(CONFIG_ARM64_SME) &&
1150 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1151 unsigned long cpacr = cpacr_save_enable_kernel_sme();
1152
1153 /*
1154 * We mask out SMPS since even if the hardware
1155 * supports priorities the kernel does not at present
1156 * and we block access to them.
1157 */
1158 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
1159 vec_init_vq_map(ARM64_VEC_SME);
1160
1161 cpacr_restore(cpacr);
1162 }
1163
1164 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
1165 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
1166 }
1167
1168 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
1169 {
1170 const struct arm64_ftr_bits *ftrp;
1171
1172 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
1173 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
1174 s64 ftr_new = arm64_ftr_value(ftrp, new);
1175
1176 if (ftr_cur == ftr_new)
1177 continue;
1178 /* Find a safe value */
1179 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
1180 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
1181 }
1182
1183 }
1184
1185 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
1186 {
1187 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1188
1189 if (!regp)
1190 return 0;
1191
1192 update_cpu_ftr_reg(regp, val);
1193 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
1194 return 0;
1195 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
1196 regp->name, boot, cpu, val);
1197 return 1;
1198 }
1199
1200 static void relax_cpu_ftr_reg(u32 sys_id, int field)
1201 {
1202 const struct arm64_ftr_bits *ftrp;
1203 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1204
1205 if (!regp)
1206 return;
1207
1208 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1209 if (ftrp->shift == field) {
1210 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1211 break;
1212 }
1213 }
1214
1215 /* Bogus field? */
1216 WARN_ON(!ftrp->width);
1217 }
1218
1219 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1220 struct cpuinfo_arm64 *boot)
1221 {
1222 static bool boot_cpu_32bit_regs_overridden = false;
1223
1224 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1225 return;
1226
1227 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1228 return;
1229
1230 boot->aarch32 = info->aarch32;
1231 init_32bit_cpu_features(&boot->aarch32);
1232 boot_cpu_32bit_regs_overridden = true;
1233 }
1234
1235 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1236 struct cpuinfo_32bit *boot)
1237 {
1238 int taint = 0;
1239 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1240
1241 /*
1242 * If we don't have AArch32 at EL1, then relax the strictness of
1243 * EL1-dependent register fields to avoid spurious sanity check fails.
1244 */
1245 if (!id_aa64pfr0_32bit_el1(pfr0)) {
1246 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT);
1247 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT);
1248 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT);
1249 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT);
1250 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT);
1251 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT);
1252 }
1253
1254 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1255 info->reg_id_dfr0, boot->reg_id_dfr0);
1256 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1257 info->reg_id_dfr1, boot->reg_id_dfr1);
1258 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1259 info->reg_id_isar0, boot->reg_id_isar0);
1260 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1261 info->reg_id_isar1, boot->reg_id_isar1);
1262 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1263 info->reg_id_isar2, boot->reg_id_isar2);
1264 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1265 info->reg_id_isar3, boot->reg_id_isar3);
1266 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1267 info->reg_id_isar4, boot->reg_id_isar4);
1268 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1269 info->reg_id_isar5, boot->reg_id_isar5);
1270 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1271 info->reg_id_isar6, boot->reg_id_isar6);
1272
1273 /*
1274 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1275 * ACTLR formats could differ across CPUs and therefore would have to
1276 * be trapped for virtualization anyway.
1277 */
1278 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1279 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1280 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1281 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1282 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1283 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1284 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1285 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1286 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1287 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1288 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1289 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1290 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1291 info->reg_id_pfr0, boot->reg_id_pfr0);
1292 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1293 info->reg_id_pfr1, boot->reg_id_pfr1);
1294 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1295 info->reg_id_pfr2, boot->reg_id_pfr2);
1296 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1297 info->reg_mvfr0, boot->reg_mvfr0);
1298 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1299 info->reg_mvfr1, boot->reg_mvfr1);
1300 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1301 info->reg_mvfr2, boot->reg_mvfr2);
1302
1303 return taint;
1304 }
1305
1306 /*
1307 * Update system wide CPU feature registers with the values from a
1308 * non-boot CPU. Also performs SANITY checks to make sure that there
1309 * aren't any insane variations from that of the boot CPU.
1310 */
1311 void update_cpu_features(int cpu,
1312 struct cpuinfo_arm64 *info,
1313 struct cpuinfo_arm64 *boot)
1314 {
1315 int taint = 0;
1316
1317 /*
1318 * The kernel can handle differing I-cache policies, but otherwise
1319 * caches should look identical. Userspace JITs will make use of
1320 * *minLine.
1321 */
1322 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1323 info->reg_ctr, boot->reg_ctr);
1324
1325 /*
1326 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1327 * could result in too much or too little memory being zeroed if a
1328 * process is preempted and migrated between CPUs.
1329 */
1330 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1331 info->reg_dczid, boot->reg_dczid);
1332
1333 /* If different, timekeeping will be broken (especially with KVM) */
1334 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1335 info->reg_cntfrq, boot->reg_cntfrq);
1336
1337 /*
1338 * The kernel uses self-hosted debug features and expects CPUs to
1339 * support identical debug features. We presently need CTX_CMPs, WRPs,
1340 * and BRPs to be identical.
1341 * ID_AA64DFR1 is currently RES0.
1342 */
1343 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1344 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1345 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1346 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1347 /*
1348 * Even in big.LITTLE, processors should be identical instruction-set
1349 * wise.
1350 */
1351 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1352 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1353 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1354 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1355 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
1356 info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1357 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu,
1358 info->reg_id_aa64isar3, boot->reg_id_aa64isar3);
1359
1360 /*
1361 * Differing PARange support is fine as long as all peripherals and
1362 * memory are mapped within the minimum PARange of all CPUs.
1363 * Linux should not care about secure memory.
1364 */
1365 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1366 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1367 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1368 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1369 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1370 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1371 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu,
1372 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3);
1373
1374 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1375 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1376 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1377 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1378 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu,
1379 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2);
1380
1381 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1382 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1383
1384 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu,
1385 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0);
1386
1387 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu,
1388 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0);
1389
1390 /* Probe vector lengths */
1391 if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1392 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1393 if (!system_capabilities_finalized()) {
1394 unsigned long cpacr = cpacr_save_enable_kernel_sve();
1395
1396 vec_update_vq_map(ARM64_VEC_SVE);
1397
1398 cpacr_restore(cpacr);
1399 }
1400 }
1401
1402 if (IS_ENABLED(CONFIG_ARM64_SME) &&
1403 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1404 unsigned long cpacr = cpacr_save_enable_kernel_sme();
1405
1406 /*
1407 * We mask out SMPS since even if the hardware
1408 * supports priorities the kernel does not at present
1409 * and we block access to them.
1410 */
1411 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
1412
1413 /* Probe vector lengths */
1414 if (!system_capabilities_finalized())
1415 vec_update_vq_map(ARM64_VEC_SME);
1416
1417 cpacr_restore(cpacr);
1418 }
1419
1420 /*
1421 * The kernel uses the LDGM/STGM instructions and the number of tags
1422 * they read/write depends on the GMID_EL1.BS field. Check that the
1423 * value is the same on all CPUs.
1424 */
1425 if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1426 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1427 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1428 info->reg_gmid, boot->reg_gmid);
1429 }
1430
1431 /*
1432 * If we don't have AArch32 at all then skip the checks entirely
1433 * as the register values may be UNKNOWN and we're not going to be
1434 * using them for anything.
1435 *
1436 * This relies on a sanitised view of the AArch64 ID registers
1437 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1438 */
1439 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1440 lazy_init_32bit_cpu_features(info, boot);
1441 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1442 &boot->aarch32);
1443 }
1444
1445 /*
1446 * Mismatched CPU features are a recipe for disaster. Don't even
1447 * pretend to support them.
1448 */
1449 if (taint) {
1450 pr_warn_once("Unsupported CPU feature variation detected.\n");
1451 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1452 }
1453 }
1454
1455 u64 read_sanitised_ftr_reg(u32 id)
1456 {
1457 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1458
1459 if (!regp)
1460 return 0;
1461 return regp->sys_val;
1462 }
1463 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1464
1465 #define read_sysreg_case(r) \
1466 case r: val = read_sysreg_s(r); break;
1467
1468 /*
1469 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1470 * Read the system register on the current CPU
1471 */
1472 u64 __read_sysreg_by_encoding(u32 sys_id)
1473 {
1474 struct arm64_ftr_reg *regp;
1475 u64 val;
1476
1477 switch (sys_id) {
1478 read_sysreg_case(SYS_ID_PFR0_EL1);
1479 read_sysreg_case(SYS_ID_PFR1_EL1);
1480 read_sysreg_case(SYS_ID_PFR2_EL1);
1481 read_sysreg_case(SYS_ID_DFR0_EL1);
1482 read_sysreg_case(SYS_ID_DFR1_EL1);
1483 read_sysreg_case(SYS_ID_MMFR0_EL1);
1484 read_sysreg_case(SYS_ID_MMFR1_EL1);
1485 read_sysreg_case(SYS_ID_MMFR2_EL1);
1486 read_sysreg_case(SYS_ID_MMFR3_EL1);
1487 read_sysreg_case(SYS_ID_MMFR4_EL1);
1488 read_sysreg_case(SYS_ID_MMFR5_EL1);
1489 read_sysreg_case(SYS_ID_ISAR0_EL1);
1490 read_sysreg_case(SYS_ID_ISAR1_EL1);
1491 read_sysreg_case(SYS_ID_ISAR2_EL1);
1492 read_sysreg_case(SYS_ID_ISAR3_EL1);
1493 read_sysreg_case(SYS_ID_ISAR4_EL1);
1494 read_sysreg_case(SYS_ID_ISAR5_EL1);
1495 read_sysreg_case(SYS_ID_ISAR6_EL1);
1496 read_sysreg_case(SYS_MVFR0_EL1);
1497 read_sysreg_case(SYS_MVFR1_EL1);
1498 read_sysreg_case(SYS_MVFR2_EL1);
1499
1500 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1501 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1502 read_sysreg_case(SYS_ID_AA64PFR2_EL1);
1503 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1504 read_sysreg_case(SYS_ID_AA64SMFR0_EL1);
1505 read_sysreg_case(SYS_ID_AA64FPFR0_EL1);
1506 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1507 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1508 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1509 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1510 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1511 read_sysreg_case(SYS_ID_AA64MMFR3_EL1);
1512 read_sysreg_case(SYS_ID_AA64MMFR4_EL1);
1513 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1514 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1515 read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
1516 read_sysreg_case(SYS_ID_AA64ISAR3_EL1);
1517
1518 read_sysreg_case(SYS_CNTFRQ_EL0);
1519 read_sysreg_case(SYS_CTR_EL0);
1520 read_sysreg_case(SYS_DCZID_EL0);
1521
1522 default:
1523 BUG();
1524 return 0;
1525 }
1526
1527 regp = get_arm64_ftr_reg(sys_id);
1528 if (regp) {
1529 val &= ~regp->override->mask;
1530 val |= (regp->override->val & regp->override->mask);
1531 }
1532
1533 return val;
1534 }
1535
1536 #include <linux/irqchip/arm-gic-v3.h>
1537
1538 static bool
1539 has_always(const struct arm64_cpu_capabilities *entry, int scope)
1540 {
1541 return true;
1542 }
1543
1544 static bool
1545 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1546 {
1547 int val, min, max;
1548 u64 tmp;
1549
1550 val = cpuid_feature_extract_field_width(reg, entry->field_pos,
1551 entry->field_width,
1552 entry->sign);
1553
1554 tmp = entry->min_field_value;
1555 tmp <<= entry->field_pos;
1556
1557 min = cpuid_feature_extract_field_width(tmp, entry->field_pos,
1558 entry->field_width,
1559 entry->sign);
1560
1561 tmp = entry->max_field_value;
1562 tmp <<= entry->field_pos;
1563
1564 max = cpuid_feature_extract_field_width(tmp, entry->field_pos,
1565 entry->field_width,
1566 entry->sign);
1567
1568 return val >= min && val <= max;
1569 }
1570
1571 static u64
1572 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope)
1573 {
1574 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1575 if (scope == SCOPE_SYSTEM)
1576 return read_sanitised_ftr_reg(entry->sys_reg);
1577 else
1578 return __read_sysreg_by_encoding(entry->sys_reg);
1579 }
1580
1581 static bool
1582 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1583 {
1584 int mask;
1585 struct arm64_ftr_reg *regp;
1586 u64 val = read_scoped_sysreg(entry, scope);
1587
1588 regp = get_arm64_ftr_reg(entry->sys_reg);
1589 if (!regp)
1590 return false;
1591
1592 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask,
1593 entry->field_pos,
1594 entry->field_width);
1595 if (!mask)
1596 return false;
1597
1598 return feature_matches(val, entry);
1599 }
1600
1601 static bool
1602 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1603 {
1604 u64 val = read_scoped_sysreg(entry, scope);
1605 return feature_matches(val, entry);
1606 }
1607
1608 const struct cpumask *system_32bit_el0_cpumask(void)
1609 {
1610 if (!system_supports_32bit_el0())
1611 return cpu_none_mask;
1612
1613 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1614 return cpu_32bit_el0_mask;
1615
1616 return cpu_possible_mask;
1617 }
1618
1619 static int __init parse_32bit_el0_param(char *str)
1620 {
1621 allow_mismatched_32bit_el0 = true;
1622 return 0;
1623 }
1624 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param);
1625
1626 static ssize_t aarch32_el0_show(struct device *dev,
1627 struct device_attribute *attr, char *buf)
1628 {
1629 const struct cpumask *mask = system_32bit_el0_cpumask();
1630
1631 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask));
1632 }
1633 static const DEVICE_ATTR_RO(aarch32_el0);
1634
1635 static int __init aarch32_el0_sysfs_init(void)
1636 {
1637 struct device *dev_root;
1638 int ret = 0;
1639
1640 if (!allow_mismatched_32bit_el0)
1641 return 0;
1642
1643 dev_root = bus_get_dev_root(&cpu_subsys);
1644 if (dev_root) {
1645 ret = device_create_file(dev_root, &dev_attr_aarch32_el0);
1646 put_device(dev_root);
1647 }
1648 return ret;
1649 }
1650 device_initcall(aarch32_el0_sysfs_init);
1651
1652 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1653 {
1654 if (!has_cpuid_feature(entry, scope))
1655 return allow_mismatched_32bit_el0;
1656
1657 if (scope == SCOPE_SYSTEM)
1658 pr_info("detected: 32-bit EL0 Support\n");
1659
1660 return true;
1661 }
1662
1663 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1664 {
1665 bool has_sre;
1666
1667 if (!has_cpuid_feature(entry, scope))
1668 return false;
1669
1670 has_sre = gic_enable_sre();
1671 if (!has_sre)
1672 pr_warn_once("%s present but disabled by higher exception level\n",
1673 entry->desc);
1674
1675 return has_sre;
1676 }
1677
1678 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1679 int scope)
1680 {
1681 u64 ctr;
1682
1683 if (scope == SCOPE_SYSTEM)
1684 ctr = arm64_ftr_reg_ctrel0.sys_val;
1685 else
1686 ctr = read_cpuid_effective_cachetype();
1687
1688 return ctr & BIT(CTR_EL0_IDC_SHIFT);
1689 }
1690
1691 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1692 {
1693 /*
1694 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1695 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1696 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1697 * value.
1698 */
1699 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT)))
1700 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1701 }
1702
1703 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1704 int scope)
1705 {
1706 u64 ctr;
1707
1708 if (scope == SCOPE_SYSTEM)
1709 ctr = arm64_ftr_reg_ctrel0.sys_val;
1710 else
1711 ctr = read_cpuid_cachetype();
1712
1713 return ctr & BIT(CTR_EL0_DIC_SHIFT);
1714 }
1715
1716 static bool __maybe_unused
1717 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1718 {
1719 /*
1720 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1721 * may share TLB entries with a CPU stuck in the crashed
1722 * kernel.
1723 */
1724 if (is_kdump_kernel())
1725 return false;
1726
1727 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1728 return false;
1729
1730 return has_cpuid_feature(entry, scope);
1731 }
1732
1733 static bool __meltdown_safe = true;
1734 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1735
1736 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1737 int scope)
1738 {
1739 /* List of CPUs that are not vulnerable and don't need KPTI */
1740 static const struct midr_range kpti_safe_list[] = {
1741 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1742 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1743 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1744 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1745 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1746 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1747 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1748 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1749 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1750 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1751 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1752 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1753 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1754 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1755 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1756 { /* sentinel */ }
1757 };
1758 char const *str = "kpti command line option";
1759 bool meltdown_safe;
1760
1761 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1762
1763 /* Defer to CPU feature registers */
1764 if (has_cpuid_feature(entry, scope))
1765 meltdown_safe = true;
1766
1767 if (!meltdown_safe)
1768 __meltdown_safe = false;
1769
1770 /*
1771 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1772 * ThunderX leads to apparent I-cache corruption of kernel text, which
1773 * ends as well as you might imagine. Don't even try. We cannot rely
1774 * on the cpus_have_*cap() helpers here to detect the CPU erratum
1775 * because cpucap detection order may change. However, since we know
1776 * affected CPUs are always in a homogeneous configuration, it is
1777 * safe to rely on this_cpu_has_cap() here.
1778 */
1779 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1780 str = "ARM64_WORKAROUND_CAVIUM_27456";
1781 __kpti_forced = -1;
1782 }
1783
1784 /* Useful for KASLR robustness */
1785 if (kaslr_enabled() && kaslr_requires_kpti()) {
1786 if (!__kpti_forced) {
1787 str = "KASLR";
1788 __kpti_forced = 1;
1789 }
1790 }
1791
1792 if (cpu_mitigations_off() && !__kpti_forced) {
1793 str = "mitigations=off";
1794 __kpti_forced = -1;
1795 }
1796
1797 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1798 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1799 return false;
1800 }
1801
1802 /* Forced? */
1803 if (__kpti_forced) {
1804 pr_info_once("kernel page table isolation forced %s by %s\n",
1805 __kpti_forced > 0 ? "ON" : "OFF", str);
1806 return __kpti_forced > 0;
1807 }
1808
1809 return !meltdown_safe;
1810 }
1811
1812 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope)
1813 {
1814 /*
1815 * Although the Apple M2 family appears to support NV1, the
1816 * PTW barfs on the nVHE EL2 S1 page table format. Pretend
1817 * that it doesn't support NV1 at all.
1818 */
1819 static const struct midr_range nv1_ni_list[] = {
1820 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD),
1821 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE),
1822 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO),
1823 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
1824 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
1825 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
1826 {}
1827 };
1828
1829 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) &&
1830 !(has_cpuid_feature(entry, scope) ||
1831 is_midr_in_range_list(read_cpuid_id(), nv1_ni_list)));
1832 }
1833
1834 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2)
1835 static bool has_lpa2_at_stage1(u64 mmfr0)
1836 {
1837 unsigned int tgran;
1838
1839 tgran = cpuid_feature_extract_unsigned_field(mmfr0,
1840 ID_AA64MMFR0_EL1_TGRAN_SHIFT);
1841 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2;
1842 }
1843
1844 static bool has_lpa2_at_stage2(u64 mmfr0)
1845 {
1846 unsigned int tgran;
1847
1848 tgran = cpuid_feature_extract_unsigned_field(mmfr0,
1849 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT);
1850 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2;
1851 }
1852
1853 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope)
1854 {
1855 u64 mmfr0;
1856
1857 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
1858 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0);
1859 }
1860 #else
1861 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope)
1862 {
1863 return false;
1864 }
1865 #endif
1866
1867 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1868 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT))
1869
1870 extern
1871 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt,
1872 phys_addr_t size, pgprot_t prot,
1873 phys_addr_t (*pgtable_alloc)(int), int flags);
1874
1875 static phys_addr_t __initdata kpti_ng_temp_alloc;
1876
1877 static phys_addr_t __init kpti_ng_pgd_alloc(int shift)
1878 {
1879 kpti_ng_temp_alloc -= PAGE_SIZE;
1880 return kpti_ng_temp_alloc;
1881 }
1882
1883 static int __init __kpti_install_ng_mappings(void *__unused)
1884 {
1885 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long);
1886 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1887 kpti_remap_fn *remap_fn;
1888
1889 int cpu = smp_processor_id();
1890 int levels = CONFIG_PGTABLE_LEVELS;
1891 int order = order_base_2(levels);
1892 u64 kpti_ng_temp_pgd_pa = 0;
1893 pgd_t *kpti_ng_temp_pgd;
1894 u64 alloc = 0;
1895
1896 if (levels == 5 && !pgtable_l5_enabled())
1897 levels = 4;
1898 else if (levels == 4 && !pgtable_l4_enabled())
1899 levels = 3;
1900
1901 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1902
1903 if (!cpu) {
1904 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
1905 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE);
1906 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd);
1907
1908 //
1909 // Create a minimal page table hierarchy that permits us to map
1910 // the swapper page tables temporarily as we traverse them.
1911 //
1912 // The physical pages are laid out as follows:
1913 //
1914 // +--------+-/-------+-/------ +-/------ +-\\\--------+
1915 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] :
1916 // +--------+-\-------+-\------ +-\------ +-///--------+
1917 // ^
1918 // The first page is mapped into this hierarchy at a PMD_SHIFT
1919 // aligned virtual address, so that we can manipulate the PTE
1920 // level entries while the mapping is active. The first entry
1921 // covers the PTE[] page itself, the remaining entries are free
1922 // to be used as a ad-hoc fixmap.
1923 //
1924 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc),
1925 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL,
1926 kpti_ng_pgd_alloc, 0);
1927 }
1928
1929 cpu_install_idmap();
1930 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA);
1931 cpu_uninstall_idmap();
1932
1933 if (!cpu) {
1934 free_pages(alloc, order);
1935 arm64_use_ng_mappings = true;
1936 }
1937
1938 return 0;
1939 }
1940
1941 static void __init kpti_install_ng_mappings(void)
1942 {
1943 /* Check whether KPTI is going to be used */
1944 if (!arm64_kernel_unmapped_at_el0())
1945 return;
1946
1947 /*
1948 * We don't need to rewrite the page-tables if either we've done
1949 * it already or we have KASLR enabled and therefore have not
1950 * created any global mappings at all.
1951 */
1952 if (arm64_use_ng_mappings)
1953 return;
1954
1955 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask);
1956 }
1957
1958 #else
1959 static inline void kpti_install_ng_mappings(void)
1960 {
1961 }
1962 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1963
1964 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap)
1965 {
1966 if (__this_cpu_read(this_cpu_vector) == vectors) {
1967 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1968
1969 __this_cpu_write(this_cpu_vector, v);
1970 }
1971
1972 }
1973
1974 static int __init parse_kpti(char *str)
1975 {
1976 bool enabled;
1977 int ret = kstrtobool(str, &enabled);
1978
1979 if (ret)
1980 return ret;
1981
1982 __kpti_forced = enabled ? 1 : -1;
1983 return 0;
1984 }
1985 early_param("kpti", parse_kpti);
1986
1987 #ifdef CONFIG_ARM64_HW_AFDBM
1988 static struct cpumask dbm_cpus __read_mostly;
1989
1990 static inline void __cpu_enable_hw_dbm(void)
1991 {
1992 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1993
1994 write_sysreg(tcr, tcr_el1);
1995 isb();
1996 local_flush_tlb_all();
1997 }
1998
1999 static bool cpu_has_broken_dbm(void)
2000 {
2001 /* List of CPUs which have broken DBM support. */
2002 static const struct midr_range cpus[] = {
2003 #ifdef CONFIG_ARM64_ERRATUM_1024718
2004 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
2005 /* Kryo4xx Silver (rdpe => r1p0) */
2006 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
2007 #endif
2008 #ifdef CONFIG_ARM64_ERRATUM_2051678
2009 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
2010 #endif
2011 {},
2012 };
2013
2014 return is_midr_in_range_list(read_cpuid_id(), cpus);
2015 }
2016
2017 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
2018 {
2019 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
2020 !cpu_has_broken_dbm();
2021 }
2022
2023 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
2024 {
2025 if (cpu_can_use_dbm(cap)) {
2026 __cpu_enable_hw_dbm();
2027 cpumask_set_cpu(smp_processor_id(), &dbm_cpus);
2028 }
2029 }
2030
2031 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
2032 int __unused)
2033 {
2034 /*
2035 * DBM is a non-conflicting feature. i.e, the kernel can safely
2036 * run a mix of CPUs with and without the feature. So, we
2037 * unconditionally enable the capability to allow any late CPU
2038 * to use the feature. We only enable the control bits on the
2039 * CPU, if it is supported.
2040 */
2041
2042 return true;
2043 }
2044
2045 #endif
2046
2047 #ifdef CONFIG_ARM64_AMU_EXTN
2048
2049 /*
2050 * The "amu_cpus" cpumask only signals that the CPU implementation for the
2051 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
2052 * information regarding all the events that it supports. When a CPU bit is
2053 * set in the cpumask, the user of this feature can only rely on the presence
2054 * of the 4 fixed counters for that CPU. But this does not guarantee that the
2055 * counters are enabled or access to these counters is enabled by code
2056 * executed at higher exception levels (firmware).
2057 */
2058 static struct cpumask amu_cpus __read_mostly;
2059
2060 bool cpu_has_amu_feat(int cpu)
2061 {
2062 return cpumask_test_cpu(cpu, &amu_cpus);
2063 }
2064
2065 int get_cpu_with_amu_feat(void)
2066 {
2067 return cpumask_any(&amu_cpus);
2068 }
2069
2070 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
2071 {
2072 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
2073 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
2074
2075 /* 0 reference values signal broken/disabled counters */
2076 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
2077 update_freq_counters_refs();
2078 }
2079 }
2080
2081 static bool has_amu(const struct arm64_cpu_capabilities *cap,
2082 int __unused)
2083 {
2084 /*
2085 * The AMU extension is a non-conflicting feature: the kernel can
2086 * safely run a mix of CPUs with and without support for the
2087 * activity monitors extension. Therefore, unconditionally enable
2088 * the capability to allow any late CPU to use the feature.
2089 *
2090 * With this feature unconditionally enabled, the cpu_enable
2091 * function will be called for all CPUs that match the criteria,
2092 * including secondary and hotplugged, marking this feature as
2093 * present on that respective CPU. The enable function will also
2094 * print a detection message.
2095 */
2096
2097 return true;
2098 }
2099 #else
2100 int get_cpu_with_amu_feat(void)
2101 {
2102 return nr_cpu_ids;
2103 }
2104 #endif
2105
2106 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
2107 {
2108 return is_kernel_in_hyp_mode();
2109 }
2110
2111 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
2112 {
2113 /*
2114 * Copy register values that aren't redirected by hardware.
2115 *
2116 * Before code patching, we only set tpidr_el1, all CPUs need to copy
2117 * this value to tpidr_el2 before we patch the code. Once we've done
2118 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
2119 * do anything here.
2120 */
2121 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
2122 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
2123 }
2124
2125 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap,
2126 int scope)
2127 {
2128 if (kvm_get_mode() != KVM_MODE_NV)
2129 return false;
2130
2131 if (!has_cpuid_feature(cap, scope)) {
2132 pr_warn("unavailable: %s\n", cap->desc);
2133 return false;
2134 }
2135
2136 return true;
2137 }
2138
2139 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry,
2140 int __unused)
2141 {
2142 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE);
2143 }
2144
2145 #ifdef CONFIG_ARM64_PAN
2146 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
2147 {
2148 /*
2149 * We modify PSTATE. This won't work from irq context as the PSTATE
2150 * is discarded once we return from the exception.
2151 */
2152 WARN_ON_ONCE(in_interrupt());
2153
2154 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
2155 set_pstate_pan(1);
2156 }
2157 #endif /* CONFIG_ARM64_PAN */
2158
2159 #ifdef CONFIG_ARM64_RAS_EXTN
2160 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
2161 {
2162 /* Firmware may have left a deferred SError in this register. */
2163 write_sysreg_s(0, SYS_DISR_EL1);
2164 }
2165 #endif /* CONFIG_ARM64_RAS_EXTN */
2166
2167 #ifdef CONFIG_ARM64_PTR_AUTH
2168 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
2169 {
2170 int boot_val, sec_val;
2171
2172 /* We don't expect to be called with SCOPE_SYSTEM */
2173 WARN_ON(scope == SCOPE_SYSTEM);
2174 /*
2175 * The ptr-auth feature levels are not intercompatible with lower
2176 * levels. Hence we must match ptr-auth feature level of the secondary
2177 * CPUs with that of the boot CPU. The level of boot cpu is fetched
2178 * from the sanitised register whereas direct register read is done for
2179 * the secondary CPUs.
2180 * The sanitised feature state is guaranteed to match that of the
2181 * boot CPU as a mismatched secondary CPU is parked before it gets
2182 * a chance to update the state, with the capability.
2183 */
2184 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
2185 entry->field_pos, entry->sign);
2186 if (scope & SCOPE_BOOT_CPU)
2187 return boot_val >= entry->min_field_value;
2188 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
2189 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
2190 entry->field_pos, entry->sign);
2191 return (sec_val >= entry->min_field_value) && (sec_val == boot_val);
2192 }
2193
2194 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
2195 int scope)
2196 {
2197 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
2198 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope);
2199 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope);
2200
2201 return apa || apa3 || api;
2202 }
2203
2204 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
2205 int __unused)
2206 {
2207 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
2208 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5);
2209 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3);
2210
2211 return gpa || gpa3 || gpi;
2212 }
2213 #endif /* CONFIG_ARM64_PTR_AUTH */
2214
2215 #ifdef CONFIG_ARM64_E0PD
2216 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
2217 {
2218 if (this_cpu_has_cap(ARM64_HAS_E0PD))
2219 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
2220 }
2221 #endif /* CONFIG_ARM64_E0PD */
2222
2223 #ifdef CONFIG_ARM64_PSEUDO_NMI
2224 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
2225 int scope)
2226 {
2227 /*
2228 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU
2229 * feature, so will be detected earlier.
2230 */
2231 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS);
2232 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS))
2233 return false;
2234
2235 return enable_pseudo_nmi;
2236 }
2237
2238 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry,
2239 int scope)
2240 {
2241 /*
2242 * If we're not using priority masking then we won't be poking PMR_EL1,
2243 * and there's no need to relax synchronization of writes to it, and
2244 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from
2245 * that.
2246 *
2247 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU
2248 * feature, so will be detected earlier.
2249 */
2250 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING);
2251 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING))
2252 return false;
2253
2254 /*
2255 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a
2256 * hint for interrupt distribution, a DSB is not necessary when
2257 * unmasking IRQs via PMR, and we can relax the barrier to a NOP.
2258 *
2259 * Linux itself doesn't use 1:N distribution, so has no need to
2260 * set PMHE. The only reason to have it set is if EL3 requires it
2261 * (and we can't change it).
2262 */
2263 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0;
2264 }
2265 #endif
2266
2267 #ifdef CONFIG_ARM64_BTI
2268 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
2269 {
2270 /*
2271 * Use of X16/X17 for tail-calls and trampolines that jump to
2272 * function entry points using BR is a requirement for
2273 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
2274 * So, be strict and forbid other BRs using other registers to
2275 * jump onto a PACIxSP instruction:
2276 */
2277 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
2278 isb();
2279 }
2280 #endif /* CONFIG_ARM64_BTI */
2281
2282 #ifdef CONFIG_ARM64_MTE
2283 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
2284 {
2285 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0);
2286
2287 mte_cpu_setup();
2288
2289 /*
2290 * Clear the tags in the zero page. This needs to be done via the
2291 * linear map which has the Tagged attribute.
2292 */
2293 if (try_page_mte_tagging(ZERO_PAGE(0))) {
2294 mte_clear_page_tags(lm_alias(empty_zero_page));
2295 set_page_mte_tagged(ZERO_PAGE(0));
2296 }
2297
2298 kasan_init_hw_tags_cpu();
2299 }
2300 #endif /* CONFIG_ARM64_MTE */
2301
2302 static void user_feature_fixup(void)
2303 {
2304 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) {
2305 struct arm64_ftr_reg *regp;
2306
2307 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1);
2308 if (regp)
2309 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK;
2310 }
2311
2312 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) {
2313 struct arm64_ftr_reg *regp;
2314
2315 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1);
2316 if (regp)
2317 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK;
2318 }
2319 }
2320
2321 static void elf_hwcap_fixup(void)
2322 {
2323 #ifdef CONFIG_COMPAT
2324 if (cpus_have_cap(ARM64_WORKAROUND_1742098))
2325 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
2326 #endif /* CONFIG_COMPAT */
2327 }
2328
2329 #ifdef CONFIG_KVM
2330 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
2331 {
2332 return kvm_get_mode() == KVM_MODE_PROTECTED;
2333 }
2334 #endif /* CONFIG_KVM */
2335
2336 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused)
2337 {
2338 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP);
2339 }
2340
2341 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused)
2342 {
2343 set_pstate_dit(1);
2344 }
2345
2346 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused)
2347 {
2348 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn);
2349 }
2350
2351 /* Internal helper functions to match cpu capability type */
2352 static bool
2353 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
2354 {
2355 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
2356 }
2357
2358 static bool
2359 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
2360 {
2361 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
2362 }
2363
2364 static bool
2365 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
2366 {
2367 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
2368 }
2369
2370 static const struct arm64_cpu_capabilities arm64_features[] = {
2371 {
2372 .capability = ARM64_ALWAYS_BOOT,
2373 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2374 .matches = has_always,
2375 },
2376 {
2377 .capability = ARM64_ALWAYS_SYSTEM,
2378 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2379 .matches = has_always,
2380 },
2381 {
2382 .desc = "GIC system register CPU interface",
2383 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS,
2384 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2385 .matches = has_useable_gicv3_cpuif,
2386 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP)
2387 },
2388 {
2389 .desc = "Enhanced Counter Virtualization",
2390 .capability = ARM64_HAS_ECV,
2391 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2392 .matches = has_cpuid_feature,
2393 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP)
2394 },
2395 {
2396 .desc = "Enhanced Counter Virtualization (CNTPOFF)",
2397 .capability = ARM64_HAS_ECV_CNTPOFF,
2398 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2399 .matches = has_cpuid_feature,
2400 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF)
2401 },
2402 #ifdef CONFIG_ARM64_PAN
2403 {
2404 .desc = "Privileged Access Never",
2405 .capability = ARM64_HAS_PAN,
2406 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2407 .matches = has_cpuid_feature,
2408 .cpu_enable = cpu_enable_pan,
2409 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP)
2410 },
2411 #endif /* CONFIG_ARM64_PAN */
2412 #ifdef CONFIG_ARM64_EPAN
2413 {
2414 .desc = "Enhanced Privileged Access Never",
2415 .capability = ARM64_HAS_EPAN,
2416 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2417 .matches = has_cpuid_feature,
2418 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3)
2419 },
2420 #endif /* CONFIG_ARM64_EPAN */
2421 #ifdef CONFIG_ARM64_LSE_ATOMICS
2422 {
2423 .desc = "LSE atomic instructions",
2424 .capability = ARM64_HAS_LSE_ATOMICS,
2425 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2426 .matches = has_cpuid_feature,
2427 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP)
2428 },
2429 #endif /* CONFIG_ARM64_LSE_ATOMICS */
2430 {
2431 .desc = "Virtualization Host Extensions",
2432 .capability = ARM64_HAS_VIRT_HOST_EXTN,
2433 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2434 .matches = runs_at_el2,
2435 .cpu_enable = cpu_copy_el2regs,
2436 },
2437 {
2438 .desc = "Nested Virtualization Support",
2439 .capability = ARM64_HAS_NESTED_VIRT,
2440 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2441 .matches = has_nested_virt_support,
2442 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2)
2443 },
2444 {
2445 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
2446 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2447 .matches = has_32bit_el0,
2448 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32)
2449 },
2450 #ifdef CONFIG_KVM
2451 {
2452 .desc = "32-bit EL1 Support",
2453 .capability = ARM64_HAS_32BIT_EL1,
2454 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2455 .matches = has_cpuid_feature,
2456 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32)
2457 },
2458 {
2459 .desc = "Protected KVM",
2460 .capability = ARM64_KVM_PROTECTED_MODE,
2461 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2462 .matches = is_kvm_protected_mode,
2463 },
2464 {
2465 .desc = "HCRX_EL2 register",
2466 .capability = ARM64_HAS_HCX,
2467 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2468 .matches = has_cpuid_feature,
2469 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP)
2470 },
2471 #endif
2472 {
2473 .desc = "Kernel page table isolation (KPTI)",
2474 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
2475 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2476 .cpu_enable = cpu_enable_kpti,
2477 .matches = unmap_kernel_at_el0,
2478 /*
2479 * The ID feature fields below are used to indicate that
2480 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
2481 * more details.
2482 */
2483 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP)
2484 },
2485 {
2486 .capability = ARM64_HAS_FPSIMD,
2487 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2488 .matches = has_cpuid_feature,
2489 .cpu_enable = cpu_enable_fpsimd,
2490 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP)
2491 },
2492 #ifdef CONFIG_ARM64_PMEM
2493 {
2494 .desc = "Data cache clean to Point of Persistence",
2495 .capability = ARM64_HAS_DCPOP,
2496 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2497 .matches = has_cpuid_feature,
2498 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP)
2499 },
2500 {
2501 .desc = "Data cache clean to Point of Deep Persistence",
2502 .capability = ARM64_HAS_DCPODP,
2503 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2504 .matches = has_cpuid_feature,
2505 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2)
2506 },
2507 #endif
2508 #ifdef CONFIG_ARM64_SVE
2509 {
2510 .desc = "Scalable Vector Extension",
2511 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2512 .capability = ARM64_SVE,
2513 .cpu_enable = cpu_enable_sve,
2514 .matches = has_cpuid_feature,
2515 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP)
2516 },
2517 #endif /* CONFIG_ARM64_SVE */
2518 #ifdef CONFIG_ARM64_RAS_EXTN
2519 {
2520 .desc = "RAS Extension Support",
2521 .capability = ARM64_HAS_RAS_EXTN,
2522 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2523 .matches = has_cpuid_feature,
2524 .cpu_enable = cpu_clear_disr,
2525 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP)
2526 },
2527 #endif /* CONFIG_ARM64_RAS_EXTN */
2528 #ifdef CONFIG_ARM64_AMU_EXTN
2529 {
2530 .desc = "Activity Monitors Unit (AMU)",
2531 .capability = ARM64_HAS_AMU_EXTN,
2532 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2533 .matches = has_amu,
2534 .cpu_enable = cpu_amu_enable,
2535 .cpus = &amu_cpus,
2536 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP)
2537 },
2538 #endif /* CONFIG_ARM64_AMU_EXTN */
2539 {
2540 .desc = "Data cache clean to the PoU not required for I/D coherence",
2541 .capability = ARM64_HAS_CACHE_IDC,
2542 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2543 .matches = has_cache_idc,
2544 .cpu_enable = cpu_emulate_effective_ctr,
2545 },
2546 {
2547 .desc = "Instruction cache invalidation not required for I/D coherence",
2548 .capability = ARM64_HAS_CACHE_DIC,
2549 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2550 .matches = has_cache_dic,
2551 },
2552 {
2553 .desc = "Stage-2 Force Write-Back",
2554 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2555 .capability = ARM64_HAS_STAGE2_FWB,
2556 .matches = has_cpuid_feature,
2557 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP)
2558 },
2559 {
2560 .desc = "ARMv8.4 Translation Table Level",
2561 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2562 .capability = ARM64_HAS_ARMv8_4_TTL,
2563 .matches = has_cpuid_feature,
2564 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP)
2565 },
2566 {
2567 .desc = "TLB range maintenance instructions",
2568 .capability = ARM64_HAS_TLB_RANGE,
2569 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2570 .matches = has_cpuid_feature,
2571 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE)
2572 },
2573 #ifdef CONFIG_ARM64_HW_AFDBM
2574 {
2575 .desc = "Hardware dirty bit management",
2576 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2577 .capability = ARM64_HW_DBM,
2578 .matches = has_hw_dbm,
2579 .cpu_enable = cpu_enable_hw_dbm,
2580 .cpus = &dbm_cpus,
2581 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM)
2582 },
2583 #endif
2584 {
2585 .desc = "CRC32 instructions",
2586 .capability = ARM64_HAS_CRC32,
2587 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2588 .matches = has_cpuid_feature,
2589 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP)
2590 },
2591 {
2592 .desc = "Speculative Store Bypassing Safe (SSBS)",
2593 .capability = ARM64_SSBS,
2594 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2595 .matches = has_cpuid_feature,
2596 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP)
2597 },
2598 #ifdef CONFIG_ARM64_CNP
2599 {
2600 .desc = "Common not Private translations",
2601 .capability = ARM64_HAS_CNP,
2602 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2603 .matches = has_useable_cnp,
2604 .cpu_enable = cpu_enable_cnp,
2605 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP)
2606 },
2607 #endif
2608 {
2609 .desc = "Speculation barrier (SB)",
2610 .capability = ARM64_HAS_SB,
2611 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2612 .matches = has_cpuid_feature,
2613 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP)
2614 },
2615 #ifdef CONFIG_ARM64_PTR_AUTH
2616 {
2617 .desc = "Address authentication (architected QARMA5 algorithm)",
2618 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5,
2619 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2620 .matches = has_address_auth_cpucap,
2621 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth)
2622 },
2623 {
2624 .desc = "Address authentication (architected QARMA3 algorithm)",
2625 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3,
2626 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2627 .matches = has_address_auth_cpucap,
2628 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth)
2629 },
2630 {
2631 .desc = "Address authentication (IMP DEF algorithm)",
2632 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2633 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2634 .matches = has_address_auth_cpucap,
2635 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth)
2636 },
2637 {
2638 .capability = ARM64_HAS_ADDRESS_AUTH,
2639 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2640 .matches = has_address_auth_metacap,
2641 },
2642 {
2643 .desc = "Generic authentication (architected QARMA5 algorithm)",
2644 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5,
2645 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2646 .matches = has_cpuid_feature,
2647 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP)
2648 },
2649 {
2650 .desc = "Generic authentication (architected QARMA3 algorithm)",
2651 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3,
2652 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2653 .matches = has_cpuid_feature,
2654 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP)
2655 },
2656 {
2657 .desc = "Generic authentication (IMP DEF algorithm)",
2658 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2659 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2660 .matches = has_cpuid_feature,
2661 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP)
2662 },
2663 {
2664 .capability = ARM64_HAS_GENERIC_AUTH,
2665 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2666 .matches = has_generic_auth,
2667 },
2668 #endif /* CONFIG_ARM64_PTR_AUTH */
2669 #ifdef CONFIG_ARM64_PSEUDO_NMI
2670 {
2671 /*
2672 * Depends on having GICv3
2673 */
2674 .desc = "IRQ priority masking",
2675 .capability = ARM64_HAS_GIC_PRIO_MASKING,
2676 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2677 .matches = can_use_gic_priorities,
2678 },
2679 {
2680 /*
2681 * Depends on ARM64_HAS_GIC_PRIO_MASKING
2682 */
2683 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC,
2684 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2685 .matches = has_gic_prio_relaxed_sync,
2686 },
2687 #endif
2688 #ifdef CONFIG_ARM64_E0PD
2689 {
2690 .desc = "E0PD",
2691 .capability = ARM64_HAS_E0PD,
2692 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2693 .cpu_enable = cpu_enable_e0pd,
2694 .matches = has_cpuid_feature,
2695 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP)
2696 },
2697 #endif
2698 {
2699 .desc = "Random Number Generator",
2700 .capability = ARM64_HAS_RNG,
2701 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2702 .matches = has_cpuid_feature,
2703 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP)
2704 },
2705 #ifdef CONFIG_ARM64_BTI
2706 {
2707 .desc = "Branch Target Identification",
2708 .capability = ARM64_BTI,
2709 #ifdef CONFIG_ARM64_BTI_KERNEL
2710 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2711 #else
2712 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2713 #endif
2714 .matches = has_cpuid_feature,
2715 .cpu_enable = bti_enable,
2716 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP)
2717 },
2718 #endif
2719 #ifdef CONFIG_ARM64_MTE
2720 {
2721 .desc = "Memory Tagging Extension",
2722 .capability = ARM64_MTE,
2723 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2724 .matches = has_cpuid_feature,
2725 .cpu_enable = cpu_enable_mte,
2726 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2)
2727 },
2728 {
2729 .desc = "Asymmetric MTE Tag Check Fault",
2730 .capability = ARM64_MTE_ASYMM,
2731 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2732 .matches = has_cpuid_feature,
2733 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3)
2734 },
2735 #endif /* CONFIG_ARM64_MTE */
2736 {
2737 .desc = "RCpc load-acquire (LDAPR)",
2738 .capability = ARM64_HAS_LDAPR,
2739 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2740 .matches = has_cpuid_feature,
2741 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP)
2742 },
2743 {
2744 .desc = "Fine Grained Traps",
2745 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2746 .capability = ARM64_HAS_FGT,
2747 .matches = has_cpuid_feature,
2748 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP)
2749 },
2750 #ifdef CONFIG_ARM64_SME
2751 {
2752 .desc = "Scalable Matrix Extension",
2753 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2754 .capability = ARM64_SME,
2755 .matches = has_cpuid_feature,
2756 .cpu_enable = cpu_enable_sme,
2757 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP)
2758 },
2759 /* FA64 should be sorted after the base SME capability */
2760 {
2761 .desc = "FA64",
2762 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2763 .capability = ARM64_SME_FA64,
2764 .matches = has_cpuid_feature,
2765 .cpu_enable = cpu_enable_fa64,
2766 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP)
2767 },
2768 {
2769 .desc = "SME2",
2770 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2771 .capability = ARM64_SME2,
2772 .matches = has_cpuid_feature,
2773 .cpu_enable = cpu_enable_sme2,
2774 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2)
2775 },
2776 #endif /* CONFIG_ARM64_SME */
2777 {
2778 .desc = "WFx with timeout",
2779 .capability = ARM64_HAS_WFXT,
2780 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2781 .matches = has_cpuid_feature,
2782 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP)
2783 },
2784 {
2785 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality",
2786 .capability = ARM64_HAS_TIDCP1,
2787 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2788 .matches = has_cpuid_feature,
2789 .cpu_enable = cpu_trap_el0_impdef,
2790 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP)
2791 },
2792 {
2793 .desc = "Data independent timing control (DIT)",
2794 .capability = ARM64_HAS_DIT,
2795 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2796 .matches = has_cpuid_feature,
2797 .cpu_enable = cpu_enable_dit,
2798 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP)
2799 },
2800 {
2801 .desc = "Memory Copy and Memory Set instructions",
2802 .capability = ARM64_HAS_MOPS,
2803 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2804 .matches = has_cpuid_feature,
2805 .cpu_enable = cpu_enable_mops,
2806 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP)
2807 },
2808 {
2809 .capability = ARM64_HAS_TCR2,
2810 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2811 .matches = has_cpuid_feature,
2812 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP)
2813 },
2814 {
2815 .desc = "Stage-1 Permission Indirection Extension (S1PIE)",
2816 .capability = ARM64_HAS_S1PIE,
2817 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2818 .matches = has_cpuid_feature,
2819 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP)
2820 },
2821 {
2822 .desc = "VHE for hypervisor only",
2823 .capability = ARM64_KVM_HVHE,
2824 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2825 .matches = hvhe_possible,
2826 },
2827 {
2828 .desc = "Enhanced Virtualization Traps",
2829 .capability = ARM64_HAS_EVT,
2830 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2831 .matches = has_cpuid_feature,
2832 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP)
2833 },
2834 {
2835 .desc = "52-bit Virtual Addressing for KVM (LPA2)",
2836 .capability = ARM64_HAS_LPA2,
2837 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2838 .matches = has_lpa2,
2839 },
2840 {
2841 .desc = "FPMR",
2842 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2843 .capability = ARM64_HAS_FPMR,
2844 .matches = has_cpuid_feature,
2845 .cpu_enable = cpu_enable_fpmr,
2846 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP)
2847 },
2848 #ifdef CONFIG_ARM64_VA_BITS_52
2849 {
2850 .capability = ARM64_HAS_VA52,
2851 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2852 .matches = has_cpuid_feature,
2853 #ifdef CONFIG_ARM64_64K_PAGES
2854 .desc = "52-bit Virtual Addressing (LVA)",
2855 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52)
2856 #else
2857 .desc = "52-bit Virtual Addressing (LPA2)",
2858 #ifdef CONFIG_ARM64_4K_PAGES
2859 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT)
2860 #else
2861 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT)
2862 #endif
2863 #endif
2864 },
2865 #endif
2866 {
2867 .desc = "NV1",
2868 .capability = ARM64_HAS_HCR_NV1,
2869 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2870 .matches = has_nv1,
2871 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1)
2872 },
2873 {},
2874 };
2875
2876 #define HWCAP_CPUID_MATCH(reg, field, min_value) \
2877 .matches = has_user_cpuid_feature, \
2878 ARM64_CPUID_FIELDS(reg, field, min_value)
2879
2880 #define __HWCAP_CAP(name, cap_type, cap) \
2881 .desc = name, \
2882 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2883 .hwcap_type = cap_type, \
2884 .hwcap = cap, \
2885
2886 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \
2887 { \
2888 __HWCAP_CAP(#cap, cap_type, cap) \
2889 HWCAP_CPUID_MATCH(reg, field, min_value) \
2890 }
2891
2892 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
2893 { \
2894 __HWCAP_CAP(#cap, cap_type, cap) \
2895 .matches = cpucap_multi_entry_cap_matches, \
2896 .match_list = list, \
2897 }
2898
2899 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
2900 { \
2901 __HWCAP_CAP(#cap, cap_type, cap) \
2902 .matches = match, \
2903 }
2904
2905 #ifdef CONFIG_ARM64_PTR_AUTH
2906 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2907 {
2908 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth)
2909 },
2910 {
2911 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth)
2912 },
2913 {
2914 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth)
2915 },
2916 {},
2917 };
2918
2919 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2920 {
2921 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP)
2922 },
2923 {
2924 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP)
2925 },
2926 {
2927 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP)
2928 },
2929 {},
2930 };
2931 #endif
2932
2933 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2934 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2935 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES),
2936 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2937 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2938 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2939 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2940 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2941 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128),
2942 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2943 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2944 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3),
2945 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4),
2946 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2947 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2948 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2949 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2950 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG),
2951 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP),
2952 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2953 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2954 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2955 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT),
2956 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR),
2957 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2958 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2959 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2960 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2961 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2962 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2963 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3),
2964 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2965 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB),
2966 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16),
2967 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16),
2968 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH),
2969 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2970 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT),
2971 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX),
2972 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2973 #ifdef CONFIG_ARM64_SVE
2974 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),
2975 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),
2976 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2977 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2978 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2979 HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2980 HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16),
2981 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2982 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),
2983 HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2984 HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2985 HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2986 HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2987 HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2988 #endif
2989 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2990 #ifdef CONFIG_ARM64_BTI
2991 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI),
2992 #endif
2993 #ifdef CONFIG_ARM64_PTR_AUTH
2994 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2995 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2996 #endif
2997 #ifdef CONFIG_ARM64_MTE
2998 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE),
2999 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3),
3000 #endif /* CONFIG_ARM64_MTE */
3001 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV),
3002 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP),
3003 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC),
3004 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM),
3005 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES),
3006 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
3007 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS),
3008 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC),
3009 #ifdef CONFIG_ARM64_SME
3010 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
3011 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
3012 HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2),
3013 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1),
3014 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2),
3015 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
3016 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
3017 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32),
3018 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16),
3019 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16),
3020 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16),
3021 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32),
3022 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
3023 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
3024 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
3025 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32),
3026 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
3027 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA),
3028 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4),
3029 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2),
3030 #endif /* CONFIG_ARM64_SME */
3031 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT),
3032 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA),
3033 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4),
3034 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2),
3035 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3),
3036 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2),
3037 {},
3038 };
3039
3040 #ifdef CONFIG_COMPAT
3041 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
3042 {
3043 /*
3044 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
3045 * in line with that of arm32 as in vfp_init(). We make sure that the
3046 * check is future proof, by making sure value is non-zero.
3047 */
3048 u32 mvfr1;
3049
3050 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
3051 if (scope == SCOPE_SYSTEM)
3052 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
3053 else
3054 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
3055
3056 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) &&
3057 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) &&
3058 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT);
3059 }
3060 #endif
3061
3062 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
3063 #ifdef CONFIG_COMPAT
3064 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
3065 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
3066 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
3067 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
3068 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
3069 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP),
3070 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP),
3071 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
3072 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
3073 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
3074 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
3075 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
3076 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP),
3077 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM),
3078 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB),
3079 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16),
3080 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM),
3081 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS),
3082 #endif
3083 {},
3084 };
3085
3086 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
3087 {
3088 switch (cap->hwcap_type) {
3089 case CAP_HWCAP:
3090 cpu_set_feature(cap->hwcap);
3091 break;
3092 #ifdef CONFIG_COMPAT
3093 case CAP_COMPAT_HWCAP:
3094 compat_elf_hwcap |= (u32)cap->hwcap;
3095 break;
3096 case CAP_COMPAT_HWCAP2:
3097 compat_elf_hwcap2 |= (u32)cap->hwcap;
3098 break;
3099 #endif
3100 default:
3101 WARN_ON(1);
3102 break;
3103 }
3104 }
3105
3106 /* Check if we have a particular HWCAP enabled */
3107 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
3108 {
3109 bool rc;
3110
3111 switch (cap->hwcap_type) {
3112 case CAP_HWCAP:
3113 rc = cpu_have_feature(cap->hwcap);
3114 break;
3115 #ifdef CONFIG_COMPAT
3116 case CAP_COMPAT_HWCAP:
3117 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
3118 break;
3119 case CAP_COMPAT_HWCAP2:
3120 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
3121 break;
3122 #endif
3123 default:
3124 WARN_ON(1);
3125 rc = false;
3126 }
3127
3128 return rc;
3129 }
3130
3131 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
3132 {
3133 /* We support emulation of accesses to CPU ID feature registers */
3134 cpu_set_named_feature(CPUID);
3135 for (; hwcaps->matches; hwcaps++)
3136 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
3137 cap_set_elf_hwcap(hwcaps);
3138 }
3139
3140 static void update_cpu_capabilities(u16 scope_mask)
3141 {
3142 int i;
3143 const struct arm64_cpu_capabilities *caps;
3144
3145 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3146 for (i = 0; i < ARM64_NCAPS; i++) {
3147 caps = cpucap_ptrs[i];
3148 if (!caps || !(caps->type & scope_mask) ||
3149 cpus_have_cap(caps->capability) ||
3150 !caps->matches(caps, cpucap_default_scope(caps)))
3151 continue;
3152
3153 if (caps->desc && !caps->cpus)
3154 pr_info("detected: %s\n", caps->desc);
3155
3156 __set_bit(caps->capability, system_cpucaps);
3157
3158 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
3159 set_bit(caps->capability, boot_cpucaps);
3160 }
3161 }
3162
3163 /*
3164 * Enable all the available capabilities on this CPU. The capabilities
3165 * with BOOT_CPU scope are handled separately and hence skipped here.
3166 */
3167 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
3168 {
3169 int i;
3170 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
3171
3172 for_each_available_cap(i) {
3173 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i];
3174
3175 if (WARN_ON(!cap))
3176 continue;
3177
3178 if (!(cap->type & non_boot_scope))
3179 continue;
3180
3181 if (cap->cpu_enable)
3182 cap->cpu_enable(cap);
3183 }
3184 return 0;
3185 }
3186
3187 /*
3188 * Run through the enabled capabilities and enable() it on all active
3189 * CPUs
3190 */
3191 static void __init enable_cpu_capabilities(u16 scope_mask)
3192 {
3193 int i;
3194 const struct arm64_cpu_capabilities *caps;
3195 bool boot_scope;
3196
3197 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3198 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
3199
3200 for (i = 0; i < ARM64_NCAPS; i++) {
3201 caps = cpucap_ptrs[i];
3202 if (!caps || !(caps->type & scope_mask) ||
3203 !cpus_have_cap(caps->capability))
3204 continue;
3205
3206 if (boot_scope && caps->cpu_enable)
3207 /*
3208 * Capabilities with SCOPE_BOOT_CPU scope are finalised
3209 * before any secondary CPU boots. Thus, each secondary
3210 * will enable the capability as appropriate via
3211 * check_local_cpu_capabilities(). The only exception is
3212 * the boot CPU, for which the capability must be
3213 * enabled here. This approach avoids costly
3214 * stop_machine() calls for this case.
3215 */
3216 caps->cpu_enable(caps);
3217 }
3218
3219 /*
3220 * For all non-boot scope capabilities, use stop_machine()
3221 * as it schedules the work allowing us to modify PSTATE,
3222 * instead of on_each_cpu() which uses an IPI, giving us a
3223 * PSTATE that disappears when we return.
3224 */
3225 if (!boot_scope)
3226 stop_machine(cpu_enable_non_boot_scope_capabilities,
3227 NULL, cpu_online_mask);
3228 }
3229
3230 /*
3231 * Run through the list of capabilities to check for conflicts.
3232 * If the system has already detected a capability, take necessary
3233 * action on this CPU.
3234 */
3235 static void verify_local_cpu_caps(u16 scope_mask)
3236 {
3237 int i;
3238 bool cpu_has_cap, system_has_cap;
3239 const struct arm64_cpu_capabilities *caps;
3240
3241 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3242
3243 for (i = 0; i < ARM64_NCAPS; i++) {
3244 caps = cpucap_ptrs[i];
3245 if (!caps || !(caps->type & scope_mask))
3246 continue;
3247
3248 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
3249 system_has_cap = cpus_have_cap(caps->capability);
3250
3251 if (system_has_cap) {
3252 /*
3253 * Check if the new CPU misses an advertised feature,
3254 * which is not safe to miss.
3255 */
3256 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
3257 break;
3258 /*
3259 * We have to issue cpu_enable() irrespective of
3260 * whether the CPU has it or not, as it is enabeld
3261 * system wide. It is upto the call back to take
3262 * appropriate action on this CPU.
3263 */
3264 if (caps->cpu_enable)
3265 caps->cpu_enable(caps);
3266 } else {
3267 /*
3268 * Check if the CPU has this capability if it isn't
3269 * safe to have when the system doesn't.
3270 */
3271 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
3272 break;
3273 }
3274 }
3275
3276 if (i < ARM64_NCAPS) {
3277 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
3278 smp_processor_id(), caps->capability,
3279 caps->desc, system_has_cap, cpu_has_cap);
3280
3281 if (cpucap_panic_on_conflict(caps))
3282 cpu_panic_kernel();
3283 else
3284 cpu_die_early();
3285 }
3286 }
3287
3288 /*
3289 * Check for CPU features that are used in early boot
3290 * based on the Boot CPU value.
3291 */
3292 static void check_early_cpu_features(void)
3293 {
3294 verify_cpu_asid_bits();
3295
3296 verify_local_cpu_caps(SCOPE_BOOT_CPU);
3297 }
3298
3299 static void
3300 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
3301 {
3302
3303 for (; caps->matches; caps++)
3304 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
3305 pr_crit("CPU%d: missing HWCAP: %s\n",
3306 smp_processor_id(), caps->desc);
3307 cpu_die_early();
3308 }
3309 }
3310
3311 static void verify_local_elf_hwcaps(void)
3312 {
3313 __verify_local_elf_hwcaps(arm64_elf_hwcaps);
3314
3315 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
3316 __verify_local_elf_hwcaps(compat_elf_hwcaps);
3317 }
3318
3319 static void verify_sve_features(void)
3320 {
3321 unsigned long cpacr = cpacr_save_enable_kernel_sve();
3322
3323 if (vec_verify_vq_map(ARM64_VEC_SVE)) {
3324 pr_crit("CPU%d: SVE: vector length support mismatch\n",
3325 smp_processor_id());
3326 cpu_die_early();
3327 }
3328
3329 cpacr_restore(cpacr);
3330 }
3331
3332 static void verify_sme_features(void)
3333 {
3334 unsigned long cpacr = cpacr_save_enable_kernel_sme();
3335
3336 if (vec_verify_vq_map(ARM64_VEC_SME)) {
3337 pr_crit("CPU%d: SME: vector length support mismatch\n",
3338 smp_processor_id());
3339 cpu_die_early();
3340 }
3341
3342 cpacr_restore(cpacr);
3343 }
3344
3345 static void verify_hyp_capabilities(void)
3346 {
3347 u64 safe_mmfr1, mmfr0, mmfr1;
3348 int parange, ipa_max;
3349 unsigned int safe_vmid_bits, vmid_bits;
3350
3351 if (!IS_ENABLED(CONFIG_KVM))
3352 return;
3353
3354 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
3355 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
3356 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
3357
3358 /* Verify VMID bits */
3359 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
3360 vmid_bits = get_vmid_bits(mmfr1);
3361 if (vmid_bits < safe_vmid_bits) {
3362 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
3363 cpu_die_early();
3364 }
3365
3366 /* Verify IPA range */
3367 parange = cpuid_feature_extract_unsigned_field(mmfr0,
3368 ID_AA64MMFR0_EL1_PARANGE_SHIFT);
3369 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
3370 if (ipa_max < get_kvm_ipa_limit()) {
3371 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
3372 cpu_die_early();
3373 }
3374 }
3375
3376 /*
3377 * Run through the enabled system capabilities and enable() it on this CPU.
3378 * The capabilities were decided based on the available CPUs at the boot time.
3379 * Any new CPU should match the system wide status of the capability. If the
3380 * new CPU doesn't have a capability which the system now has enabled, we
3381 * cannot do anything to fix it up and could cause unexpected failures. So
3382 * we park the CPU.
3383 */
3384 static void verify_local_cpu_capabilities(void)
3385 {
3386 /*
3387 * The capabilities with SCOPE_BOOT_CPU are checked from
3388 * check_early_cpu_features(), as they need to be verified
3389 * on all secondary CPUs.
3390 */
3391 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3392 verify_local_elf_hwcaps();
3393
3394 if (system_supports_sve())
3395 verify_sve_features();
3396
3397 if (system_supports_sme())
3398 verify_sme_features();
3399
3400 if (is_hyp_mode_available())
3401 verify_hyp_capabilities();
3402 }
3403
3404 void check_local_cpu_capabilities(void)
3405 {
3406 /*
3407 * All secondary CPUs should conform to the early CPU features
3408 * in use by the kernel based on boot CPU.
3409 */
3410 check_early_cpu_features();
3411
3412 /*
3413 * If we haven't finalised the system capabilities, this CPU gets
3414 * a chance to update the errata work arounds and local features.
3415 * Otherwise, this CPU should verify that it has all the system
3416 * advertised capabilities.
3417 */
3418 if (!system_capabilities_finalized())
3419 update_cpu_capabilities(SCOPE_LOCAL_CPU);
3420 else
3421 verify_local_cpu_capabilities();
3422 }
3423
3424 bool this_cpu_has_cap(unsigned int n)
3425 {
3426 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
3427 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n];
3428
3429 if (cap)
3430 return cap->matches(cap, SCOPE_LOCAL_CPU);
3431 }
3432
3433 return false;
3434 }
3435 EXPORT_SYMBOL_GPL(this_cpu_has_cap);
3436
3437 /*
3438 * This helper function is used in a narrow window when,
3439 * - The system wide safe registers are set with all the SMP CPUs and,
3440 * - The SYSTEM_FEATURE system_cpucaps may not have been set.
3441 */
3442 static bool __maybe_unused __system_matches_cap(unsigned int n)
3443 {
3444 if (n < ARM64_NCAPS) {
3445 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n];
3446
3447 if (cap)
3448 return cap->matches(cap, SCOPE_SYSTEM);
3449 }
3450 return false;
3451 }
3452
3453 void cpu_set_feature(unsigned int num)
3454 {
3455 set_bit(num, elf_hwcap);
3456 }
3457
3458 bool cpu_have_feature(unsigned int num)
3459 {
3460 return test_bit(num, elf_hwcap);
3461 }
3462 EXPORT_SYMBOL_GPL(cpu_have_feature);
3463
3464 unsigned long cpu_get_elf_hwcap(void)
3465 {
3466 /*
3467 * We currently only populate the first 32 bits of AT_HWCAP. Please
3468 * note that for userspace compatibility we guarantee that bits 62
3469 * and 63 will always be returned as 0.
3470 */
3471 return elf_hwcap[0];
3472 }
3473
3474 unsigned long cpu_get_elf_hwcap2(void)
3475 {
3476 return elf_hwcap[1];
3477 }
3478
3479 static void __init setup_boot_cpu_capabilities(void)
3480 {
3481 /*
3482 * The boot CPU's feature register values have been recorded. Detect
3483 * boot cpucaps and local cpucaps for the boot CPU, then enable and
3484 * patch alternatives for the available boot cpucaps.
3485 */
3486 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
3487 enable_cpu_capabilities(SCOPE_BOOT_CPU);
3488 apply_boot_alternatives();
3489 }
3490
3491 void __init setup_boot_cpu_features(void)
3492 {
3493 /*
3494 * Initialize the indirect array of CPU capabilities pointers before we
3495 * handle the boot CPU.
3496 */
3497 init_cpucap_indirect_list();
3498
3499 /*
3500 * Detect broken pseudo-NMI. Must be called _before_ the call to
3501 * setup_boot_cpu_capabilities() since it interacts with
3502 * can_use_gic_priorities().
3503 */
3504 detect_system_supports_pseudo_nmi();
3505
3506 setup_boot_cpu_capabilities();
3507 }
3508
3509 static void __init setup_system_capabilities(void)
3510 {
3511 /*
3512 * The system-wide safe feature register values have been finalized.
3513 * Detect, enable, and patch alternatives for the available system
3514 * cpucaps.
3515 */
3516 update_cpu_capabilities(SCOPE_SYSTEM);
3517 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3518 apply_alternatives_all();
3519
3520 /*
3521 * Log any cpucaps with a cpumask as these aren't logged by
3522 * update_cpu_capabilities().
3523 */
3524 for (int i = 0; i < ARM64_NCAPS; i++) {
3525 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i];
3526
3527 if (caps && caps->cpus && caps->desc &&
3528 cpumask_any(caps->cpus) < nr_cpu_ids)
3529 pr_info("detected: %s on CPU%*pbl\n",
3530 caps->desc, cpumask_pr_args(caps->cpus));
3531 }
3532
3533 /*
3534 * TTBR0 PAN doesn't have its own cpucap, so log it manually.
3535 */
3536 if (system_uses_ttbr0_pan())
3537 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
3538 }
3539
3540 void __init setup_system_features(void)
3541 {
3542 setup_system_capabilities();
3543
3544 kpti_install_ng_mappings();
3545
3546 sve_setup();
3547 sme_setup();
3548
3549 /*
3550 * Check for sane CTR_EL0.CWG value.
3551 */
3552 if (!cache_type_cwg())
3553 pr_warn("No Cache Writeback Granule information, assuming %d\n",
3554 ARCH_DMA_MINALIGN);
3555 }
3556
3557 void __init setup_user_features(void)
3558 {
3559 user_feature_fixup();
3560
3561 setup_elf_hwcaps(arm64_elf_hwcaps);
3562
3563 if (system_supports_32bit_el0()) {
3564 setup_elf_hwcaps(compat_elf_hwcaps);
3565 elf_hwcap_fixup();
3566 }
3567
3568 minsigstksz_setup();
3569 }
3570
3571 static int enable_mismatched_32bit_el0(unsigned int cpu)
3572 {
3573 /*
3574 * The first 32-bit-capable CPU we detected and so can no longer
3575 * be offlined by userspace. -1 indicates we haven't yet onlined
3576 * a 32-bit-capable CPU.
3577 */
3578 static int lucky_winner = -1;
3579
3580 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
3581 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
3582
3583 if (cpu_32bit) {
3584 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
3585 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
3586 }
3587
3588 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit)
3589 return 0;
3590
3591 if (lucky_winner >= 0)
3592 return 0;
3593
3594 /*
3595 * We've detected a mismatch. We need to keep one of our CPUs with
3596 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting
3597 * every CPU in the system for a 32-bit task.
3598 */
3599 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
3600 cpu_active_mask);
3601 get_cpu_device(lucky_winner)->offline_disabled = true;
3602 setup_elf_hwcaps(compat_elf_hwcaps);
3603 elf_hwcap_fixup();
3604 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
3605 cpu, lucky_winner);
3606 return 0;
3607 }
3608
3609 static int __init init_32bit_el0_mask(void)
3610 {
3611 if (!allow_mismatched_32bit_el0)
3612 return 0;
3613
3614 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
3615 return -ENOMEM;
3616
3617 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
3618 "arm64/mismatched_32bit_el0:online",
3619 enable_mismatched_32bit_el0, NULL);
3620 }
3621 subsys_initcall_sync(init_32bit_el0_mask);
3622
3623 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
3624 {
3625 cpu_enable_swapper_cnp();
3626 }
3627
3628 /*
3629 * We emulate only the following system register space.
3630 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7]
3631 * See Table C5-6 System instruction encodings for System register accesses,
3632 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
3633 */
3634 static inline bool __attribute_const__ is_emulated(u32 id)
3635 {
3636 return (sys_reg_Op0(id) == 0x3 &&
3637 sys_reg_CRn(id) == 0x0 &&
3638 sys_reg_Op1(id) == 0x0 &&
3639 (sys_reg_CRm(id) == 0 ||
3640 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7))));
3641 }
3642
3643 /*
3644 * With CRm == 0, reg should be one of :
3645 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
3646 */
3647 static inline int emulate_id_reg(u32 id, u64 *valp)
3648 {
3649 switch (id) {
3650 case SYS_MIDR_EL1:
3651 *valp = read_cpuid_id();
3652 break;
3653 case SYS_MPIDR_EL1:
3654 *valp = SYS_MPIDR_SAFE_VAL;
3655 break;
3656 case SYS_REVIDR_EL1:
3657 /* IMPLEMENTATION DEFINED values are emulated with 0 */
3658 *valp = 0;
3659 break;
3660 default:
3661 return -EINVAL;
3662 }
3663
3664 return 0;
3665 }
3666
3667 static int emulate_sys_reg(u32 id, u64 *valp)
3668 {
3669 struct arm64_ftr_reg *regp;
3670
3671 if (!is_emulated(id))
3672 return -EINVAL;
3673
3674 if (sys_reg_CRm(id) == 0)
3675 return emulate_id_reg(id, valp);
3676
3677 regp = get_arm64_ftr_reg_nowarn(id);
3678 if (regp)
3679 *valp = arm64_ftr_reg_user_value(regp);
3680 else
3681 /*
3682 * The untracked registers are either IMPLEMENTATION DEFINED
3683 * (e.g, ID_AFR0_EL1) or reserved RAZ.
3684 */
3685 *valp = 0;
3686 return 0;
3687 }
3688
3689 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3690 {
3691 int rc;
3692 u64 val;
3693
3694 rc = emulate_sys_reg(sys_reg, &val);
3695 if (!rc) {
3696 pt_regs_write_reg(regs, rt, val);
3697 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3698 }
3699 return rc;
3700 }
3701
3702 bool try_emulate_mrs(struct pt_regs *regs, u32 insn)
3703 {
3704 u32 sys_reg, rt;
3705
3706 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn))
3707 return false;
3708
3709 /*
3710 * sys_reg values are defined as used in mrs/msr instruction.
3711 * shift the imm value to get the encoding.
3712 */
3713 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3714 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3715 return do_emulate_mrs(regs, sys_reg, rt) == 0;
3716 }
3717
3718 enum mitigation_state arm64_get_meltdown_state(void)
3719 {
3720 if (__meltdown_safe)
3721 return SPECTRE_UNAFFECTED;
3722
3723 if (arm64_kernel_unmapped_at_el0())
3724 return SPECTRE_MITIGATED;
3725
3726 return SPECTRE_VULNERABLE;
3727 }
3728
3729 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3730 char *buf)
3731 {
3732 switch (arm64_get_meltdown_state()) {
3733 case SPECTRE_UNAFFECTED:
3734 return sprintf(buf, "Not affected\n");
3735
3736 case SPECTRE_MITIGATED:
3737 return sprintf(buf, "Mitigation: PTI\n");
3738
3739 default:
3740 return sprintf(buf, "Vulnerable\n");
3741 }
3742 }
3743
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