1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2016 - Linaro and Columbia University
4 * Author: Jintack Lim <jintack.lim@linaro.org>
5 */
6
7 #include <linux/kvm.h>
8 #include <linux/kvm_host.h>
9
10 #include <asm/kvm_emulate.h>
11 #include <asm/kvm_nested.h>
12
13 #include "hyp/include/hyp/adjust_pc.h"
14
15 #include "trace.h"
16
17 enum trap_behaviour {
18 BEHAVE_HANDLE_LOCALLY = 0,
19 BEHAVE_FORWARD_READ = BIT(0),
20 BEHAVE_FORWARD_WRITE = BIT(1),
21 BEHAVE_FORWARD_ANY = BEHAVE_FORWARD_READ | BEHAVE_FORWARD_WRITE,
22 };
23
24 struct trap_bits {
25 const enum vcpu_sysreg index;
26 const enum trap_behaviour behaviour;
27 const u64 value;
28 const u64 mask;
29 };
30
31 /* Coarse Grained Trap definitions */
32 enum cgt_group_id {
33 /* Indicates no coarse trap control */
34 __RESERVED__,
35
36 /*
37 * The first batch of IDs denote coarse trapping that are used
38 * on their own instead of being part of a combination of
39 * trap controls.
40 */
41 CGT_HCR_TID1,
42 CGT_HCR_TID2,
43 CGT_HCR_TID3,
44 CGT_HCR_IMO,
45 CGT_HCR_FMO,
46 CGT_HCR_TIDCP,
47 CGT_HCR_TACR,
48 CGT_HCR_TSW,
49 CGT_HCR_TPC,
50 CGT_HCR_TPU,
51 CGT_HCR_TTLB,
52 CGT_HCR_TVM,
53 CGT_HCR_TDZ,
54 CGT_HCR_TRVM,
55 CGT_HCR_TLOR,
56 CGT_HCR_TERR,
57 CGT_HCR_APK,
58 CGT_HCR_NV,
59 CGT_HCR_NV_nNV2,
60 CGT_HCR_NV1_nNV2,
61 CGT_HCR_AT,
62 CGT_HCR_nFIEN,
63 CGT_HCR_TID4,
64 CGT_HCR_TICAB,
65 CGT_HCR_TOCU,
66 CGT_HCR_ENSCXT,
67 CGT_HCR_TTLBIS,
68 CGT_HCR_TTLBOS,
69
70 CGT_MDCR_TPMCR,
71 CGT_MDCR_TPM,
72 CGT_MDCR_TDE,
73 CGT_MDCR_TDA,
74 CGT_MDCR_TDOSA,
75 CGT_MDCR_TDRA,
76 CGT_MDCR_E2PB,
77 CGT_MDCR_TPMS,
78 CGT_MDCR_TTRF,
79 CGT_MDCR_E2TB,
80 CGT_MDCR_TDCC,
81
82 CGT_CPACR_E0POE,
83 CGT_CPTR_TAM,
84 CGT_CPTR_TCPAC,
85
86 CGT_HCRX_TCR2En,
87
88 /*
89 * Anything after this point is a combination of coarse trap
90 * controls, which must all be evaluated to decide what to do.
91 */
92 __MULTIPLE_CONTROL_BITS__,
93 CGT_HCR_IMO_FMO = __MULTIPLE_CONTROL_BITS__,
94 CGT_HCR_TID2_TID4,
95 CGT_HCR_TTLB_TTLBIS,
96 CGT_HCR_TTLB_TTLBOS,
97 CGT_HCR_TVM_TRVM,
98 CGT_HCR_TVM_TRVM_HCRX_TCR2En,
99 CGT_HCR_TPU_TICAB,
100 CGT_HCR_TPU_TOCU,
101 CGT_HCR_NV1_nNV2_ENSCXT,
102 CGT_MDCR_TPM_TPMCR,
103 CGT_MDCR_TDE_TDA,
104 CGT_MDCR_TDE_TDOSA,
105 CGT_MDCR_TDE_TDRA,
106 CGT_MDCR_TDCC_TDE_TDA,
107
108 /*
109 * Anything after this point requires a callback evaluating a
110 * complex trap condition. Ugly stuff.
111 */
112 __COMPLEX_CONDITIONS__,
113 CGT_CNTHCTL_EL1PCTEN = __COMPLEX_CONDITIONS__,
114 CGT_CNTHCTL_EL1PTEN,
115
116 CGT_CPTR_TTA,
117
118 /* Must be last */
119 __NR_CGT_GROUP_IDS__
120 };
121
122 static const struct trap_bits coarse_trap_bits[] = {
123 [CGT_HCR_TID1] = {
124 .index = HCR_EL2,
125 .value = HCR_TID1,
126 .mask = HCR_TID1,
127 .behaviour = BEHAVE_FORWARD_READ,
128 },
129 [CGT_HCR_TID2] = {
130 .index = HCR_EL2,
131 .value = HCR_TID2,
132 .mask = HCR_TID2,
133 .behaviour = BEHAVE_FORWARD_ANY,
134 },
135 [CGT_HCR_TID3] = {
136 .index = HCR_EL2,
137 .value = HCR_TID3,
138 .mask = HCR_TID3,
139 .behaviour = BEHAVE_FORWARD_READ,
140 },
141 [CGT_HCR_IMO] = {
142 .index = HCR_EL2,
143 .value = HCR_IMO,
144 .mask = HCR_IMO,
145 .behaviour = BEHAVE_FORWARD_WRITE,
146 },
147 [CGT_HCR_FMO] = {
148 .index = HCR_EL2,
149 .value = HCR_FMO,
150 .mask = HCR_FMO,
151 .behaviour = BEHAVE_FORWARD_WRITE,
152 },
153 [CGT_HCR_TIDCP] = {
154 .index = HCR_EL2,
155 .value = HCR_TIDCP,
156 .mask = HCR_TIDCP,
157 .behaviour = BEHAVE_FORWARD_ANY,
158 },
159 [CGT_HCR_TACR] = {
160 .index = HCR_EL2,
161 .value = HCR_TACR,
162 .mask = HCR_TACR,
163 .behaviour = BEHAVE_FORWARD_ANY,
164 },
165 [CGT_HCR_TSW] = {
166 .index = HCR_EL2,
167 .value = HCR_TSW,
168 .mask = HCR_TSW,
169 .behaviour = BEHAVE_FORWARD_ANY,
170 },
171 [CGT_HCR_TPC] = { /* Also called TCPC when FEAT_DPB is implemented */
172 .index = HCR_EL2,
173 .value = HCR_TPC,
174 .mask = HCR_TPC,
175 .behaviour = BEHAVE_FORWARD_ANY,
176 },
177 [CGT_HCR_TPU] = {
178 .index = HCR_EL2,
179 .value = HCR_TPU,
180 .mask = HCR_TPU,
181 .behaviour = BEHAVE_FORWARD_ANY,
182 },
183 [CGT_HCR_TTLB] = {
184 .index = HCR_EL2,
185 .value = HCR_TTLB,
186 .mask = HCR_TTLB,
187 .behaviour = BEHAVE_FORWARD_ANY,
188 },
189 [CGT_HCR_TVM] = {
190 .index = HCR_EL2,
191 .value = HCR_TVM,
192 .mask = HCR_TVM,
193 .behaviour = BEHAVE_FORWARD_WRITE,
194 },
195 [CGT_HCR_TDZ] = {
196 .index = HCR_EL2,
197 .value = HCR_TDZ,
198 .mask = HCR_TDZ,
199 .behaviour = BEHAVE_FORWARD_ANY,
200 },
201 [CGT_HCR_TRVM] = {
202 .index = HCR_EL2,
203 .value = HCR_TRVM,
204 .mask = HCR_TRVM,
205 .behaviour = BEHAVE_FORWARD_READ,
206 },
207 [CGT_HCR_TLOR] = {
208 .index = HCR_EL2,
209 .value = HCR_TLOR,
210 .mask = HCR_TLOR,
211 .behaviour = BEHAVE_FORWARD_ANY,
212 },
213 [CGT_HCR_TERR] = {
214 .index = HCR_EL2,
215 .value = HCR_TERR,
216 .mask = HCR_TERR,
217 .behaviour = BEHAVE_FORWARD_ANY,
218 },
219 [CGT_HCR_APK] = {
220 .index = HCR_EL2,
221 .value = 0,
222 .mask = HCR_APK,
223 .behaviour = BEHAVE_FORWARD_ANY,
224 },
225 [CGT_HCR_NV] = {
226 .index = HCR_EL2,
227 .value = HCR_NV,
228 .mask = HCR_NV,
229 .behaviour = BEHAVE_FORWARD_ANY,
230 },
231 [CGT_HCR_NV_nNV2] = {
232 .index = HCR_EL2,
233 .value = HCR_NV,
234 .mask = HCR_NV | HCR_NV2,
235 .behaviour = BEHAVE_FORWARD_ANY,
236 },
237 [CGT_HCR_NV1_nNV2] = {
238 .index = HCR_EL2,
239 .value = HCR_NV | HCR_NV1,
240 .mask = HCR_NV | HCR_NV1 | HCR_NV2,
241 .behaviour = BEHAVE_FORWARD_ANY,
242 },
243 [CGT_HCR_AT] = {
244 .index = HCR_EL2,
245 .value = HCR_AT,
246 .mask = HCR_AT,
247 .behaviour = BEHAVE_FORWARD_ANY,
248 },
249 [CGT_HCR_nFIEN] = {
250 .index = HCR_EL2,
251 .value = 0,
252 .mask = HCR_FIEN,
253 .behaviour = BEHAVE_FORWARD_ANY,
254 },
255 [CGT_HCR_TID4] = {
256 .index = HCR_EL2,
257 .value = HCR_TID4,
258 .mask = HCR_TID4,
259 .behaviour = BEHAVE_FORWARD_ANY,
260 },
261 [CGT_HCR_TICAB] = {
262 .index = HCR_EL2,
263 .value = HCR_TICAB,
264 .mask = HCR_TICAB,
265 .behaviour = BEHAVE_FORWARD_ANY,
266 },
267 [CGT_HCR_TOCU] = {
268 .index = HCR_EL2,
269 .value = HCR_TOCU,
270 .mask = HCR_TOCU,
271 .behaviour = BEHAVE_FORWARD_ANY,
272 },
273 [CGT_HCR_ENSCXT] = {
274 .index = HCR_EL2,
275 .value = 0,
276 .mask = HCR_ENSCXT,
277 .behaviour = BEHAVE_FORWARD_ANY,
278 },
279 [CGT_HCR_TTLBIS] = {
280 .index = HCR_EL2,
281 .value = HCR_TTLBIS,
282 .mask = HCR_TTLBIS,
283 .behaviour = BEHAVE_FORWARD_ANY,
284 },
285 [CGT_HCR_TTLBOS] = {
286 .index = HCR_EL2,
287 .value = HCR_TTLBOS,
288 .mask = HCR_TTLBOS,
289 .behaviour = BEHAVE_FORWARD_ANY,
290 },
291 [CGT_MDCR_TPMCR] = {
292 .index = MDCR_EL2,
293 .value = MDCR_EL2_TPMCR,
294 .mask = MDCR_EL2_TPMCR,
295 .behaviour = BEHAVE_FORWARD_ANY,
296 },
297 [CGT_MDCR_TPM] = {
298 .index = MDCR_EL2,
299 .value = MDCR_EL2_TPM,
300 .mask = MDCR_EL2_TPM,
301 .behaviour = BEHAVE_FORWARD_ANY,
302 },
303 [CGT_MDCR_TDE] = {
304 .index = MDCR_EL2,
305 .value = MDCR_EL2_TDE,
306 .mask = MDCR_EL2_TDE,
307 .behaviour = BEHAVE_FORWARD_ANY,
308 },
309 [CGT_MDCR_TDA] = {
310 .index = MDCR_EL2,
311 .value = MDCR_EL2_TDA,
312 .mask = MDCR_EL2_TDA,
313 .behaviour = BEHAVE_FORWARD_ANY,
314 },
315 [CGT_MDCR_TDOSA] = {
316 .index = MDCR_EL2,
317 .value = MDCR_EL2_TDOSA,
318 .mask = MDCR_EL2_TDOSA,
319 .behaviour = BEHAVE_FORWARD_ANY,
320 },
321 [CGT_MDCR_TDRA] = {
322 .index = MDCR_EL2,
323 .value = MDCR_EL2_TDRA,
324 .mask = MDCR_EL2_TDRA,
325 .behaviour = BEHAVE_FORWARD_ANY,
326 },
327 [CGT_MDCR_E2PB] = {
328 .index = MDCR_EL2,
329 .value = 0,
330 .mask = BIT(MDCR_EL2_E2PB_SHIFT),
331 .behaviour = BEHAVE_FORWARD_ANY,
332 },
333 [CGT_MDCR_TPMS] = {
334 .index = MDCR_EL2,
335 .value = MDCR_EL2_TPMS,
336 .mask = MDCR_EL2_TPMS,
337 .behaviour = BEHAVE_FORWARD_ANY,
338 },
339 [CGT_MDCR_TTRF] = {
340 .index = MDCR_EL2,
341 .value = MDCR_EL2_TTRF,
342 .mask = MDCR_EL2_TTRF,
343 .behaviour = BEHAVE_FORWARD_ANY,
344 },
345 [CGT_MDCR_E2TB] = {
346 .index = MDCR_EL2,
347 .value = 0,
348 .mask = BIT(MDCR_EL2_E2TB_SHIFT),
349 .behaviour = BEHAVE_FORWARD_ANY,
350 },
351 [CGT_MDCR_TDCC] = {
352 .index = MDCR_EL2,
353 .value = MDCR_EL2_TDCC,
354 .mask = MDCR_EL2_TDCC,
355 .behaviour = BEHAVE_FORWARD_ANY,
356 },
357 [CGT_CPACR_E0POE] = {
358 .index = CPTR_EL2,
359 .value = CPACR_ELx_E0POE,
360 .mask = CPACR_ELx_E0POE,
361 .behaviour = BEHAVE_FORWARD_ANY,
362 },
363 [CGT_CPTR_TAM] = {
364 .index = CPTR_EL2,
365 .value = CPTR_EL2_TAM,
366 .mask = CPTR_EL2_TAM,
367 .behaviour = BEHAVE_FORWARD_ANY,
368 },
369 [CGT_CPTR_TCPAC] = {
370 .index = CPTR_EL2,
371 .value = CPTR_EL2_TCPAC,
372 .mask = CPTR_EL2_TCPAC,
373 .behaviour = BEHAVE_FORWARD_ANY,
374 },
375 [CGT_HCRX_TCR2En] = {
376 .index = HCRX_EL2,
377 .value = 0,
378 .mask = HCRX_EL2_TCR2En,
379 .behaviour = BEHAVE_FORWARD_ANY,
380 },
381 };
382
383 #define MCB(id, ...) \
384 [id - __MULTIPLE_CONTROL_BITS__] = \
385 (const enum cgt_group_id[]){ \
386 __VA_ARGS__, __RESERVED__ \
387 }
388
389 static const enum cgt_group_id *coarse_control_combo[] = {
390 MCB(CGT_HCR_IMO_FMO, CGT_HCR_IMO, CGT_HCR_FMO),
391 MCB(CGT_HCR_TID2_TID4, CGT_HCR_TID2, CGT_HCR_TID4),
392 MCB(CGT_HCR_TTLB_TTLBIS, CGT_HCR_TTLB, CGT_HCR_TTLBIS),
393 MCB(CGT_HCR_TTLB_TTLBOS, CGT_HCR_TTLB, CGT_HCR_TTLBOS),
394 MCB(CGT_HCR_TVM_TRVM, CGT_HCR_TVM, CGT_HCR_TRVM),
395 MCB(CGT_HCR_TVM_TRVM_HCRX_TCR2En,
396 CGT_HCR_TVM, CGT_HCR_TRVM, CGT_HCRX_TCR2En),
397 MCB(CGT_HCR_TPU_TICAB, CGT_HCR_TPU, CGT_HCR_TICAB),
398 MCB(CGT_HCR_TPU_TOCU, CGT_HCR_TPU, CGT_HCR_TOCU),
399 MCB(CGT_HCR_NV1_nNV2_ENSCXT, CGT_HCR_NV1_nNV2, CGT_HCR_ENSCXT),
400 MCB(CGT_MDCR_TPM_TPMCR, CGT_MDCR_TPM, CGT_MDCR_TPMCR),
401 MCB(CGT_MDCR_TDE_TDA, CGT_MDCR_TDE, CGT_MDCR_TDA),
402 MCB(CGT_MDCR_TDE_TDOSA, CGT_MDCR_TDE, CGT_MDCR_TDOSA),
403 MCB(CGT_MDCR_TDE_TDRA, CGT_MDCR_TDE, CGT_MDCR_TDRA),
404 MCB(CGT_MDCR_TDCC_TDE_TDA, CGT_MDCR_TDCC, CGT_MDCR_TDE, CGT_MDCR_TDA),
405 };
406
407 typedef enum trap_behaviour (*complex_condition_check)(struct kvm_vcpu *);
408
409 /*
410 * Warning, maximum confusion ahead.
411 *
412 * When E2H=0, CNTHCTL_EL2[1:0] are defined as EL1PCEN:EL1PCTEN
413 * When E2H=1, CNTHCTL_EL2[11:10] are defined as EL1PTEN:EL1PCTEN
414 *
415 * Note the single letter difference? Yet, the bits have the same
416 * function despite a different layout and a different name.
417 *
418 * We don't try to reconcile this mess. We just use the E2H=0 bits
419 * to generate something that is in the E2H=1 format, and live with
420 * it. You're welcome.
421 */
422 static u64 get_sanitized_cnthctl(struct kvm_vcpu *vcpu)
423 {
424 u64 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
425
426 if (!vcpu_el2_e2h_is_set(vcpu))
427 val = (val & (CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN)) << 10;
428
429 return val & ((CNTHCTL_EL1PCEN | CNTHCTL_EL1PCTEN) << 10);
430 }
431
432 static enum trap_behaviour check_cnthctl_el1pcten(struct kvm_vcpu *vcpu)
433 {
434 if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCTEN << 10))
435 return BEHAVE_HANDLE_LOCALLY;
436
437 return BEHAVE_FORWARD_ANY;
438 }
439
440 static enum trap_behaviour check_cnthctl_el1pten(struct kvm_vcpu *vcpu)
441 {
442 if (get_sanitized_cnthctl(vcpu) & (CNTHCTL_EL1PCEN << 10))
443 return BEHAVE_HANDLE_LOCALLY;
444
445 return BEHAVE_FORWARD_ANY;
446 }
447
448 static enum trap_behaviour check_cptr_tta(struct kvm_vcpu *vcpu)
449 {
450 u64 val = __vcpu_sys_reg(vcpu, CPTR_EL2);
451
452 if (!vcpu_el2_e2h_is_set(vcpu))
453 val = translate_cptr_el2_to_cpacr_el1(val);
454
455 if (val & CPACR_ELx_TTA)
456 return BEHAVE_FORWARD_ANY;
457
458 return BEHAVE_HANDLE_LOCALLY;
459 }
460
461 #define CCC(id, fn) \
462 [id - __COMPLEX_CONDITIONS__] = fn
463
464 static const complex_condition_check ccc[] = {
465 CCC(CGT_CNTHCTL_EL1PCTEN, check_cnthctl_el1pcten),
466 CCC(CGT_CNTHCTL_EL1PTEN, check_cnthctl_el1pten),
467 CCC(CGT_CPTR_TTA, check_cptr_tta),
468 };
469
470 /*
471 * Bit assignment for the trap controls. We use a 64bit word with the
472 * following layout for each trapped sysreg:
473 *
474 * [9:0] enum cgt_group_id (10 bits)
475 * [13:10] enum fgt_group_id (4 bits)
476 * [19:14] bit number in the FGT register (6 bits)
477 * [20] trap polarity (1 bit)
478 * [25:21] FG filter (5 bits)
479 * [35:26] Main SysReg table index (10 bits)
480 * [62:36] Unused (27 bits)
481 * [63] RES0 - Must be zero, as lost on insertion in the xarray
482 */
483 #define TC_CGT_BITS 10
484 #define TC_FGT_BITS 4
485 #define TC_FGF_BITS 5
486 #define TC_SRI_BITS 10
487
488 union trap_config {
489 u64 val;
490 struct {
491 unsigned long cgt:TC_CGT_BITS; /* Coarse Grained Trap id */
492 unsigned long fgt:TC_FGT_BITS; /* Fine Grained Trap id */
493 unsigned long bit:6; /* Bit number */
494 unsigned long pol:1; /* Polarity */
495 unsigned long fgf:TC_FGF_BITS; /* Fine Grained Filter */
496 unsigned long sri:TC_SRI_BITS; /* SysReg Index */
497 unsigned long unused:27; /* Unused, should be zero */
498 unsigned long mbz:1; /* Must Be Zero */
499 };
500 };
501
502 struct encoding_to_trap_config {
503 const u32 encoding;
504 const u32 end;
505 const union trap_config tc;
506 const unsigned int line;
507 };
508
509 #define SR_RANGE_TRAP(sr_start, sr_end, trap_id) \
510 { \
511 .encoding = sr_start, \
512 .end = sr_end, \
513 .tc = { \
514 .cgt = trap_id, \
515 }, \
516 .line = __LINE__, \
517 }
518
519 #define SR_TRAP(sr, trap_id) SR_RANGE_TRAP(sr, sr, trap_id)
520
521 /*
522 * Map encoding to trap bits for exception reported with EC=0x18.
523 * These must only be evaluated when running a nested hypervisor, but
524 * that the current context is not a hypervisor context. When the
525 * trapped access matches one of the trap controls, the exception is
526 * re-injected in the nested hypervisor.
527 */
528 static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
529 SR_TRAP(SYS_REVIDR_EL1, CGT_HCR_TID1),
530 SR_TRAP(SYS_AIDR_EL1, CGT_HCR_TID1),
531 SR_TRAP(SYS_SMIDR_EL1, CGT_HCR_TID1),
532 SR_TRAP(SYS_CTR_EL0, CGT_HCR_TID2),
533 SR_TRAP(SYS_CCSIDR_EL1, CGT_HCR_TID2_TID4),
534 SR_TRAP(SYS_CCSIDR2_EL1, CGT_HCR_TID2_TID4),
535 SR_TRAP(SYS_CLIDR_EL1, CGT_HCR_TID2_TID4),
536 SR_TRAP(SYS_CSSELR_EL1, CGT_HCR_TID2_TID4),
537 SR_RANGE_TRAP(SYS_ID_PFR0_EL1,
538 sys_reg(3, 0, 0, 7, 7), CGT_HCR_TID3),
539 SR_TRAP(SYS_ICC_SGI0R_EL1, CGT_HCR_IMO_FMO),
540 SR_TRAP(SYS_ICC_ASGI1R_EL1, CGT_HCR_IMO_FMO),
541 SR_TRAP(SYS_ICC_SGI1R_EL1, CGT_HCR_IMO_FMO),
542 SR_RANGE_TRAP(sys_reg(3, 0, 11, 0, 0),
543 sys_reg(3, 0, 11, 15, 7), CGT_HCR_TIDCP),
544 SR_RANGE_TRAP(sys_reg(3, 1, 11, 0, 0),
545 sys_reg(3, 1, 11, 15, 7), CGT_HCR_TIDCP),
546 SR_RANGE_TRAP(sys_reg(3, 2, 11, 0, 0),
547 sys_reg(3, 2, 11, 15, 7), CGT_HCR_TIDCP),
548 SR_RANGE_TRAP(sys_reg(3, 3, 11, 0, 0),
549 sys_reg(3, 3, 11, 15, 7), CGT_HCR_TIDCP),
550 SR_RANGE_TRAP(sys_reg(3, 4, 11, 0, 0),
551 sys_reg(3, 4, 11, 15, 7), CGT_HCR_TIDCP),
552 SR_RANGE_TRAP(sys_reg(3, 5, 11, 0, 0),
553 sys_reg(3, 5, 11, 15, 7), CGT_HCR_TIDCP),
554 SR_RANGE_TRAP(sys_reg(3, 6, 11, 0, 0),
555 sys_reg(3, 6, 11, 15, 7), CGT_HCR_TIDCP),
556 SR_RANGE_TRAP(sys_reg(3, 7, 11, 0, 0),
557 sys_reg(3, 7, 11, 15, 7), CGT_HCR_TIDCP),
558 SR_RANGE_TRAP(sys_reg(3, 0, 15, 0, 0),
559 sys_reg(3, 0, 15, 15, 7), CGT_HCR_TIDCP),
560 SR_RANGE_TRAP(sys_reg(3, 1, 15, 0, 0),
561 sys_reg(3, 1, 15, 15, 7), CGT_HCR_TIDCP),
562 SR_RANGE_TRAP(sys_reg(3, 2, 15, 0, 0),
563 sys_reg(3, 2, 15, 15, 7), CGT_HCR_TIDCP),
564 SR_RANGE_TRAP(sys_reg(3, 3, 15, 0, 0),
565 sys_reg(3, 3, 15, 15, 7), CGT_HCR_TIDCP),
566 SR_RANGE_TRAP(sys_reg(3, 4, 15, 0, 0),
567 sys_reg(3, 4, 15, 15, 7), CGT_HCR_TIDCP),
568 SR_RANGE_TRAP(sys_reg(3, 5, 15, 0, 0),
569 sys_reg(3, 5, 15, 15, 7), CGT_HCR_TIDCP),
570 SR_RANGE_TRAP(sys_reg(3, 6, 15, 0, 0),
571 sys_reg(3, 6, 15, 15, 7), CGT_HCR_TIDCP),
572 SR_RANGE_TRAP(sys_reg(3, 7, 15, 0, 0),
573 sys_reg(3, 7, 15, 15, 7), CGT_HCR_TIDCP),
574 SR_TRAP(SYS_ACTLR_EL1, CGT_HCR_TACR),
575 SR_TRAP(SYS_DC_ISW, CGT_HCR_TSW),
576 SR_TRAP(SYS_DC_CSW, CGT_HCR_TSW),
577 SR_TRAP(SYS_DC_CISW, CGT_HCR_TSW),
578 SR_TRAP(SYS_DC_IGSW, CGT_HCR_TSW),
579 SR_TRAP(SYS_DC_IGDSW, CGT_HCR_TSW),
580 SR_TRAP(SYS_DC_CGSW, CGT_HCR_TSW),
581 SR_TRAP(SYS_DC_CGDSW, CGT_HCR_TSW),
582 SR_TRAP(SYS_DC_CIGSW, CGT_HCR_TSW),
583 SR_TRAP(SYS_DC_CIGDSW, CGT_HCR_TSW),
584 SR_TRAP(SYS_DC_CIVAC, CGT_HCR_TPC),
585 SR_TRAP(SYS_DC_CVAC, CGT_HCR_TPC),
586 SR_TRAP(SYS_DC_CVAP, CGT_HCR_TPC),
587 SR_TRAP(SYS_DC_CVADP, CGT_HCR_TPC),
588 SR_TRAP(SYS_DC_IVAC, CGT_HCR_TPC),
589 SR_TRAP(SYS_DC_CIGVAC, CGT_HCR_TPC),
590 SR_TRAP(SYS_DC_CIGDVAC, CGT_HCR_TPC),
591 SR_TRAP(SYS_DC_IGVAC, CGT_HCR_TPC),
592 SR_TRAP(SYS_DC_IGDVAC, CGT_HCR_TPC),
593 SR_TRAP(SYS_DC_CGVAC, CGT_HCR_TPC),
594 SR_TRAP(SYS_DC_CGDVAC, CGT_HCR_TPC),
595 SR_TRAP(SYS_DC_CGVAP, CGT_HCR_TPC),
596 SR_TRAP(SYS_DC_CGDVAP, CGT_HCR_TPC),
597 SR_TRAP(SYS_DC_CGVADP, CGT_HCR_TPC),
598 SR_TRAP(SYS_DC_CGDVADP, CGT_HCR_TPC),
599 SR_TRAP(SYS_IC_IVAU, CGT_HCR_TPU_TOCU),
600 SR_TRAP(SYS_IC_IALLU, CGT_HCR_TPU_TOCU),
601 SR_TRAP(SYS_IC_IALLUIS, CGT_HCR_TPU_TICAB),
602 SR_TRAP(SYS_DC_CVAU, CGT_HCR_TPU_TOCU),
603 SR_TRAP(OP_TLBI_RVAE1, CGT_HCR_TTLB),
604 SR_TRAP(OP_TLBI_RVAAE1, CGT_HCR_TTLB),
605 SR_TRAP(OP_TLBI_RVALE1, CGT_HCR_TTLB),
606 SR_TRAP(OP_TLBI_RVAALE1, CGT_HCR_TTLB),
607 SR_TRAP(OP_TLBI_VMALLE1, CGT_HCR_TTLB),
608 SR_TRAP(OP_TLBI_VAE1, CGT_HCR_TTLB),
609 SR_TRAP(OP_TLBI_ASIDE1, CGT_HCR_TTLB),
610 SR_TRAP(OP_TLBI_VAAE1, CGT_HCR_TTLB),
611 SR_TRAP(OP_TLBI_VALE1, CGT_HCR_TTLB),
612 SR_TRAP(OP_TLBI_VAALE1, CGT_HCR_TTLB),
613 SR_TRAP(OP_TLBI_RVAE1NXS, CGT_HCR_TTLB),
614 SR_TRAP(OP_TLBI_RVAAE1NXS, CGT_HCR_TTLB),
615 SR_TRAP(OP_TLBI_RVALE1NXS, CGT_HCR_TTLB),
616 SR_TRAP(OP_TLBI_RVAALE1NXS, CGT_HCR_TTLB),
617 SR_TRAP(OP_TLBI_VMALLE1NXS, CGT_HCR_TTLB),
618 SR_TRAP(OP_TLBI_VAE1NXS, CGT_HCR_TTLB),
619 SR_TRAP(OP_TLBI_ASIDE1NXS, CGT_HCR_TTLB),
620 SR_TRAP(OP_TLBI_VAAE1NXS, CGT_HCR_TTLB),
621 SR_TRAP(OP_TLBI_VALE1NXS, CGT_HCR_TTLB),
622 SR_TRAP(OP_TLBI_VAALE1NXS, CGT_HCR_TTLB),
623 SR_TRAP(OP_TLBI_RVAE1IS, CGT_HCR_TTLB_TTLBIS),
624 SR_TRAP(OP_TLBI_RVAAE1IS, CGT_HCR_TTLB_TTLBIS),
625 SR_TRAP(OP_TLBI_RVALE1IS, CGT_HCR_TTLB_TTLBIS),
626 SR_TRAP(OP_TLBI_RVAALE1IS, CGT_HCR_TTLB_TTLBIS),
627 SR_TRAP(OP_TLBI_VMALLE1IS, CGT_HCR_TTLB_TTLBIS),
628 SR_TRAP(OP_TLBI_VAE1IS, CGT_HCR_TTLB_TTLBIS),
629 SR_TRAP(OP_TLBI_ASIDE1IS, CGT_HCR_TTLB_TTLBIS),
630 SR_TRAP(OP_TLBI_VAAE1IS, CGT_HCR_TTLB_TTLBIS),
631 SR_TRAP(OP_TLBI_VALE1IS, CGT_HCR_TTLB_TTLBIS),
632 SR_TRAP(OP_TLBI_VAALE1IS, CGT_HCR_TTLB_TTLBIS),
633 SR_TRAP(OP_TLBI_RVAE1ISNXS, CGT_HCR_TTLB_TTLBIS),
634 SR_TRAP(OP_TLBI_RVAAE1ISNXS, CGT_HCR_TTLB_TTLBIS),
635 SR_TRAP(OP_TLBI_RVALE1ISNXS, CGT_HCR_TTLB_TTLBIS),
636 SR_TRAP(OP_TLBI_RVAALE1ISNXS, CGT_HCR_TTLB_TTLBIS),
637 SR_TRAP(OP_TLBI_VMALLE1ISNXS, CGT_HCR_TTLB_TTLBIS),
638 SR_TRAP(OP_TLBI_VAE1ISNXS, CGT_HCR_TTLB_TTLBIS),
639 SR_TRAP(OP_TLBI_ASIDE1ISNXS, CGT_HCR_TTLB_TTLBIS),
640 SR_TRAP(OP_TLBI_VAAE1ISNXS, CGT_HCR_TTLB_TTLBIS),
641 SR_TRAP(OP_TLBI_VALE1ISNXS, CGT_HCR_TTLB_TTLBIS),
642 SR_TRAP(OP_TLBI_VAALE1ISNXS, CGT_HCR_TTLB_TTLBIS),
643 SR_TRAP(OP_TLBI_VMALLE1OS, CGT_HCR_TTLB_TTLBOS),
644 SR_TRAP(OP_TLBI_VAE1OS, CGT_HCR_TTLB_TTLBOS),
645 SR_TRAP(OP_TLBI_ASIDE1OS, CGT_HCR_TTLB_TTLBOS),
646 SR_TRAP(OP_TLBI_VAAE1OS, CGT_HCR_TTLB_TTLBOS),
647 SR_TRAP(OP_TLBI_VALE1OS, CGT_HCR_TTLB_TTLBOS),
648 SR_TRAP(OP_TLBI_VAALE1OS, CGT_HCR_TTLB_TTLBOS),
649 SR_TRAP(OP_TLBI_RVAE1OS, CGT_HCR_TTLB_TTLBOS),
650 SR_TRAP(OP_TLBI_RVAAE1OS, CGT_HCR_TTLB_TTLBOS),
651 SR_TRAP(OP_TLBI_RVALE1OS, CGT_HCR_TTLB_TTLBOS),
652 SR_TRAP(OP_TLBI_RVAALE1OS, CGT_HCR_TTLB_TTLBOS),
653 SR_TRAP(OP_TLBI_VMALLE1OSNXS, CGT_HCR_TTLB_TTLBOS),
654 SR_TRAP(OP_TLBI_VAE1OSNXS, CGT_HCR_TTLB_TTLBOS),
655 SR_TRAP(OP_TLBI_ASIDE1OSNXS, CGT_HCR_TTLB_TTLBOS),
656 SR_TRAP(OP_TLBI_VAAE1OSNXS, CGT_HCR_TTLB_TTLBOS),
657 SR_TRAP(OP_TLBI_VALE1OSNXS, CGT_HCR_TTLB_TTLBOS),
658 SR_TRAP(OP_TLBI_VAALE1OSNXS, CGT_HCR_TTLB_TTLBOS),
659 SR_TRAP(OP_TLBI_RVAE1OSNXS, CGT_HCR_TTLB_TTLBOS),
660 SR_TRAP(OP_TLBI_RVAAE1OSNXS, CGT_HCR_TTLB_TTLBOS),
661 SR_TRAP(OP_TLBI_RVALE1OSNXS, CGT_HCR_TTLB_TTLBOS),
662 SR_TRAP(OP_TLBI_RVAALE1OSNXS, CGT_HCR_TTLB_TTLBOS),
663 SR_TRAP(SYS_SCTLR_EL1, CGT_HCR_TVM_TRVM),
664 SR_TRAP(SYS_TTBR0_EL1, CGT_HCR_TVM_TRVM),
665 SR_TRAP(SYS_TTBR1_EL1, CGT_HCR_TVM_TRVM),
666 SR_TRAP(SYS_TCR_EL1, CGT_HCR_TVM_TRVM),
667 SR_TRAP(SYS_ESR_EL1, CGT_HCR_TVM_TRVM),
668 SR_TRAP(SYS_FAR_EL1, CGT_HCR_TVM_TRVM),
669 SR_TRAP(SYS_AFSR0_EL1, CGT_HCR_TVM_TRVM),
670 SR_TRAP(SYS_AFSR1_EL1, CGT_HCR_TVM_TRVM),
671 SR_TRAP(SYS_MAIR_EL1, CGT_HCR_TVM_TRVM),
672 SR_TRAP(SYS_AMAIR_EL1, CGT_HCR_TVM_TRVM),
673 SR_TRAP(SYS_CONTEXTIDR_EL1, CGT_HCR_TVM_TRVM),
674 SR_TRAP(SYS_TCR2_EL1, CGT_HCR_TVM_TRVM_HCRX_TCR2En),
675 SR_TRAP(SYS_DC_ZVA, CGT_HCR_TDZ),
676 SR_TRAP(SYS_DC_GVA, CGT_HCR_TDZ),
677 SR_TRAP(SYS_DC_GZVA, CGT_HCR_TDZ),
678 SR_TRAP(SYS_LORSA_EL1, CGT_HCR_TLOR),
679 SR_TRAP(SYS_LOREA_EL1, CGT_HCR_TLOR),
680 SR_TRAP(SYS_LORN_EL1, CGT_HCR_TLOR),
681 SR_TRAP(SYS_LORC_EL1, CGT_HCR_TLOR),
682 SR_TRAP(SYS_LORID_EL1, CGT_HCR_TLOR),
683 SR_TRAP(SYS_ERRIDR_EL1, CGT_HCR_TERR),
684 SR_TRAP(SYS_ERRSELR_EL1, CGT_HCR_TERR),
685 SR_TRAP(SYS_ERXADDR_EL1, CGT_HCR_TERR),
686 SR_TRAP(SYS_ERXCTLR_EL1, CGT_HCR_TERR),
687 SR_TRAP(SYS_ERXFR_EL1, CGT_HCR_TERR),
688 SR_TRAP(SYS_ERXMISC0_EL1, CGT_HCR_TERR),
689 SR_TRAP(SYS_ERXMISC1_EL1, CGT_HCR_TERR),
690 SR_TRAP(SYS_ERXMISC2_EL1, CGT_HCR_TERR),
691 SR_TRAP(SYS_ERXMISC3_EL1, CGT_HCR_TERR),
692 SR_TRAP(SYS_ERXSTATUS_EL1, CGT_HCR_TERR),
693 SR_TRAP(SYS_APIAKEYLO_EL1, CGT_HCR_APK),
694 SR_TRAP(SYS_APIAKEYHI_EL1, CGT_HCR_APK),
695 SR_TRAP(SYS_APIBKEYLO_EL1, CGT_HCR_APK),
696 SR_TRAP(SYS_APIBKEYHI_EL1, CGT_HCR_APK),
697 SR_TRAP(SYS_APDAKEYLO_EL1, CGT_HCR_APK),
698 SR_TRAP(SYS_APDAKEYHI_EL1, CGT_HCR_APK),
699 SR_TRAP(SYS_APDBKEYLO_EL1, CGT_HCR_APK),
700 SR_TRAP(SYS_APDBKEYHI_EL1, CGT_HCR_APK),
701 SR_TRAP(SYS_APGAKEYLO_EL1, CGT_HCR_APK),
702 SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK),
703 /* All _EL2 registers */
704 SR_TRAP(SYS_BRBCR_EL2, CGT_HCR_NV),
705 SR_TRAP(SYS_VPIDR_EL2, CGT_HCR_NV),
706 SR_TRAP(SYS_VMPIDR_EL2, CGT_HCR_NV),
707 SR_TRAP(SYS_SCTLR_EL2, CGT_HCR_NV),
708 SR_TRAP(SYS_ACTLR_EL2, CGT_HCR_NV),
709 SR_TRAP(SYS_SCTLR2_EL2, CGT_HCR_NV),
710 SR_RANGE_TRAP(SYS_HCR_EL2,
711 SYS_HCRX_EL2, CGT_HCR_NV),
712 SR_TRAP(SYS_SMPRIMAP_EL2, CGT_HCR_NV),
713 SR_TRAP(SYS_SMCR_EL2, CGT_HCR_NV),
714 SR_RANGE_TRAP(SYS_TTBR0_EL2,
715 SYS_TCR2_EL2, CGT_HCR_NV),
716 SR_TRAP(SYS_VTTBR_EL2, CGT_HCR_NV),
717 SR_TRAP(SYS_VTCR_EL2, CGT_HCR_NV),
718 SR_TRAP(SYS_VNCR_EL2, CGT_HCR_NV),
719 SR_RANGE_TRAP(SYS_HDFGRTR_EL2,
720 SYS_HAFGRTR_EL2, CGT_HCR_NV),
721 /* Skip the SP_EL1 encoding... */
722 SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV),
723 SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV),
724 /* Skip SPSR_irq, SPSR_abt, SPSR_und, SPSR_fiq */
725 SR_TRAP(SYS_AFSR0_EL2, CGT_HCR_NV),
726 SR_TRAP(SYS_AFSR1_EL2, CGT_HCR_NV),
727 SR_TRAP(SYS_ESR_EL2, CGT_HCR_NV),
728 SR_TRAP(SYS_VSESR_EL2, CGT_HCR_NV),
729 SR_TRAP(SYS_TFSR_EL2, CGT_HCR_NV),
730 SR_TRAP(SYS_FAR_EL2, CGT_HCR_NV),
731 SR_TRAP(SYS_HPFAR_EL2, CGT_HCR_NV),
732 SR_TRAP(SYS_PMSCR_EL2, CGT_HCR_NV),
733 SR_TRAP(SYS_MAIR_EL2, CGT_HCR_NV),
734 SR_TRAP(SYS_AMAIR_EL2, CGT_HCR_NV),
735 SR_TRAP(SYS_MPAMHCR_EL2, CGT_HCR_NV),
736 SR_TRAP(SYS_MPAMVPMV_EL2, CGT_HCR_NV),
737 SR_TRAP(SYS_MPAM2_EL2, CGT_HCR_NV),
738 SR_RANGE_TRAP(SYS_MPAMVPM0_EL2,
739 SYS_MPAMVPM7_EL2, CGT_HCR_NV),
740 /*
741 * Note that the spec. describes a group of MEC registers
742 * whose access should not trap, therefore skip the following:
743 * MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2,
744 * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2,
745 * VMECID_P_EL2.
746 */
747 SR_RANGE_TRAP(SYS_VBAR_EL2,
748 SYS_RMR_EL2, CGT_HCR_NV),
749 SR_TRAP(SYS_VDISR_EL2, CGT_HCR_NV),
750 /* ICH_AP0R<m>_EL2 */
751 SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2,
752 SYS_ICH_AP0R3_EL2, CGT_HCR_NV),
753 /* ICH_AP1R<m>_EL2 */
754 SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2,
755 SYS_ICH_AP1R3_EL2, CGT_HCR_NV),
756 SR_TRAP(SYS_ICC_SRE_EL2, CGT_HCR_NV),
757 SR_RANGE_TRAP(SYS_ICH_HCR_EL2,
758 SYS_ICH_EISR_EL2, CGT_HCR_NV),
759 SR_TRAP(SYS_ICH_ELRSR_EL2, CGT_HCR_NV),
760 SR_TRAP(SYS_ICH_VMCR_EL2, CGT_HCR_NV),
761 /* ICH_LR<m>_EL2 */
762 SR_RANGE_TRAP(SYS_ICH_LR0_EL2,
763 SYS_ICH_LR15_EL2, CGT_HCR_NV),
764 SR_TRAP(SYS_CONTEXTIDR_EL2, CGT_HCR_NV),
765 SR_TRAP(SYS_TPIDR_EL2, CGT_HCR_NV),
766 SR_TRAP(SYS_SCXTNUM_EL2, CGT_HCR_NV),
767 /* AMEVCNTVOFF0<n>_EL2, AMEVCNTVOFF1<n>_EL2 */
768 SR_RANGE_TRAP(SYS_AMEVCNTVOFF0n_EL2(0),
769 SYS_AMEVCNTVOFF1n_EL2(15), CGT_HCR_NV),
770 /* CNT*_EL2 */
771 SR_TRAP(SYS_CNTVOFF_EL2, CGT_HCR_NV),
772 SR_TRAP(SYS_CNTPOFF_EL2, CGT_HCR_NV),
773 SR_TRAP(SYS_CNTHCTL_EL2, CGT_HCR_NV),
774 SR_RANGE_TRAP(SYS_CNTHP_TVAL_EL2,
775 SYS_CNTHP_CVAL_EL2, CGT_HCR_NV),
776 SR_RANGE_TRAP(SYS_CNTHV_TVAL_EL2,
777 SYS_CNTHV_CVAL_EL2, CGT_HCR_NV),
778 /* All _EL02, _EL12 registers */
779 SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
780 sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),
781 SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0),
782 sys_reg(3, 5, 14, 15, 7), CGT_HCR_NV),
783 SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV),
784 SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV),
785 SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV),
786 SR_TRAP(OP_AT_S12E1W, CGT_HCR_NV),
787 SR_TRAP(OP_AT_S12E0R, CGT_HCR_NV),
788 SR_TRAP(OP_AT_S12E0W, CGT_HCR_NV),
789 SR_TRAP(OP_TLBI_IPAS2E1, CGT_HCR_NV),
790 SR_TRAP(OP_TLBI_RIPAS2E1, CGT_HCR_NV),
791 SR_TRAP(OP_TLBI_IPAS2LE1, CGT_HCR_NV),
792 SR_TRAP(OP_TLBI_RIPAS2LE1, CGT_HCR_NV),
793 SR_TRAP(OP_TLBI_RVAE2, CGT_HCR_NV),
794 SR_TRAP(OP_TLBI_RVALE2, CGT_HCR_NV),
795 SR_TRAP(OP_TLBI_ALLE2, CGT_HCR_NV),
796 SR_TRAP(OP_TLBI_VAE2, CGT_HCR_NV),
797 SR_TRAP(OP_TLBI_ALLE1, CGT_HCR_NV),
798 SR_TRAP(OP_TLBI_VALE2, CGT_HCR_NV),
799 SR_TRAP(OP_TLBI_VMALLS12E1, CGT_HCR_NV),
800 SR_TRAP(OP_TLBI_IPAS2E1NXS, CGT_HCR_NV),
801 SR_TRAP(OP_TLBI_RIPAS2E1NXS, CGT_HCR_NV),
802 SR_TRAP(OP_TLBI_IPAS2LE1NXS, CGT_HCR_NV),
803 SR_TRAP(OP_TLBI_RIPAS2LE1NXS, CGT_HCR_NV),
804 SR_TRAP(OP_TLBI_RVAE2NXS, CGT_HCR_NV),
805 SR_TRAP(OP_TLBI_RVALE2NXS, CGT_HCR_NV),
806 SR_TRAP(OP_TLBI_ALLE2NXS, CGT_HCR_NV),
807 SR_TRAP(OP_TLBI_VAE2NXS, CGT_HCR_NV),
808 SR_TRAP(OP_TLBI_ALLE1NXS, CGT_HCR_NV),
809 SR_TRAP(OP_TLBI_VALE2NXS, CGT_HCR_NV),
810 SR_TRAP(OP_TLBI_VMALLS12E1NXS, CGT_HCR_NV),
811 SR_TRAP(OP_TLBI_IPAS2E1IS, CGT_HCR_NV),
812 SR_TRAP(OP_TLBI_RIPAS2E1IS, CGT_HCR_NV),
813 SR_TRAP(OP_TLBI_IPAS2LE1IS, CGT_HCR_NV),
814 SR_TRAP(OP_TLBI_RIPAS2LE1IS, CGT_HCR_NV),
815 SR_TRAP(OP_TLBI_RVAE2IS, CGT_HCR_NV),
816 SR_TRAP(OP_TLBI_RVALE2IS, CGT_HCR_NV),
817 SR_TRAP(OP_TLBI_ALLE2IS, CGT_HCR_NV),
818 SR_TRAP(OP_TLBI_VAE2IS, CGT_HCR_NV),
819 SR_TRAP(OP_TLBI_ALLE1IS, CGT_HCR_NV),
820 SR_TRAP(OP_TLBI_VALE2IS, CGT_HCR_NV),
821 SR_TRAP(OP_TLBI_VMALLS12E1IS, CGT_HCR_NV),
822 SR_TRAP(OP_TLBI_IPAS2E1ISNXS, CGT_HCR_NV),
823 SR_TRAP(OP_TLBI_RIPAS2E1ISNXS, CGT_HCR_NV),
824 SR_TRAP(OP_TLBI_IPAS2LE1ISNXS, CGT_HCR_NV),
825 SR_TRAP(OP_TLBI_RIPAS2LE1ISNXS, CGT_HCR_NV),
826 SR_TRAP(OP_TLBI_RVAE2ISNXS, CGT_HCR_NV),
827 SR_TRAP(OP_TLBI_RVALE2ISNXS, CGT_HCR_NV),
828 SR_TRAP(OP_TLBI_ALLE2ISNXS, CGT_HCR_NV),
829 SR_TRAP(OP_TLBI_VAE2ISNXS, CGT_HCR_NV),
830 SR_TRAP(OP_TLBI_ALLE1ISNXS, CGT_HCR_NV),
831 SR_TRAP(OP_TLBI_VALE2ISNXS, CGT_HCR_NV),
832 SR_TRAP(OP_TLBI_VMALLS12E1ISNXS,CGT_HCR_NV),
833 SR_TRAP(OP_TLBI_ALLE2OS, CGT_HCR_NV),
834 SR_TRAP(OP_TLBI_VAE2OS, CGT_HCR_NV),
835 SR_TRAP(OP_TLBI_ALLE1OS, CGT_HCR_NV),
836 SR_TRAP(OP_TLBI_VALE2OS, CGT_HCR_NV),
837 SR_TRAP(OP_TLBI_VMALLS12E1OS, CGT_HCR_NV),
838 SR_TRAP(OP_TLBI_IPAS2E1OS, CGT_HCR_NV),
839 SR_TRAP(OP_TLBI_RIPAS2E1OS, CGT_HCR_NV),
840 SR_TRAP(OP_TLBI_IPAS2LE1OS, CGT_HCR_NV),
841 SR_TRAP(OP_TLBI_RIPAS2LE1OS, CGT_HCR_NV),
842 SR_TRAP(OP_TLBI_RVAE2OS, CGT_HCR_NV),
843 SR_TRAP(OP_TLBI_RVALE2OS, CGT_HCR_NV),
844 SR_TRAP(OP_TLBI_ALLE2OSNXS, CGT_HCR_NV),
845 SR_TRAP(OP_TLBI_VAE2OSNXS, CGT_HCR_NV),
846 SR_TRAP(OP_TLBI_ALLE1OSNXS, CGT_HCR_NV),
847 SR_TRAP(OP_TLBI_VALE2OSNXS, CGT_HCR_NV),
848 SR_TRAP(OP_TLBI_VMALLS12E1OSNXS,CGT_HCR_NV),
849 SR_TRAP(OP_TLBI_IPAS2E1OSNXS, CGT_HCR_NV),
850 SR_TRAP(OP_TLBI_RIPAS2E1OSNXS, CGT_HCR_NV),
851 SR_TRAP(OP_TLBI_IPAS2LE1OSNXS, CGT_HCR_NV),
852 SR_TRAP(OP_TLBI_RIPAS2LE1OSNXS, CGT_HCR_NV),
853 SR_TRAP(OP_TLBI_RVAE2OSNXS, CGT_HCR_NV),
854 SR_TRAP(OP_TLBI_RVALE2OSNXS, CGT_HCR_NV),
855 SR_TRAP(OP_CPP_RCTX, CGT_HCR_NV),
856 SR_TRAP(OP_DVP_RCTX, CGT_HCR_NV),
857 SR_TRAP(OP_CFP_RCTX, CGT_HCR_NV),
858 SR_TRAP(SYS_SP_EL1, CGT_HCR_NV_nNV2),
859 SR_TRAP(SYS_VBAR_EL1, CGT_HCR_NV1_nNV2),
860 SR_TRAP(SYS_ELR_EL1, CGT_HCR_NV1_nNV2),
861 SR_TRAP(SYS_SPSR_EL1, CGT_HCR_NV1_nNV2),
862 SR_TRAP(SYS_SCXTNUM_EL1, CGT_HCR_NV1_nNV2_ENSCXT),
863 SR_TRAP(SYS_SCXTNUM_EL0, CGT_HCR_ENSCXT),
864 SR_TRAP(OP_AT_S1E1R, CGT_HCR_AT),
865 SR_TRAP(OP_AT_S1E1W, CGT_HCR_AT),
866 SR_TRAP(OP_AT_S1E0R, CGT_HCR_AT),
867 SR_TRAP(OP_AT_S1E0W, CGT_HCR_AT),
868 SR_TRAP(OP_AT_S1E1RP, CGT_HCR_AT),
869 SR_TRAP(OP_AT_S1E1WP, CGT_HCR_AT),
870 SR_TRAP(SYS_ERXPFGF_EL1, CGT_HCR_nFIEN),
871 SR_TRAP(SYS_ERXPFGCTL_EL1, CGT_HCR_nFIEN),
872 SR_TRAP(SYS_ERXPFGCDN_EL1, CGT_HCR_nFIEN),
873 SR_TRAP(SYS_PMCR_EL0, CGT_MDCR_TPM_TPMCR),
874 SR_TRAP(SYS_PMCNTENSET_EL0, CGT_MDCR_TPM),
875 SR_TRAP(SYS_PMCNTENCLR_EL0, CGT_MDCR_TPM),
876 SR_TRAP(SYS_PMOVSSET_EL0, CGT_MDCR_TPM),
877 SR_TRAP(SYS_PMOVSCLR_EL0, CGT_MDCR_TPM),
878 SR_TRAP(SYS_PMCEID0_EL0, CGT_MDCR_TPM),
879 SR_TRAP(SYS_PMCEID1_EL0, CGT_MDCR_TPM),
880 SR_TRAP(SYS_PMXEVTYPER_EL0, CGT_MDCR_TPM),
881 SR_TRAP(SYS_PMSWINC_EL0, CGT_MDCR_TPM),
882 SR_TRAP(SYS_PMSELR_EL0, CGT_MDCR_TPM),
883 SR_TRAP(SYS_PMXEVCNTR_EL0, CGT_MDCR_TPM),
884 SR_TRAP(SYS_PMCCNTR_EL0, CGT_MDCR_TPM),
885 SR_TRAP(SYS_PMUSERENR_EL0, CGT_MDCR_TPM),
886 SR_TRAP(SYS_PMINTENSET_EL1, CGT_MDCR_TPM),
887 SR_TRAP(SYS_PMINTENCLR_EL1, CGT_MDCR_TPM),
888 SR_TRAP(SYS_PMMIR_EL1, CGT_MDCR_TPM),
889 SR_TRAP(SYS_PMEVCNTRn_EL0(0), CGT_MDCR_TPM),
890 SR_TRAP(SYS_PMEVCNTRn_EL0(1), CGT_MDCR_TPM),
891 SR_TRAP(SYS_PMEVCNTRn_EL0(2), CGT_MDCR_TPM),
892 SR_TRAP(SYS_PMEVCNTRn_EL0(3), CGT_MDCR_TPM),
893 SR_TRAP(SYS_PMEVCNTRn_EL0(4), CGT_MDCR_TPM),
894 SR_TRAP(SYS_PMEVCNTRn_EL0(5), CGT_MDCR_TPM),
895 SR_TRAP(SYS_PMEVCNTRn_EL0(6), CGT_MDCR_TPM),
896 SR_TRAP(SYS_PMEVCNTRn_EL0(7), CGT_MDCR_TPM),
897 SR_TRAP(SYS_PMEVCNTRn_EL0(8), CGT_MDCR_TPM),
898 SR_TRAP(SYS_PMEVCNTRn_EL0(9), CGT_MDCR_TPM),
899 SR_TRAP(SYS_PMEVCNTRn_EL0(10), CGT_MDCR_TPM),
900 SR_TRAP(SYS_PMEVCNTRn_EL0(11), CGT_MDCR_TPM),
901 SR_TRAP(SYS_PMEVCNTRn_EL0(12), CGT_MDCR_TPM),
902 SR_TRAP(SYS_PMEVCNTRn_EL0(13), CGT_MDCR_TPM),
903 SR_TRAP(SYS_PMEVCNTRn_EL0(14), CGT_MDCR_TPM),
904 SR_TRAP(SYS_PMEVCNTRn_EL0(15), CGT_MDCR_TPM),
905 SR_TRAP(SYS_PMEVCNTRn_EL0(16), CGT_MDCR_TPM),
906 SR_TRAP(SYS_PMEVCNTRn_EL0(17), CGT_MDCR_TPM),
907 SR_TRAP(SYS_PMEVCNTRn_EL0(18), CGT_MDCR_TPM),
908 SR_TRAP(SYS_PMEVCNTRn_EL0(19), CGT_MDCR_TPM),
909 SR_TRAP(SYS_PMEVCNTRn_EL0(20), CGT_MDCR_TPM),
910 SR_TRAP(SYS_PMEVCNTRn_EL0(21), CGT_MDCR_TPM),
911 SR_TRAP(SYS_PMEVCNTRn_EL0(22), CGT_MDCR_TPM),
912 SR_TRAP(SYS_PMEVCNTRn_EL0(23), CGT_MDCR_TPM),
913 SR_TRAP(SYS_PMEVCNTRn_EL0(24), CGT_MDCR_TPM),
914 SR_TRAP(SYS_PMEVCNTRn_EL0(25), CGT_MDCR_TPM),
915 SR_TRAP(SYS_PMEVCNTRn_EL0(26), CGT_MDCR_TPM),
916 SR_TRAP(SYS_PMEVCNTRn_EL0(27), CGT_MDCR_TPM),
917 SR_TRAP(SYS_PMEVCNTRn_EL0(28), CGT_MDCR_TPM),
918 SR_TRAP(SYS_PMEVCNTRn_EL0(29), CGT_MDCR_TPM),
919 SR_TRAP(SYS_PMEVCNTRn_EL0(30), CGT_MDCR_TPM),
920 SR_TRAP(SYS_PMEVTYPERn_EL0(0), CGT_MDCR_TPM),
921 SR_TRAP(SYS_PMEVTYPERn_EL0(1), CGT_MDCR_TPM),
922 SR_TRAP(SYS_PMEVTYPERn_EL0(2), CGT_MDCR_TPM),
923 SR_TRAP(SYS_PMEVTYPERn_EL0(3), CGT_MDCR_TPM),
924 SR_TRAP(SYS_PMEVTYPERn_EL0(4), CGT_MDCR_TPM),
925 SR_TRAP(SYS_PMEVTYPERn_EL0(5), CGT_MDCR_TPM),
926 SR_TRAP(SYS_PMEVTYPERn_EL0(6), CGT_MDCR_TPM),
927 SR_TRAP(SYS_PMEVTYPERn_EL0(7), CGT_MDCR_TPM),
928 SR_TRAP(SYS_PMEVTYPERn_EL0(8), CGT_MDCR_TPM),
929 SR_TRAP(SYS_PMEVTYPERn_EL0(9), CGT_MDCR_TPM),
930 SR_TRAP(SYS_PMEVTYPERn_EL0(10), CGT_MDCR_TPM),
931 SR_TRAP(SYS_PMEVTYPERn_EL0(11), CGT_MDCR_TPM),
932 SR_TRAP(SYS_PMEVTYPERn_EL0(12), CGT_MDCR_TPM),
933 SR_TRAP(SYS_PMEVTYPERn_EL0(13), CGT_MDCR_TPM),
934 SR_TRAP(SYS_PMEVTYPERn_EL0(14), CGT_MDCR_TPM),
935 SR_TRAP(SYS_PMEVTYPERn_EL0(15), CGT_MDCR_TPM),
936 SR_TRAP(SYS_PMEVTYPERn_EL0(16), CGT_MDCR_TPM),
937 SR_TRAP(SYS_PMEVTYPERn_EL0(17), CGT_MDCR_TPM),
938 SR_TRAP(SYS_PMEVTYPERn_EL0(18), CGT_MDCR_TPM),
939 SR_TRAP(SYS_PMEVTYPERn_EL0(19), CGT_MDCR_TPM),
940 SR_TRAP(SYS_PMEVTYPERn_EL0(20), CGT_MDCR_TPM),
941 SR_TRAP(SYS_PMEVTYPERn_EL0(21), CGT_MDCR_TPM),
942 SR_TRAP(SYS_PMEVTYPERn_EL0(22), CGT_MDCR_TPM),
943 SR_TRAP(SYS_PMEVTYPERn_EL0(23), CGT_MDCR_TPM),
944 SR_TRAP(SYS_PMEVTYPERn_EL0(24), CGT_MDCR_TPM),
945 SR_TRAP(SYS_PMEVTYPERn_EL0(25), CGT_MDCR_TPM),
946 SR_TRAP(SYS_PMEVTYPERn_EL0(26), CGT_MDCR_TPM),
947 SR_TRAP(SYS_PMEVTYPERn_EL0(27), CGT_MDCR_TPM),
948 SR_TRAP(SYS_PMEVTYPERn_EL0(28), CGT_MDCR_TPM),
949 SR_TRAP(SYS_PMEVTYPERn_EL0(29), CGT_MDCR_TPM),
950 SR_TRAP(SYS_PMEVTYPERn_EL0(30), CGT_MDCR_TPM),
951 SR_TRAP(SYS_PMCCFILTR_EL0, CGT_MDCR_TPM),
952 SR_TRAP(SYS_MDCCSR_EL0, CGT_MDCR_TDCC_TDE_TDA),
953 SR_TRAP(SYS_MDCCINT_EL1, CGT_MDCR_TDCC_TDE_TDA),
954 SR_TRAP(SYS_OSDTRRX_EL1, CGT_MDCR_TDCC_TDE_TDA),
955 SR_TRAP(SYS_OSDTRTX_EL1, CGT_MDCR_TDCC_TDE_TDA),
956 SR_TRAP(SYS_DBGDTR_EL0, CGT_MDCR_TDCC_TDE_TDA),
957 /*
958 * Also covers DBGDTRRX_EL0, which has the same encoding as
959 * SYS_DBGDTRTX_EL0...
960 */
961 SR_TRAP(SYS_DBGDTRTX_EL0, CGT_MDCR_TDCC_TDE_TDA),
962 SR_TRAP(SYS_MDSCR_EL1, CGT_MDCR_TDE_TDA),
963 SR_TRAP(SYS_OSECCR_EL1, CGT_MDCR_TDE_TDA),
964 SR_TRAP(SYS_DBGBVRn_EL1(0), CGT_MDCR_TDE_TDA),
965 SR_TRAP(SYS_DBGBVRn_EL1(1), CGT_MDCR_TDE_TDA),
966 SR_TRAP(SYS_DBGBVRn_EL1(2), CGT_MDCR_TDE_TDA),
967 SR_TRAP(SYS_DBGBVRn_EL1(3), CGT_MDCR_TDE_TDA),
968 SR_TRAP(SYS_DBGBVRn_EL1(4), CGT_MDCR_TDE_TDA),
969 SR_TRAP(SYS_DBGBVRn_EL1(5), CGT_MDCR_TDE_TDA),
970 SR_TRAP(SYS_DBGBVRn_EL1(6), CGT_MDCR_TDE_TDA),
971 SR_TRAP(SYS_DBGBVRn_EL1(7), CGT_MDCR_TDE_TDA),
972 SR_TRAP(SYS_DBGBVRn_EL1(8), CGT_MDCR_TDE_TDA),
973 SR_TRAP(SYS_DBGBVRn_EL1(9), CGT_MDCR_TDE_TDA),
974 SR_TRAP(SYS_DBGBVRn_EL1(10), CGT_MDCR_TDE_TDA),
975 SR_TRAP(SYS_DBGBVRn_EL1(11), CGT_MDCR_TDE_TDA),
976 SR_TRAP(SYS_DBGBVRn_EL1(12), CGT_MDCR_TDE_TDA),
977 SR_TRAP(SYS_DBGBVRn_EL1(13), CGT_MDCR_TDE_TDA),
978 SR_TRAP(SYS_DBGBVRn_EL1(14), CGT_MDCR_TDE_TDA),
979 SR_TRAP(SYS_DBGBVRn_EL1(15), CGT_MDCR_TDE_TDA),
980 SR_TRAP(SYS_DBGBCRn_EL1(0), CGT_MDCR_TDE_TDA),
981 SR_TRAP(SYS_DBGBCRn_EL1(1), CGT_MDCR_TDE_TDA),
982 SR_TRAP(SYS_DBGBCRn_EL1(2), CGT_MDCR_TDE_TDA),
983 SR_TRAP(SYS_DBGBCRn_EL1(3), CGT_MDCR_TDE_TDA),
984 SR_TRAP(SYS_DBGBCRn_EL1(4), CGT_MDCR_TDE_TDA),
985 SR_TRAP(SYS_DBGBCRn_EL1(5), CGT_MDCR_TDE_TDA),
986 SR_TRAP(SYS_DBGBCRn_EL1(6), CGT_MDCR_TDE_TDA),
987 SR_TRAP(SYS_DBGBCRn_EL1(7), CGT_MDCR_TDE_TDA),
988 SR_TRAP(SYS_DBGBCRn_EL1(8), CGT_MDCR_TDE_TDA),
989 SR_TRAP(SYS_DBGBCRn_EL1(9), CGT_MDCR_TDE_TDA),
990 SR_TRAP(SYS_DBGBCRn_EL1(10), CGT_MDCR_TDE_TDA),
991 SR_TRAP(SYS_DBGBCRn_EL1(11), CGT_MDCR_TDE_TDA),
992 SR_TRAP(SYS_DBGBCRn_EL1(12), CGT_MDCR_TDE_TDA),
993 SR_TRAP(SYS_DBGBCRn_EL1(13), CGT_MDCR_TDE_TDA),
994 SR_TRAP(SYS_DBGBCRn_EL1(14), CGT_MDCR_TDE_TDA),
995 SR_TRAP(SYS_DBGBCRn_EL1(15), CGT_MDCR_TDE_TDA),
996 SR_TRAP(SYS_DBGWVRn_EL1(0), CGT_MDCR_TDE_TDA),
997 SR_TRAP(SYS_DBGWVRn_EL1(1), CGT_MDCR_TDE_TDA),
998 SR_TRAP(SYS_DBGWVRn_EL1(2), CGT_MDCR_TDE_TDA),
999 SR_TRAP(SYS_DBGWVRn_EL1(3), CGT_MDCR_TDE_TDA),
1000 SR_TRAP(SYS_DBGWVRn_EL1(4), CGT_MDCR_TDE_TDA),
1001 SR_TRAP(SYS_DBGWVRn_EL1(5), CGT_MDCR_TDE_TDA),
1002 SR_TRAP(SYS_DBGWVRn_EL1(6), CGT_MDCR_TDE_TDA),
1003 SR_TRAP(SYS_DBGWVRn_EL1(7), CGT_MDCR_TDE_TDA),
1004 SR_TRAP(SYS_DBGWVRn_EL1(8), CGT_MDCR_TDE_TDA),
1005 SR_TRAP(SYS_DBGWVRn_EL1(9), CGT_MDCR_TDE_TDA),
1006 SR_TRAP(SYS_DBGWVRn_EL1(10), CGT_MDCR_TDE_TDA),
1007 SR_TRAP(SYS_DBGWVRn_EL1(11), CGT_MDCR_TDE_TDA),
1008 SR_TRAP(SYS_DBGWVRn_EL1(12), CGT_MDCR_TDE_TDA),
1009 SR_TRAP(SYS_DBGWVRn_EL1(13), CGT_MDCR_TDE_TDA),
1010 SR_TRAP(SYS_DBGWVRn_EL1(14), CGT_MDCR_TDE_TDA),
1011 SR_TRAP(SYS_DBGWVRn_EL1(15), CGT_MDCR_TDE_TDA),
1012 SR_TRAP(SYS_DBGWCRn_EL1(0), CGT_MDCR_TDE_TDA),
1013 SR_TRAP(SYS_DBGWCRn_EL1(1), CGT_MDCR_TDE_TDA),
1014 SR_TRAP(SYS_DBGWCRn_EL1(2), CGT_MDCR_TDE_TDA),
1015 SR_TRAP(SYS_DBGWCRn_EL1(3), CGT_MDCR_TDE_TDA),
1016 SR_TRAP(SYS_DBGWCRn_EL1(4), CGT_MDCR_TDE_TDA),
1017 SR_TRAP(SYS_DBGWCRn_EL1(5), CGT_MDCR_TDE_TDA),
1018 SR_TRAP(SYS_DBGWCRn_EL1(6), CGT_MDCR_TDE_TDA),
1019 SR_TRAP(SYS_DBGWCRn_EL1(7), CGT_MDCR_TDE_TDA),
1020 SR_TRAP(SYS_DBGWCRn_EL1(8), CGT_MDCR_TDE_TDA),
1021 SR_TRAP(SYS_DBGWCRn_EL1(9), CGT_MDCR_TDE_TDA),
1022 SR_TRAP(SYS_DBGWCRn_EL1(10), CGT_MDCR_TDE_TDA),
1023 SR_TRAP(SYS_DBGWCRn_EL1(11), CGT_MDCR_TDE_TDA),
1024 SR_TRAP(SYS_DBGWCRn_EL1(12), CGT_MDCR_TDE_TDA),
1025 SR_TRAP(SYS_DBGWCRn_EL1(13), CGT_MDCR_TDE_TDA),
1026 SR_TRAP(SYS_DBGWCRn_EL1(14), CGT_MDCR_TDE_TDA),
1027 SR_TRAP(SYS_DBGCLAIMSET_EL1, CGT_MDCR_TDE_TDA),
1028 SR_TRAP(SYS_DBGCLAIMCLR_EL1, CGT_MDCR_TDE_TDA),
1029 SR_TRAP(SYS_DBGAUTHSTATUS_EL1, CGT_MDCR_TDE_TDA),
1030 SR_TRAP(SYS_OSLAR_EL1, CGT_MDCR_TDE_TDOSA),
1031 SR_TRAP(SYS_OSLSR_EL1, CGT_MDCR_TDE_TDOSA),
1032 SR_TRAP(SYS_OSDLR_EL1, CGT_MDCR_TDE_TDOSA),
1033 SR_TRAP(SYS_DBGPRCR_EL1, CGT_MDCR_TDE_TDOSA),
1034 SR_TRAP(SYS_MDRAR_EL1, CGT_MDCR_TDE_TDRA),
1035 SR_TRAP(SYS_PMBLIMITR_EL1, CGT_MDCR_E2PB),
1036 SR_TRAP(SYS_PMBPTR_EL1, CGT_MDCR_E2PB),
1037 SR_TRAP(SYS_PMBSR_EL1, CGT_MDCR_E2PB),
1038 SR_TRAP(SYS_PMSCR_EL1, CGT_MDCR_TPMS),
1039 SR_TRAP(SYS_PMSEVFR_EL1, CGT_MDCR_TPMS),
1040 SR_TRAP(SYS_PMSFCR_EL1, CGT_MDCR_TPMS),
1041 SR_TRAP(SYS_PMSICR_EL1, CGT_MDCR_TPMS),
1042 SR_TRAP(SYS_PMSIDR_EL1, CGT_MDCR_TPMS),
1043 SR_TRAP(SYS_PMSIRR_EL1, CGT_MDCR_TPMS),
1044 SR_TRAP(SYS_PMSLATFR_EL1, CGT_MDCR_TPMS),
1045 SR_TRAP(SYS_PMSNEVFR_EL1, CGT_MDCR_TPMS),
1046 SR_TRAP(SYS_TRFCR_EL1, CGT_MDCR_TTRF),
1047 SR_TRAP(SYS_TRBBASER_EL1, CGT_MDCR_E2TB),
1048 SR_TRAP(SYS_TRBLIMITR_EL1, CGT_MDCR_E2TB),
1049 SR_TRAP(SYS_TRBMAR_EL1, CGT_MDCR_E2TB),
1050 SR_TRAP(SYS_TRBPTR_EL1, CGT_MDCR_E2TB),
1051 SR_TRAP(SYS_TRBSR_EL1, CGT_MDCR_E2TB),
1052 SR_TRAP(SYS_TRBTRG_EL1, CGT_MDCR_E2TB),
1053 SR_TRAP(SYS_CPACR_EL1, CGT_CPTR_TCPAC),
1054 SR_TRAP(SYS_AMUSERENR_EL0, CGT_CPTR_TAM),
1055 SR_TRAP(SYS_AMCFGR_EL0, CGT_CPTR_TAM),
1056 SR_TRAP(SYS_AMCGCR_EL0, CGT_CPTR_TAM),
1057 SR_TRAP(SYS_AMCNTENCLR0_EL0, CGT_CPTR_TAM),
1058 SR_TRAP(SYS_AMCNTENCLR1_EL0, CGT_CPTR_TAM),
1059 SR_TRAP(SYS_AMCNTENSET0_EL0, CGT_CPTR_TAM),
1060 SR_TRAP(SYS_AMCNTENSET1_EL0, CGT_CPTR_TAM),
1061 SR_TRAP(SYS_AMCR_EL0, CGT_CPTR_TAM),
1062 SR_TRAP(SYS_AMEVCNTR0_EL0(0), CGT_CPTR_TAM),
1063 SR_TRAP(SYS_AMEVCNTR0_EL0(1), CGT_CPTR_TAM),
1064 SR_TRAP(SYS_AMEVCNTR0_EL0(2), CGT_CPTR_TAM),
1065 SR_TRAP(SYS_AMEVCNTR0_EL0(3), CGT_CPTR_TAM),
1066 SR_TRAP(SYS_AMEVCNTR1_EL0(0), CGT_CPTR_TAM),
1067 SR_TRAP(SYS_AMEVCNTR1_EL0(1), CGT_CPTR_TAM),
1068 SR_TRAP(SYS_AMEVCNTR1_EL0(2), CGT_CPTR_TAM),
1069 SR_TRAP(SYS_AMEVCNTR1_EL0(3), CGT_CPTR_TAM),
1070 SR_TRAP(SYS_AMEVCNTR1_EL0(4), CGT_CPTR_TAM),
1071 SR_TRAP(SYS_AMEVCNTR1_EL0(5), CGT_CPTR_TAM),
1072 SR_TRAP(SYS_AMEVCNTR1_EL0(6), CGT_CPTR_TAM),
1073 SR_TRAP(SYS_AMEVCNTR1_EL0(7), CGT_CPTR_TAM),
1074 SR_TRAP(SYS_AMEVCNTR1_EL0(8), CGT_CPTR_TAM),
1075 SR_TRAP(SYS_AMEVCNTR1_EL0(9), CGT_CPTR_TAM),
1076 SR_TRAP(SYS_AMEVCNTR1_EL0(10), CGT_CPTR_TAM),
1077 SR_TRAP(SYS_AMEVCNTR1_EL0(11), CGT_CPTR_TAM),
1078 SR_TRAP(SYS_AMEVCNTR1_EL0(12), CGT_CPTR_TAM),
1079 SR_TRAP(SYS_AMEVCNTR1_EL0(13), CGT_CPTR_TAM),
1080 SR_TRAP(SYS_AMEVCNTR1_EL0(14), CGT_CPTR_TAM),
1081 SR_TRAP(SYS_AMEVCNTR1_EL0(15), CGT_CPTR_TAM),
1082 SR_TRAP(SYS_AMEVTYPER0_EL0(0), CGT_CPTR_TAM),
1083 SR_TRAP(SYS_AMEVTYPER0_EL0(1), CGT_CPTR_TAM),
1084 SR_TRAP(SYS_AMEVTYPER0_EL0(2), CGT_CPTR_TAM),
1085 SR_TRAP(SYS_AMEVTYPER0_EL0(3), CGT_CPTR_TAM),
1086 SR_TRAP(SYS_AMEVTYPER1_EL0(0), CGT_CPTR_TAM),
1087 SR_TRAP(SYS_AMEVTYPER1_EL0(1), CGT_CPTR_TAM),
1088 SR_TRAP(SYS_AMEVTYPER1_EL0(2), CGT_CPTR_TAM),
1089 SR_TRAP(SYS_AMEVTYPER1_EL0(3), CGT_CPTR_TAM),
1090 SR_TRAP(SYS_AMEVTYPER1_EL0(4), CGT_CPTR_TAM),
1091 SR_TRAP(SYS_AMEVTYPER1_EL0(5), CGT_CPTR_TAM),
1092 SR_TRAP(SYS_AMEVTYPER1_EL0(6), CGT_CPTR_TAM),
1093 SR_TRAP(SYS_AMEVTYPER1_EL0(7), CGT_CPTR_TAM),
1094 SR_TRAP(SYS_AMEVTYPER1_EL0(8), CGT_CPTR_TAM),
1095 SR_TRAP(SYS_AMEVTYPER1_EL0(9), CGT_CPTR_TAM),
1096 SR_TRAP(SYS_AMEVTYPER1_EL0(10), CGT_CPTR_TAM),
1097 SR_TRAP(SYS_AMEVTYPER1_EL0(11), CGT_CPTR_TAM),
1098 SR_TRAP(SYS_AMEVTYPER1_EL0(12), CGT_CPTR_TAM),
1099 SR_TRAP(SYS_AMEVTYPER1_EL0(13), CGT_CPTR_TAM),
1100 SR_TRAP(SYS_AMEVTYPER1_EL0(14), CGT_CPTR_TAM),
1101 SR_TRAP(SYS_AMEVTYPER1_EL0(15), CGT_CPTR_TAM),
1102 SR_TRAP(SYS_POR_EL0, CGT_CPACR_E0POE),
1103 /* op0=2, op1=1, and CRn<0b1000 */
1104 SR_RANGE_TRAP(sys_reg(2, 1, 0, 0, 0),
1105 sys_reg(2, 1, 7, 15, 7), CGT_CPTR_TTA),
1106 SR_TRAP(SYS_CNTP_TVAL_EL0, CGT_CNTHCTL_EL1PTEN),
1107 SR_TRAP(SYS_CNTP_CVAL_EL0, CGT_CNTHCTL_EL1PTEN),
1108 SR_TRAP(SYS_CNTP_CTL_EL0, CGT_CNTHCTL_EL1PTEN),
1109 SR_TRAP(SYS_CNTPCT_EL0, CGT_CNTHCTL_EL1PCTEN),
1110 SR_TRAP(SYS_CNTPCTSS_EL0, CGT_CNTHCTL_EL1PCTEN),
1111 };
1112
1113 static DEFINE_XARRAY(sr_forward_xa);
1114
1115 enum fg_filter_id {
1116 __NO_FGF__,
1117 HCRX_FGTnXS,
1118
1119 /* Must be last */
1120 __NR_FG_FILTER_IDS__
1121 };
1122
1123 #define SR_FGF(sr, g, b, p, f) \
1124 { \
1125 .encoding = sr, \
1126 .end = sr, \
1127 .tc = { \
1128 .fgt = g ## _GROUP, \
1129 .bit = g ## _EL2_ ## b ## _SHIFT, \
1130 .pol = p, \
1131 .fgf = f, \
1132 }, \
1133 .line = __LINE__, \
1134 }
1135
1136 #define SR_FGT(sr, g, b, p) SR_FGF(sr, g, b, p, __NO_FGF__)
1137
1138 static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
1139 /* HFGRTR_EL2, HFGWTR_EL2 */
1140 SR_FGT(SYS_AMAIR2_EL1, HFGxTR, nAMAIR2_EL1, 0),
1141 SR_FGT(SYS_MAIR2_EL1, HFGxTR, nMAIR2_EL1, 0),
1142 SR_FGT(SYS_S2POR_EL1, HFGxTR, nS2POR_EL1, 0),
1143 SR_FGT(SYS_POR_EL1, HFGxTR, nPOR_EL1, 0),
1144 SR_FGT(SYS_POR_EL0, HFGxTR, nPOR_EL0, 0),
1145 SR_FGT(SYS_PIR_EL1, HFGxTR, nPIR_EL1, 0),
1146 SR_FGT(SYS_PIRE0_EL1, HFGxTR, nPIRE0_EL1, 0),
1147 SR_FGT(SYS_RCWMASK_EL1, HFGxTR, nRCWMASK_EL1, 0),
1148 SR_FGT(SYS_TPIDR2_EL0, HFGxTR, nTPIDR2_EL0, 0),
1149 SR_FGT(SYS_SMPRI_EL1, HFGxTR, nSMPRI_EL1, 0),
1150 SR_FGT(SYS_GCSCR_EL1, HFGxTR, nGCS_EL1, 0),
1151 SR_FGT(SYS_GCSPR_EL1, HFGxTR, nGCS_EL1, 0),
1152 SR_FGT(SYS_GCSCRE0_EL1, HFGxTR, nGCS_EL0, 0),
1153 SR_FGT(SYS_GCSPR_EL0, HFGxTR, nGCS_EL0, 0),
1154 SR_FGT(SYS_ACCDATA_EL1, HFGxTR, nACCDATA_EL1, 0),
1155 SR_FGT(SYS_ERXADDR_EL1, HFGxTR, ERXADDR_EL1, 1),
1156 SR_FGT(SYS_ERXPFGCDN_EL1, HFGxTR, ERXPFGCDN_EL1, 1),
1157 SR_FGT(SYS_ERXPFGCTL_EL1, HFGxTR, ERXPFGCTL_EL1, 1),
1158 SR_FGT(SYS_ERXPFGF_EL1, HFGxTR, ERXPFGF_EL1, 1),
1159 SR_FGT(SYS_ERXMISC0_EL1, HFGxTR, ERXMISCn_EL1, 1),
1160 SR_FGT(SYS_ERXMISC1_EL1, HFGxTR, ERXMISCn_EL1, 1),
1161 SR_FGT(SYS_ERXMISC2_EL1, HFGxTR, ERXMISCn_EL1, 1),
1162 SR_FGT(SYS_ERXMISC3_EL1, HFGxTR, ERXMISCn_EL1, 1),
1163 SR_FGT(SYS_ERXSTATUS_EL1, HFGxTR, ERXSTATUS_EL1, 1),
1164 SR_FGT(SYS_ERXCTLR_EL1, HFGxTR, ERXCTLR_EL1, 1),
1165 SR_FGT(SYS_ERXFR_EL1, HFGxTR, ERXFR_EL1, 1),
1166 SR_FGT(SYS_ERRSELR_EL1, HFGxTR, ERRSELR_EL1, 1),
1167 SR_FGT(SYS_ERRIDR_EL1, HFGxTR, ERRIDR_EL1, 1),
1168 SR_FGT(SYS_ICC_IGRPEN0_EL1, HFGxTR, ICC_IGRPENn_EL1, 1),
1169 SR_FGT(SYS_ICC_IGRPEN1_EL1, HFGxTR, ICC_IGRPENn_EL1, 1),
1170 SR_FGT(SYS_VBAR_EL1, HFGxTR, VBAR_EL1, 1),
1171 SR_FGT(SYS_TTBR1_EL1, HFGxTR, TTBR1_EL1, 1),
1172 SR_FGT(SYS_TTBR0_EL1, HFGxTR, TTBR0_EL1, 1),
1173 SR_FGT(SYS_TPIDR_EL0, HFGxTR, TPIDR_EL0, 1),
1174 SR_FGT(SYS_TPIDRRO_EL0, HFGxTR, TPIDRRO_EL0, 1),
1175 SR_FGT(SYS_TPIDR_EL1, HFGxTR, TPIDR_EL1, 1),
1176 SR_FGT(SYS_TCR_EL1, HFGxTR, TCR_EL1, 1),
1177 SR_FGT(SYS_TCR2_EL1, HFGxTR, TCR_EL1, 1),
1178 SR_FGT(SYS_SCXTNUM_EL0, HFGxTR, SCXTNUM_EL0, 1),
1179 SR_FGT(SYS_SCXTNUM_EL1, HFGxTR, SCXTNUM_EL1, 1),
1180 SR_FGT(SYS_SCTLR_EL1, HFGxTR, SCTLR_EL1, 1),
1181 SR_FGT(SYS_REVIDR_EL1, HFGxTR, REVIDR_EL1, 1),
1182 SR_FGT(SYS_PAR_EL1, HFGxTR, PAR_EL1, 1),
1183 SR_FGT(SYS_MPIDR_EL1, HFGxTR, MPIDR_EL1, 1),
1184 SR_FGT(SYS_MIDR_EL1, HFGxTR, MIDR_EL1, 1),
1185 SR_FGT(SYS_MAIR_EL1, HFGxTR, MAIR_EL1, 1),
1186 SR_FGT(SYS_LORSA_EL1, HFGxTR, LORSA_EL1, 1),
1187 SR_FGT(SYS_LORN_EL1, HFGxTR, LORN_EL1, 1),
1188 SR_FGT(SYS_LORID_EL1, HFGxTR, LORID_EL1, 1),
1189 SR_FGT(SYS_LOREA_EL1, HFGxTR, LOREA_EL1, 1),
1190 SR_FGT(SYS_LORC_EL1, HFGxTR, LORC_EL1, 1),
1191 SR_FGT(SYS_ISR_EL1, HFGxTR, ISR_EL1, 1),
1192 SR_FGT(SYS_FAR_EL1, HFGxTR, FAR_EL1, 1),
1193 SR_FGT(SYS_ESR_EL1, HFGxTR, ESR_EL1, 1),
1194 SR_FGT(SYS_DCZID_EL0, HFGxTR, DCZID_EL0, 1),
1195 SR_FGT(SYS_CTR_EL0, HFGxTR, CTR_EL0, 1),
1196 SR_FGT(SYS_CSSELR_EL1, HFGxTR, CSSELR_EL1, 1),
1197 SR_FGT(SYS_CPACR_EL1, HFGxTR, CPACR_EL1, 1),
1198 SR_FGT(SYS_CONTEXTIDR_EL1, HFGxTR, CONTEXTIDR_EL1, 1),
1199 SR_FGT(SYS_CLIDR_EL1, HFGxTR, CLIDR_EL1, 1),
1200 SR_FGT(SYS_CCSIDR_EL1, HFGxTR, CCSIDR_EL1, 1),
1201 SR_FGT(SYS_APIBKEYLO_EL1, HFGxTR, APIBKey, 1),
1202 SR_FGT(SYS_APIBKEYHI_EL1, HFGxTR, APIBKey, 1),
1203 SR_FGT(SYS_APIAKEYLO_EL1, HFGxTR, APIAKey, 1),
1204 SR_FGT(SYS_APIAKEYHI_EL1, HFGxTR, APIAKey, 1),
1205 SR_FGT(SYS_APGAKEYLO_EL1, HFGxTR, APGAKey, 1),
1206 SR_FGT(SYS_APGAKEYHI_EL1, HFGxTR, APGAKey, 1),
1207 SR_FGT(SYS_APDBKEYLO_EL1, HFGxTR, APDBKey, 1),
1208 SR_FGT(SYS_APDBKEYHI_EL1, HFGxTR, APDBKey, 1),
1209 SR_FGT(SYS_APDAKEYLO_EL1, HFGxTR, APDAKey, 1),
1210 SR_FGT(SYS_APDAKEYHI_EL1, HFGxTR, APDAKey, 1),
1211 SR_FGT(SYS_AMAIR_EL1, HFGxTR, AMAIR_EL1, 1),
1212 SR_FGT(SYS_AIDR_EL1, HFGxTR, AIDR_EL1, 1),
1213 SR_FGT(SYS_AFSR1_EL1, HFGxTR, AFSR1_EL1, 1),
1214 SR_FGT(SYS_AFSR0_EL1, HFGxTR, AFSR0_EL1, 1),
1215 /* HFGITR_EL2 */
1216 SR_FGT(OP_AT_S1E1A, HFGITR, ATS1E1A, 1),
1217 SR_FGT(OP_COSP_RCTX, HFGITR, COSPRCTX, 1),
1218 SR_FGT(OP_GCSPUSHX, HFGITR, nGCSEPP, 0),
1219 SR_FGT(OP_GCSPOPX, HFGITR, nGCSEPP, 0),
1220 SR_FGT(OP_GCSPUSHM, HFGITR, nGCSPUSHM_EL1, 0),
1221 SR_FGT(OP_BRB_IALL, HFGITR, nBRBIALL, 0),
1222 SR_FGT(OP_BRB_INJ, HFGITR, nBRBINJ, 0),
1223 SR_FGT(SYS_DC_CVAC, HFGITR, DCCVAC, 1),
1224 SR_FGT(SYS_DC_CGVAC, HFGITR, DCCVAC, 1),
1225 SR_FGT(SYS_DC_CGDVAC, HFGITR, DCCVAC, 1),
1226 SR_FGT(OP_CPP_RCTX, HFGITR, CPPRCTX, 1),
1227 SR_FGT(OP_DVP_RCTX, HFGITR, DVPRCTX, 1),
1228 SR_FGT(OP_CFP_RCTX, HFGITR, CFPRCTX, 1),
1229 SR_FGT(OP_TLBI_VAALE1, HFGITR, TLBIVAALE1, 1),
1230 SR_FGT(OP_TLBI_VALE1, HFGITR, TLBIVALE1, 1),
1231 SR_FGT(OP_TLBI_VAAE1, HFGITR, TLBIVAAE1, 1),
1232 SR_FGT(OP_TLBI_ASIDE1, HFGITR, TLBIASIDE1, 1),
1233 SR_FGT(OP_TLBI_VAE1, HFGITR, TLBIVAE1, 1),
1234 SR_FGT(OP_TLBI_VMALLE1, HFGITR, TLBIVMALLE1, 1),
1235 SR_FGT(OP_TLBI_RVAALE1, HFGITR, TLBIRVAALE1, 1),
1236 SR_FGT(OP_TLBI_RVALE1, HFGITR, TLBIRVALE1, 1),
1237 SR_FGT(OP_TLBI_RVAAE1, HFGITR, TLBIRVAAE1, 1),
1238 SR_FGT(OP_TLBI_RVAE1, HFGITR, TLBIRVAE1, 1),
1239 SR_FGT(OP_TLBI_RVAALE1IS, HFGITR, TLBIRVAALE1IS, 1),
1240 SR_FGT(OP_TLBI_RVALE1IS, HFGITR, TLBIRVALE1IS, 1),
1241 SR_FGT(OP_TLBI_RVAAE1IS, HFGITR, TLBIRVAAE1IS, 1),
1242 SR_FGT(OP_TLBI_RVAE1IS, HFGITR, TLBIRVAE1IS, 1),
1243 SR_FGT(OP_TLBI_VAALE1IS, HFGITR, TLBIVAALE1IS, 1),
1244 SR_FGT(OP_TLBI_VALE1IS, HFGITR, TLBIVALE1IS, 1),
1245 SR_FGT(OP_TLBI_VAAE1IS, HFGITR, TLBIVAAE1IS, 1),
1246 SR_FGT(OP_TLBI_ASIDE1IS, HFGITR, TLBIASIDE1IS, 1),
1247 SR_FGT(OP_TLBI_VAE1IS, HFGITR, TLBIVAE1IS, 1),
1248 SR_FGT(OP_TLBI_VMALLE1IS, HFGITR, TLBIVMALLE1IS, 1),
1249 SR_FGT(OP_TLBI_RVAALE1OS, HFGITR, TLBIRVAALE1OS, 1),
1250 SR_FGT(OP_TLBI_RVALE1OS, HFGITR, TLBIRVALE1OS, 1),
1251 SR_FGT(OP_TLBI_RVAAE1OS, HFGITR, TLBIRVAAE1OS, 1),
1252 SR_FGT(OP_TLBI_RVAE1OS, HFGITR, TLBIRVAE1OS, 1),
1253 SR_FGT(OP_TLBI_VAALE1OS, HFGITR, TLBIVAALE1OS, 1),
1254 SR_FGT(OP_TLBI_VALE1OS, HFGITR, TLBIVALE1OS, 1),
1255 SR_FGT(OP_TLBI_VAAE1OS, HFGITR, TLBIVAAE1OS, 1),
1256 SR_FGT(OP_TLBI_ASIDE1OS, HFGITR, TLBIASIDE1OS, 1),
1257 SR_FGT(OP_TLBI_VAE1OS, HFGITR, TLBIVAE1OS, 1),
1258 SR_FGT(OP_TLBI_VMALLE1OS, HFGITR, TLBIVMALLE1OS, 1),
1259 /* nXS variants must be checked against HCRX_EL2.FGTnXS */
1260 SR_FGF(OP_TLBI_VAALE1NXS, HFGITR, TLBIVAALE1, 1, HCRX_FGTnXS),
1261 SR_FGF(OP_TLBI_VALE1NXS, HFGITR, TLBIVALE1, 1, HCRX_FGTnXS),
1262 SR_FGF(OP_TLBI_VAAE1NXS, HFGITR, TLBIVAAE1, 1, HCRX_FGTnXS),
1263 SR_FGF(OP_TLBI_ASIDE1NXS, HFGITR, TLBIASIDE1, 1, HCRX_FGTnXS),
1264 SR_FGF(OP_TLBI_VAE1NXS, HFGITR, TLBIVAE1, 1, HCRX_FGTnXS),
1265 SR_FGF(OP_TLBI_VMALLE1NXS, HFGITR, TLBIVMALLE1, 1, HCRX_FGTnXS),
1266 SR_FGF(OP_TLBI_RVAALE1NXS, HFGITR, TLBIRVAALE1, 1, HCRX_FGTnXS),
1267 SR_FGF(OP_TLBI_RVALE1NXS, HFGITR, TLBIRVALE1, 1, HCRX_FGTnXS),
1268 SR_FGF(OP_TLBI_RVAAE1NXS, HFGITR, TLBIRVAAE1, 1, HCRX_FGTnXS),
1269 SR_FGF(OP_TLBI_RVAE1NXS, HFGITR, TLBIRVAE1, 1, HCRX_FGTnXS),
1270 SR_FGF(OP_TLBI_RVAALE1ISNXS, HFGITR, TLBIRVAALE1IS, 1, HCRX_FGTnXS),
1271 SR_FGF(OP_TLBI_RVALE1ISNXS, HFGITR, TLBIRVALE1IS, 1, HCRX_FGTnXS),
1272 SR_FGF(OP_TLBI_RVAAE1ISNXS, HFGITR, TLBIRVAAE1IS, 1, HCRX_FGTnXS),
1273 SR_FGF(OP_TLBI_RVAE1ISNXS, HFGITR, TLBIRVAE1IS, 1, HCRX_FGTnXS),
1274 SR_FGF(OP_TLBI_VAALE1ISNXS, HFGITR, TLBIVAALE1IS, 1, HCRX_FGTnXS),
1275 SR_FGF(OP_TLBI_VALE1ISNXS, HFGITR, TLBIVALE1IS, 1, HCRX_FGTnXS),
1276 SR_FGF(OP_TLBI_VAAE1ISNXS, HFGITR, TLBIVAAE1IS, 1, HCRX_FGTnXS),
1277 SR_FGF(OP_TLBI_ASIDE1ISNXS, HFGITR, TLBIASIDE1IS, 1, HCRX_FGTnXS),
1278 SR_FGF(OP_TLBI_VAE1ISNXS, HFGITR, TLBIVAE1IS, 1, HCRX_FGTnXS),
1279 SR_FGF(OP_TLBI_VMALLE1ISNXS, HFGITR, TLBIVMALLE1IS, 1, HCRX_FGTnXS),
1280 SR_FGF(OP_TLBI_RVAALE1OSNXS, HFGITR, TLBIRVAALE1OS, 1, HCRX_FGTnXS),
1281 SR_FGF(OP_TLBI_RVALE1OSNXS, HFGITR, TLBIRVALE1OS, 1, HCRX_FGTnXS),
1282 SR_FGF(OP_TLBI_RVAAE1OSNXS, HFGITR, TLBIRVAAE1OS, 1, HCRX_FGTnXS),
1283 SR_FGF(OP_TLBI_RVAE1OSNXS, HFGITR, TLBIRVAE1OS, 1, HCRX_FGTnXS),
1284 SR_FGF(OP_TLBI_VAALE1OSNXS, HFGITR, TLBIVAALE1OS, 1, HCRX_FGTnXS),
1285 SR_FGF(OP_TLBI_VALE1OSNXS, HFGITR, TLBIVALE1OS, 1, HCRX_FGTnXS),
1286 SR_FGF(OP_TLBI_VAAE1OSNXS, HFGITR, TLBIVAAE1OS, 1, HCRX_FGTnXS),
1287 SR_FGF(OP_TLBI_ASIDE1OSNXS, HFGITR, TLBIASIDE1OS, 1, HCRX_FGTnXS),
1288 SR_FGF(OP_TLBI_VAE1OSNXS, HFGITR, TLBIVAE1OS, 1, HCRX_FGTnXS),
1289 SR_FGF(OP_TLBI_VMALLE1OSNXS, HFGITR, TLBIVMALLE1OS, 1, HCRX_FGTnXS),
1290 SR_FGT(OP_AT_S1E1WP, HFGITR, ATS1E1WP, 1),
1291 SR_FGT(OP_AT_S1E1RP, HFGITR, ATS1E1RP, 1),
1292 SR_FGT(OP_AT_S1E0W, HFGITR, ATS1E0W, 1),
1293 SR_FGT(OP_AT_S1E0R, HFGITR, ATS1E0R, 1),
1294 SR_FGT(OP_AT_S1E1W, HFGITR, ATS1E1W, 1),
1295 SR_FGT(OP_AT_S1E1R, HFGITR, ATS1E1R, 1),
1296 SR_FGT(SYS_DC_ZVA, HFGITR, DCZVA, 1),
1297 SR_FGT(SYS_DC_GVA, HFGITR, DCZVA, 1),
1298 SR_FGT(SYS_DC_GZVA, HFGITR, DCZVA, 1),
1299 SR_FGT(SYS_DC_CIVAC, HFGITR, DCCIVAC, 1),
1300 SR_FGT(SYS_DC_CIGVAC, HFGITR, DCCIVAC, 1),
1301 SR_FGT(SYS_DC_CIGDVAC, HFGITR, DCCIVAC, 1),
1302 SR_FGT(SYS_DC_CVADP, HFGITR, DCCVADP, 1),
1303 SR_FGT(SYS_DC_CGVADP, HFGITR, DCCVADP, 1),
1304 SR_FGT(SYS_DC_CGDVADP, HFGITR, DCCVADP, 1),
1305 SR_FGT(SYS_DC_CVAP, HFGITR, DCCVAP, 1),
1306 SR_FGT(SYS_DC_CGVAP, HFGITR, DCCVAP, 1),
1307 SR_FGT(SYS_DC_CGDVAP, HFGITR, DCCVAP, 1),
1308 SR_FGT(SYS_DC_CVAU, HFGITR, DCCVAU, 1),
1309 SR_FGT(SYS_DC_CISW, HFGITR, DCCISW, 1),
1310 SR_FGT(SYS_DC_CIGSW, HFGITR, DCCISW, 1),
1311 SR_FGT(SYS_DC_CIGDSW, HFGITR, DCCISW, 1),
1312 SR_FGT(SYS_DC_CSW, HFGITR, DCCSW, 1),
1313 SR_FGT(SYS_DC_CGSW, HFGITR, DCCSW, 1),
1314 SR_FGT(SYS_DC_CGDSW, HFGITR, DCCSW, 1),
1315 SR_FGT(SYS_DC_ISW, HFGITR, DCISW, 1),
1316 SR_FGT(SYS_DC_IGSW, HFGITR, DCISW, 1),
1317 SR_FGT(SYS_DC_IGDSW, HFGITR, DCISW, 1),
1318 SR_FGT(SYS_DC_IVAC, HFGITR, DCIVAC, 1),
1319 SR_FGT(SYS_DC_IGVAC, HFGITR, DCIVAC, 1),
1320 SR_FGT(SYS_DC_IGDVAC, HFGITR, DCIVAC, 1),
1321 SR_FGT(SYS_IC_IVAU, HFGITR, ICIVAU, 1),
1322 SR_FGT(SYS_IC_IALLU, HFGITR, ICIALLU, 1),
1323 SR_FGT(SYS_IC_IALLUIS, HFGITR, ICIALLUIS, 1),
1324 /* HDFGRTR_EL2 */
1325 SR_FGT(SYS_PMBIDR_EL1, HDFGRTR, PMBIDR_EL1, 1),
1326 SR_FGT(SYS_PMSNEVFR_EL1, HDFGRTR, nPMSNEVFR_EL1, 0),
1327 SR_FGT(SYS_BRBINF_EL1(0), HDFGRTR, nBRBDATA, 0),
1328 SR_FGT(SYS_BRBINF_EL1(1), HDFGRTR, nBRBDATA, 0),
1329 SR_FGT(SYS_BRBINF_EL1(2), HDFGRTR, nBRBDATA, 0),
1330 SR_FGT(SYS_BRBINF_EL1(3), HDFGRTR, nBRBDATA, 0),
1331 SR_FGT(SYS_BRBINF_EL1(4), HDFGRTR, nBRBDATA, 0),
1332 SR_FGT(SYS_BRBINF_EL1(5), HDFGRTR, nBRBDATA, 0),
1333 SR_FGT(SYS_BRBINF_EL1(6), HDFGRTR, nBRBDATA, 0),
1334 SR_FGT(SYS_BRBINF_EL1(7), HDFGRTR, nBRBDATA, 0),
1335 SR_FGT(SYS_BRBINF_EL1(8), HDFGRTR, nBRBDATA, 0),
1336 SR_FGT(SYS_BRBINF_EL1(9), HDFGRTR, nBRBDATA, 0),
1337 SR_FGT(SYS_BRBINF_EL1(10), HDFGRTR, nBRBDATA, 0),
1338 SR_FGT(SYS_BRBINF_EL1(11), HDFGRTR, nBRBDATA, 0),
1339 SR_FGT(SYS_BRBINF_EL1(12), HDFGRTR, nBRBDATA, 0),
1340 SR_FGT(SYS_BRBINF_EL1(13), HDFGRTR, nBRBDATA, 0),
1341 SR_FGT(SYS_BRBINF_EL1(14), HDFGRTR, nBRBDATA, 0),
1342 SR_FGT(SYS_BRBINF_EL1(15), HDFGRTR, nBRBDATA, 0),
1343 SR_FGT(SYS_BRBINF_EL1(16), HDFGRTR, nBRBDATA, 0),
1344 SR_FGT(SYS_BRBINF_EL1(17), HDFGRTR, nBRBDATA, 0),
1345 SR_FGT(SYS_BRBINF_EL1(18), HDFGRTR, nBRBDATA, 0),
1346 SR_FGT(SYS_BRBINF_EL1(19), HDFGRTR, nBRBDATA, 0),
1347 SR_FGT(SYS_BRBINF_EL1(20), HDFGRTR, nBRBDATA, 0),
1348 SR_FGT(SYS_BRBINF_EL1(21), HDFGRTR, nBRBDATA, 0),
1349 SR_FGT(SYS_BRBINF_EL1(22), HDFGRTR, nBRBDATA, 0),
1350 SR_FGT(SYS_BRBINF_EL1(23), HDFGRTR, nBRBDATA, 0),
1351 SR_FGT(SYS_BRBINF_EL1(24), HDFGRTR, nBRBDATA, 0),
1352 SR_FGT(SYS_BRBINF_EL1(25), HDFGRTR, nBRBDATA, 0),
1353 SR_FGT(SYS_BRBINF_EL1(26), HDFGRTR, nBRBDATA, 0),
1354 SR_FGT(SYS_BRBINF_EL1(27), HDFGRTR, nBRBDATA, 0),
1355 SR_FGT(SYS_BRBINF_EL1(28), HDFGRTR, nBRBDATA, 0),
1356 SR_FGT(SYS_BRBINF_EL1(29), HDFGRTR, nBRBDATA, 0),
1357 SR_FGT(SYS_BRBINF_EL1(30), HDFGRTR, nBRBDATA, 0),
1358 SR_FGT(SYS_BRBINF_EL1(31), HDFGRTR, nBRBDATA, 0),
1359 SR_FGT(SYS_BRBINFINJ_EL1, HDFGRTR, nBRBDATA, 0),
1360 SR_FGT(SYS_BRBSRC_EL1(0), HDFGRTR, nBRBDATA, 0),
1361 SR_FGT(SYS_BRBSRC_EL1(1), HDFGRTR, nBRBDATA, 0),
1362 SR_FGT(SYS_BRBSRC_EL1(2), HDFGRTR, nBRBDATA, 0),
1363 SR_FGT(SYS_BRBSRC_EL1(3), HDFGRTR, nBRBDATA, 0),
1364 SR_FGT(SYS_BRBSRC_EL1(4), HDFGRTR, nBRBDATA, 0),
1365 SR_FGT(SYS_BRBSRC_EL1(5), HDFGRTR, nBRBDATA, 0),
1366 SR_FGT(SYS_BRBSRC_EL1(6), HDFGRTR, nBRBDATA, 0),
1367 SR_FGT(SYS_BRBSRC_EL1(7), HDFGRTR, nBRBDATA, 0),
1368 SR_FGT(SYS_BRBSRC_EL1(8), HDFGRTR, nBRBDATA, 0),
1369 SR_FGT(SYS_BRBSRC_EL1(9), HDFGRTR, nBRBDATA, 0),
1370 SR_FGT(SYS_BRBSRC_EL1(10), HDFGRTR, nBRBDATA, 0),
1371 SR_FGT(SYS_BRBSRC_EL1(11), HDFGRTR, nBRBDATA, 0),
1372 SR_FGT(SYS_BRBSRC_EL1(12), HDFGRTR, nBRBDATA, 0),
1373 SR_FGT(SYS_BRBSRC_EL1(13), HDFGRTR, nBRBDATA, 0),
1374 SR_FGT(SYS_BRBSRC_EL1(14), HDFGRTR, nBRBDATA, 0),
1375 SR_FGT(SYS_BRBSRC_EL1(15), HDFGRTR, nBRBDATA, 0),
1376 SR_FGT(SYS_BRBSRC_EL1(16), HDFGRTR, nBRBDATA, 0),
1377 SR_FGT(SYS_BRBSRC_EL1(17), HDFGRTR, nBRBDATA, 0),
1378 SR_FGT(SYS_BRBSRC_EL1(18), HDFGRTR, nBRBDATA, 0),
1379 SR_FGT(SYS_BRBSRC_EL1(19), HDFGRTR, nBRBDATA, 0),
1380 SR_FGT(SYS_BRBSRC_EL1(20), HDFGRTR, nBRBDATA, 0),
1381 SR_FGT(SYS_BRBSRC_EL1(21), HDFGRTR, nBRBDATA, 0),
1382 SR_FGT(SYS_BRBSRC_EL1(22), HDFGRTR, nBRBDATA, 0),
1383 SR_FGT(SYS_BRBSRC_EL1(23), HDFGRTR, nBRBDATA, 0),
1384 SR_FGT(SYS_BRBSRC_EL1(24), HDFGRTR, nBRBDATA, 0),
1385 SR_FGT(SYS_BRBSRC_EL1(25), HDFGRTR, nBRBDATA, 0),
1386 SR_FGT(SYS_BRBSRC_EL1(26), HDFGRTR, nBRBDATA, 0),
1387 SR_FGT(SYS_BRBSRC_EL1(27), HDFGRTR, nBRBDATA, 0),
1388 SR_FGT(SYS_BRBSRC_EL1(28), HDFGRTR, nBRBDATA, 0),
1389 SR_FGT(SYS_BRBSRC_EL1(29), HDFGRTR, nBRBDATA, 0),
1390 SR_FGT(SYS_BRBSRC_EL1(30), HDFGRTR, nBRBDATA, 0),
1391 SR_FGT(SYS_BRBSRC_EL1(31), HDFGRTR, nBRBDATA, 0),
1392 SR_FGT(SYS_BRBSRCINJ_EL1, HDFGRTR, nBRBDATA, 0),
1393 SR_FGT(SYS_BRBTGT_EL1(0), HDFGRTR, nBRBDATA, 0),
1394 SR_FGT(SYS_BRBTGT_EL1(1), HDFGRTR, nBRBDATA, 0),
1395 SR_FGT(SYS_BRBTGT_EL1(2), HDFGRTR, nBRBDATA, 0),
1396 SR_FGT(SYS_BRBTGT_EL1(3), HDFGRTR, nBRBDATA, 0),
1397 SR_FGT(SYS_BRBTGT_EL1(4), HDFGRTR, nBRBDATA, 0),
1398 SR_FGT(SYS_BRBTGT_EL1(5), HDFGRTR, nBRBDATA, 0),
1399 SR_FGT(SYS_BRBTGT_EL1(6), HDFGRTR, nBRBDATA, 0),
1400 SR_FGT(SYS_BRBTGT_EL1(7), HDFGRTR, nBRBDATA, 0),
1401 SR_FGT(SYS_BRBTGT_EL1(8), HDFGRTR, nBRBDATA, 0),
1402 SR_FGT(SYS_BRBTGT_EL1(9), HDFGRTR, nBRBDATA, 0),
1403 SR_FGT(SYS_BRBTGT_EL1(10), HDFGRTR, nBRBDATA, 0),
1404 SR_FGT(SYS_BRBTGT_EL1(11), HDFGRTR, nBRBDATA, 0),
1405 SR_FGT(SYS_BRBTGT_EL1(12), HDFGRTR, nBRBDATA, 0),
1406 SR_FGT(SYS_BRBTGT_EL1(13), HDFGRTR, nBRBDATA, 0),
1407 SR_FGT(SYS_BRBTGT_EL1(14), HDFGRTR, nBRBDATA, 0),
1408 SR_FGT(SYS_BRBTGT_EL1(15), HDFGRTR, nBRBDATA, 0),
1409 SR_FGT(SYS_BRBTGT_EL1(16), HDFGRTR, nBRBDATA, 0),
1410 SR_FGT(SYS_BRBTGT_EL1(17), HDFGRTR, nBRBDATA, 0),
1411 SR_FGT(SYS_BRBTGT_EL1(18), HDFGRTR, nBRBDATA, 0),
1412 SR_FGT(SYS_BRBTGT_EL1(19), HDFGRTR, nBRBDATA, 0),
1413 SR_FGT(SYS_BRBTGT_EL1(20), HDFGRTR, nBRBDATA, 0),
1414 SR_FGT(SYS_BRBTGT_EL1(21), HDFGRTR, nBRBDATA, 0),
1415 SR_FGT(SYS_BRBTGT_EL1(22), HDFGRTR, nBRBDATA, 0),
1416 SR_FGT(SYS_BRBTGT_EL1(23), HDFGRTR, nBRBDATA, 0),
1417 SR_FGT(SYS_BRBTGT_EL1(24), HDFGRTR, nBRBDATA, 0),
1418 SR_FGT(SYS_BRBTGT_EL1(25), HDFGRTR, nBRBDATA, 0),
1419 SR_FGT(SYS_BRBTGT_EL1(26), HDFGRTR, nBRBDATA, 0),
1420 SR_FGT(SYS_BRBTGT_EL1(27), HDFGRTR, nBRBDATA, 0),
1421 SR_FGT(SYS_BRBTGT_EL1(28), HDFGRTR, nBRBDATA, 0),
1422 SR_FGT(SYS_BRBTGT_EL1(29), HDFGRTR, nBRBDATA, 0),
1423 SR_FGT(SYS_BRBTGT_EL1(30), HDFGRTR, nBRBDATA, 0),
1424 SR_FGT(SYS_BRBTGT_EL1(31), HDFGRTR, nBRBDATA, 0),
1425 SR_FGT(SYS_BRBTGTINJ_EL1, HDFGRTR, nBRBDATA, 0),
1426 SR_FGT(SYS_BRBTS_EL1, HDFGRTR, nBRBDATA, 0),
1427 SR_FGT(SYS_BRBCR_EL1, HDFGRTR, nBRBCTL, 0),
1428 SR_FGT(SYS_BRBFCR_EL1, HDFGRTR, nBRBCTL, 0),
1429 SR_FGT(SYS_BRBIDR0_EL1, HDFGRTR, nBRBIDR, 0),
1430 SR_FGT(SYS_PMCEID0_EL0, HDFGRTR, PMCEIDn_EL0, 1),
1431 SR_FGT(SYS_PMCEID1_EL0, HDFGRTR, PMCEIDn_EL0, 1),
1432 SR_FGT(SYS_PMUSERENR_EL0, HDFGRTR, PMUSERENR_EL0, 1),
1433 SR_FGT(SYS_TRBTRG_EL1, HDFGRTR, TRBTRG_EL1, 1),
1434 SR_FGT(SYS_TRBSR_EL1, HDFGRTR, TRBSR_EL1, 1),
1435 SR_FGT(SYS_TRBPTR_EL1, HDFGRTR, TRBPTR_EL1, 1),
1436 SR_FGT(SYS_TRBMAR_EL1, HDFGRTR, TRBMAR_EL1, 1),
1437 SR_FGT(SYS_TRBLIMITR_EL1, HDFGRTR, TRBLIMITR_EL1, 1),
1438 SR_FGT(SYS_TRBIDR_EL1, HDFGRTR, TRBIDR_EL1, 1),
1439 SR_FGT(SYS_TRBBASER_EL1, HDFGRTR, TRBBASER_EL1, 1),
1440 SR_FGT(SYS_TRCVICTLR, HDFGRTR, TRCVICTLR, 1),
1441 SR_FGT(SYS_TRCSTATR, HDFGRTR, TRCSTATR, 1),
1442 SR_FGT(SYS_TRCSSCSR(0), HDFGRTR, TRCSSCSRn, 1),
1443 SR_FGT(SYS_TRCSSCSR(1), HDFGRTR, TRCSSCSRn, 1),
1444 SR_FGT(SYS_TRCSSCSR(2), HDFGRTR, TRCSSCSRn, 1),
1445 SR_FGT(SYS_TRCSSCSR(3), HDFGRTR, TRCSSCSRn, 1),
1446 SR_FGT(SYS_TRCSSCSR(4), HDFGRTR, TRCSSCSRn, 1),
1447 SR_FGT(SYS_TRCSSCSR(5), HDFGRTR, TRCSSCSRn, 1),
1448 SR_FGT(SYS_TRCSSCSR(6), HDFGRTR, TRCSSCSRn, 1),
1449 SR_FGT(SYS_TRCSSCSR(7), HDFGRTR, TRCSSCSRn, 1),
1450 SR_FGT(SYS_TRCSEQSTR, HDFGRTR, TRCSEQSTR, 1),
1451 SR_FGT(SYS_TRCPRGCTLR, HDFGRTR, TRCPRGCTLR, 1),
1452 SR_FGT(SYS_TRCOSLSR, HDFGRTR, TRCOSLSR, 1),
1453 SR_FGT(SYS_TRCIMSPEC(0), HDFGRTR, TRCIMSPECn, 1),
1454 SR_FGT(SYS_TRCIMSPEC(1), HDFGRTR, TRCIMSPECn, 1),
1455 SR_FGT(SYS_TRCIMSPEC(2), HDFGRTR, TRCIMSPECn, 1),
1456 SR_FGT(SYS_TRCIMSPEC(3), HDFGRTR, TRCIMSPECn, 1),
1457 SR_FGT(SYS_TRCIMSPEC(4), HDFGRTR, TRCIMSPECn, 1),
1458 SR_FGT(SYS_TRCIMSPEC(5), HDFGRTR, TRCIMSPECn, 1),
1459 SR_FGT(SYS_TRCIMSPEC(6), HDFGRTR, TRCIMSPECn, 1),
1460 SR_FGT(SYS_TRCIMSPEC(7), HDFGRTR, TRCIMSPECn, 1),
1461 SR_FGT(SYS_TRCDEVARCH, HDFGRTR, TRCID, 1),
1462 SR_FGT(SYS_TRCDEVID, HDFGRTR, TRCID, 1),
1463 SR_FGT(SYS_TRCIDR0, HDFGRTR, TRCID, 1),
1464 SR_FGT(SYS_TRCIDR1, HDFGRTR, TRCID, 1),
1465 SR_FGT(SYS_TRCIDR2, HDFGRTR, TRCID, 1),
1466 SR_FGT(SYS_TRCIDR3, HDFGRTR, TRCID, 1),
1467 SR_FGT(SYS_TRCIDR4, HDFGRTR, TRCID, 1),
1468 SR_FGT(SYS_TRCIDR5, HDFGRTR, TRCID, 1),
1469 SR_FGT(SYS_TRCIDR6, HDFGRTR, TRCID, 1),
1470 SR_FGT(SYS_TRCIDR7, HDFGRTR, TRCID, 1),
1471 SR_FGT(SYS_TRCIDR8, HDFGRTR, TRCID, 1),
1472 SR_FGT(SYS_TRCIDR9, HDFGRTR, TRCID, 1),
1473 SR_FGT(SYS_TRCIDR10, HDFGRTR, TRCID, 1),
1474 SR_FGT(SYS_TRCIDR11, HDFGRTR, TRCID, 1),
1475 SR_FGT(SYS_TRCIDR12, HDFGRTR, TRCID, 1),
1476 SR_FGT(SYS_TRCIDR13, HDFGRTR, TRCID, 1),
1477 SR_FGT(SYS_TRCCNTVR(0), HDFGRTR, TRCCNTVRn, 1),
1478 SR_FGT(SYS_TRCCNTVR(1), HDFGRTR, TRCCNTVRn, 1),
1479 SR_FGT(SYS_TRCCNTVR(2), HDFGRTR, TRCCNTVRn, 1),
1480 SR_FGT(SYS_TRCCNTVR(3), HDFGRTR, TRCCNTVRn, 1),
1481 SR_FGT(SYS_TRCCLAIMCLR, HDFGRTR, TRCCLAIM, 1),
1482 SR_FGT(SYS_TRCCLAIMSET, HDFGRTR, TRCCLAIM, 1),
1483 SR_FGT(SYS_TRCAUXCTLR, HDFGRTR, TRCAUXCTLR, 1),
1484 SR_FGT(SYS_TRCAUTHSTATUS, HDFGRTR, TRCAUTHSTATUS, 1),
1485 SR_FGT(SYS_TRCACATR(0), HDFGRTR, TRC, 1),
1486 SR_FGT(SYS_TRCACATR(1), HDFGRTR, TRC, 1),
1487 SR_FGT(SYS_TRCACATR(2), HDFGRTR, TRC, 1),
1488 SR_FGT(SYS_TRCACATR(3), HDFGRTR, TRC, 1),
1489 SR_FGT(SYS_TRCACATR(4), HDFGRTR, TRC, 1),
1490 SR_FGT(SYS_TRCACATR(5), HDFGRTR, TRC, 1),
1491 SR_FGT(SYS_TRCACATR(6), HDFGRTR, TRC, 1),
1492 SR_FGT(SYS_TRCACATR(7), HDFGRTR, TRC, 1),
1493 SR_FGT(SYS_TRCACATR(8), HDFGRTR, TRC, 1),
1494 SR_FGT(SYS_TRCACATR(9), HDFGRTR, TRC, 1),
1495 SR_FGT(SYS_TRCACATR(10), HDFGRTR, TRC, 1),
1496 SR_FGT(SYS_TRCACATR(11), HDFGRTR, TRC, 1),
1497 SR_FGT(SYS_TRCACATR(12), HDFGRTR, TRC, 1),
1498 SR_FGT(SYS_TRCACATR(13), HDFGRTR, TRC, 1),
1499 SR_FGT(SYS_TRCACATR(14), HDFGRTR, TRC, 1),
1500 SR_FGT(SYS_TRCACATR(15), HDFGRTR, TRC, 1),
1501 SR_FGT(SYS_TRCACVR(0), HDFGRTR, TRC, 1),
1502 SR_FGT(SYS_TRCACVR(1), HDFGRTR, TRC, 1),
1503 SR_FGT(SYS_TRCACVR(2), HDFGRTR, TRC, 1),
1504 SR_FGT(SYS_TRCACVR(3), HDFGRTR, TRC, 1),
1505 SR_FGT(SYS_TRCACVR(4), HDFGRTR, TRC, 1),
1506 SR_FGT(SYS_TRCACVR(5), HDFGRTR, TRC, 1),
1507 SR_FGT(SYS_TRCACVR(6), HDFGRTR, TRC, 1),
1508 SR_FGT(SYS_TRCACVR(7), HDFGRTR, TRC, 1),
1509 SR_FGT(SYS_TRCACVR(8), HDFGRTR, TRC, 1),
1510 SR_FGT(SYS_TRCACVR(9), HDFGRTR, TRC, 1),
1511 SR_FGT(SYS_TRCACVR(10), HDFGRTR, TRC, 1),
1512 SR_FGT(SYS_TRCACVR(11), HDFGRTR, TRC, 1),
1513 SR_FGT(SYS_TRCACVR(12), HDFGRTR, TRC, 1),
1514 SR_FGT(SYS_TRCACVR(13), HDFGRTR, TRC, 1),
1515 SR_FGT(SYS_TRCACVR(14), HDFGRTR, TRC, 1),
1516 SR_FGT(SYS_TRCACVR(15), HDFGRTR, TRC, 1),
1517 SR_FGT(SYS_TRCBBCTLR, HDFGRTR, TRC, 1),
1518 SR_FGT(SYS_TRCCCCTLR, HDFGRTR, TRC, 1),
1519 SR_FGT(SYS_TRCCIDCCTLR0, HDFGRTR, TRC, 1),
1520 SR_FGT(SYS_TRCCIDCCTLR1, HDFGRTR, TRC, 1),
1521 SR_FGT(SYS_TRCCIDCVR(0), HDFGRTR, TRC, 1),
1522 SR_FGT(SYS_TRCCIDCVR(1), HDFGRTR, TRC, 1),
1523 SR_FGT(SYS_TRCCIDCVR(2), HDFGRTR, TRC, 1),
1524 SR_FGT(SYS_TRCCIDCVR(3), HDFGRTR, TRC, 1),
1525 SR_FGT(SYS_TRCCIDCVR(4), HDFGRTR, TRC, 1),
1526 SR_FGT(SYS_TRCCIDCVR(5), HDFGRTR, TRC, 1),
1527 SR_FGT(SYS_TRCCIDCVR(6), HDFGRTR, TRC, 1),
1528 SR_FGT(SYS_TRCCIDCVR(7), HDFGRTR, TRC, 1),
1529 SR_FGT(SYS_TRCCNTCTLR(0), HDFGRTR, TRC, 1),
1530 SR_FGT(SYS_TRCCNTCTLR(1), HDFGRTR, TRC, 1),
1531 SR_FGT(SYS_TRCCNTCTLR(2), HDFGRTR, TRC, 1),
1532 SR_FGT(SYS_TRCCNTCTLR(3), HDFGRTR, TRC, 1),
1533 SR_FGT(SYS_TRCCNTRLDVR(0), HDFGRTR, TRC, 1),
1534 SR_FGT(SYS_TRCCNTRLDVR(1), HDFGRTR, TRC, 1),
1535 SR_FGT(SYS_TRCCNTRLDVR(2), HDFGRTR, TRC, 1),
1536 SR_FGT(SYS_TRCCNTRLDVR(3), HDFGRTR, TRC, 1),
1537 SR_FGT(SYS_TRCCONFIGR, HDFGRTR, TRC, 1),
1538 SR_FGT(SYS_TRCEVENTCTL0R, HDFGRTR, TRC, 1),
1539 SR_FGT(SYS_TRCEVENTCTL1R, HDFGRTR, TRC, 1),
1540 SR_FGT(SYS_TRCEXTINSELR(0), HDFGRTR, TRC, 1),
1541 SR_FGT(SYS_TRCEXTINSELR(1), HDFGRTR, TRC, 1),
1542 SR_FGT(SYS_TRCEXTINSELR(2), HDFGRTR, TRC, 1),
1543 SR_FGT(SYS_TRCEXTINSELR(3), HDFGRTR, TRC, 1),
1544 SR_FGT(SYS_TRCQCTLR, HDFGRTR, TRC, 1),
1545 SR_FGT(SYS_TRCRSCTLR(2), HDFGRTR, TRC, 1),
1546 SR_FGT(SYS_TRCRSCTLR(3), HDFGRTR, TRC, 1),
1547 SR_FGT(SYS_TRCRSCTLR(4), HDFGRTR, TRC, 1),
1548 SR_FGT(SYS_TRCRSCTLR(5), HDFGRTR, TRC, 1),
1549 SR_FGT(SYS_TRCRSCTLR(6), HDFGRTR, TRC, 1),
1550 SR_FGT(SYS_TRCRSCTLR(7), HDFGRTR, TRC, 1),
1551 SR_FGT(SYS_TRCRSCTLR(8), HDFGRTR, TRC, 1),
1552 SR_FGT(SYS_TRCRSCTLR(9), HDFGRTR, TRC, 1),
1553 SR_FGT(SYS_TRCRSCTLR(10), HDFGRTR, TRC, 1),
1554 SR_FGT(SYS_TRCRSCTLR(11), HDFGRTR, TRC, 1),
1555 SR_FGT(SYS_TRCRSCTLR(12), HDFGRTR, TRC, 1),
1556 SR_FGT(SYS_TRCRSCTLR(13), HDFGRTR, TRC, 1),
1557 SR_FGT(SYS_TRCRSCTLR(14), HDFGRTR, TRC, 1),
1558 SR_FGT(SYS_TRCRSCTLR(15), HDFGRTR, TRC, 1),
1559 SR_FGT(SYS_TRCRSCTLR(16), HDFGRTR, TRC, 1),
1560 SR_FGT(SYS_TRCRSCTLR(17), HDFGRTR, TRC, 1),
1561 SR_FGT(SYS_TRCRSCTLR(18), HDFGRTR, TRC, 1),
1562 SR_FGT(SYS_TRCRSCTLR(19), HDFGRTR, TRC, 1),
1563 SR_FGT(SYS_TRCRSCTLR(20), HDFGRTR, TRC, 1),
1564 SR_FGT(SYS_TRCRSCTLR(21), HDFGRTR, TRC, 1),
1565 SR_FGT(SYS_TRCRSCTLR(22), HDFGRTR, TRC, 1),
1566 SR_FGT(SYS_TRCRSCTLR(23), HDFGRTR, TRC, 1),
1567 SR_FGT(SYS_TRCRSCTLR(24), HDFGRTR, TRC, 1),
1568 SR_FGT(SYS_TRCRSCTLR(25), HDFGRTR, TRC, 1),
1569 SR_FGT(SYS_TRCRSCTLR(26), HDFGRTR, TRC, 1),
1570 SR_FGT(SYS_TRCRSCTLR(27), HDFGRTR, TRC, 1),
1571 SR_FGT(SYS_TRCRSCTLR(28), HDFGRTR, TRC, 1),
1572 SR_FGT(SYS_TRCRSCTLR(29), HDFGRTR, TRC, 1),
1573 SR_FGT(SYS_TRCRSCTLR(30), HDFGRTR, TRC, 1),
1574 SR_FGT(SYS_TRCRSCTLR(31), HDFGRTR, TRC, 1),
1575 SR_FGT(SYS_TRCRSR, HDFGRTR, TRC, 1),
1576 SR_FGT(SYS_TRCSEQEVR(0), HDFGRTR, TRC, 1),
1577 SR_FGT(SYS_TRCSEQEVR(1), HDFGRTR, TRC, 1),
1578 SR_FGT(SYS_TRCSEQEVR(2), HDFGRTR, TRC, 1),
1579 SR_FGT(SYS_TRCSEQRSTEVR, HDFGRTR, TRC, 1),
1580 SR_FGT(SYS_TRCSSCCR(0), HDFGRTR, TRC, 1),
1581 SR_FGT(SYS_TRCSSCCR(1), HDFGRTR, TRC, 1),
1582 SR_FGT(SYS_TRCSSCCR(2), HDFGRTR, TRC, 1),
1583 SR_FGT(SYS_TRCSSCCR(3), HDFGRTR, TRC, 1),
1584 SR_FGT(SYS_TRCSSCCR(4), HDFGRTR, TRC, 1),
1585 SR_FGT(SYS_TRCSSCCR(5), HDFGRTR, TRC, 1),
1586 SR_FGT(SYS_TRCSSCCR(6), HDFGRTR, TRC, 1),
1587 SR_FGT(SYS_TRCSSCCR(7), HDFGRTR, TRC, 1),
1588 SR_FGT(SYS_TRCSSPCICR(0), HDFGRTR, TRC, 1),
1589 SR_FGT(SYS_TRCSSPCICR(1), HDFGRTR, TRC, 1),
1590 SR_FGT(SYS_TRCSSPCICR(2), HDFGRTR, TRC, 1),
1591 SR_FGT(SYS_TRCSSPCICR(3), HDFGRTR, TRC, 1),
1592 SR_FGT(SYS_TRCSSPCICR(4), HDFGRTR, TRC, 1),
1593 SR_FGT(SYS_TRCSSPCICR(5), HDFGRTR, TRC, 1),
1594 SR_FGT(SYS_TRCSSPCICR(6), HDFGRTR, TRC, 1),
1595 SR_FGT(SYS_TRCSSPCICR(7), HDFGRTR, TRC, 1),
1596 SR_FGT(SYS_TRCSTALLCTLR, HDFGRTR, TRC, 1),
1597 SR_FGT(SYS_TRCSYNCPR, HDFGRTR, TRC, 1),
1598 SR_FGT(SYS_TRCTRACEIDR, HDFGRTR, TRC, 1),
1599 SR_FGT(SYS_TRCTSCTLR, HDFGRTR, TRC, 1),
1600 SR_FGT(SYS_TRCVIIECTLR, HDFGRTR, TRC, 1),
1601 SR_FGT(SYS_TRCVIPCSSCTLR, HDFGRTR, TRC, 1),
1602 SR_FGT(SYS_TRCVISSCTLR, HDFGRTR, TRC, 1),
1603 SR_FGT(SYS_TRCVMIDCCTLR0, HDFGRTR, TRC, 1),
1604 SR_FGT(SYS_TRCVMIDCCTLR1, HDFGRTR, TRC, 1),
1605 SR_FGT(SYS_TRCVMIDCVR(0), HDFGRTR, TRC, 1),
1606 SR_FGT(SYS_TRCVMIDCVR(1), HDFGRTR, TRC, 1),
1607 SR_FGT(SYS_TRCVMIDCVR(2), HDFGRTR, TRC, 1),
1608 SR_FGT(SYS_TRCVMIDCVR(3), HDFGRTR, TRC, 1),
1609 SR_FGT(SYS_TRCVMIDCVR(4), HDFGRTR, TRC, 1),
1610 SR_FGT(SYS_TRCVMIDCVR(5), HDFGRTR, TRC, 1),
1611 SR_FGT(SYS_TRCVMIDCVR(6), HDFGRTR, TRC, 1),
1612 SR_FGT(SYS_TRCVMIDCVR(7), HDFGRTR, TRC, 1),
1613 SR_FGT(SYS_PMSLATFR_EL1, HDFGRTR, PMSLATFR_EL1, 1),
1614 SR_FGT(SYS_PMSIRR_EL1, HDFGRTR, PMSIRR_EL1, 1),
1615 SR_FGT(SYS_PMSIDR_EL1, HDFGRTR, PMSIDR_EL1, 1),
1616 SR_FGT(SYS_PMSICR_EL1, HDFGRTR, PMSICR_EL1, 1),
1617 SR_FGT(SYS_PMSFCR_EL1, HDFGRTR, PMSFCR_EL1, 1),
1618 SR_FGT(SYS_PMSEVFR_EL1, HDFGRTR, PMSEVFR_EL1, 1),
1619 SR_FGT(SYS_PMSCR_EL1, HDFGRTR, PMSCR_EL1, 1),
1620 SR_FGT(SYS_PMBSR_EL1, HDFGRTR, PMBSR_EL1, 1),
1621 SR_FGT(SYS_PMBPTR_EL1, HDFGRTR, PMBPTR_EL1, 1),
1622 SR_FGT(SYS_PMBLIMITR_EL1, HDFGRTR, PMBLIMITR_EL1, 1),
1623 SR_FGT(SYS_PMMIR_EL1, HDFGRTR, PMMIR_EL1, 1),
1624 SR_FGT(SYS_PMSELR_EL0, HDFGRTR, PMSELR_EL0, 1),
1625 SR_FGT(SYS_PMOVSCLR_EL0, HDFGRTR, PMOVS, 1),
1626 SR_FGT(SYS_PMOVSSET_EL0, HDFGRTR, PMOVS, 1),
1627 SR_FGT(SYS_PMINTENCLR_EL1, HDFGRTR, PMINTEN, 1),
1628 SR_FGT(SYS_PMINTENSET_EL1, HDFGRTR, PMINTEN, 1),
1629 SR_FGT(SYS_PMCNTENCLR_EL0, HDFGRTR, PMCNTEN, 1),
1630 SR_FGT(SYS_PMCNTENSET_EL0, HDFGRTR, PMCNTEN, 1),
1631 SR_FGT(SYS_PMCCNTR_EL0, HDFGRTR, PMCCNTR_EL0, 1),
1632 SR_FGT(SYS_PMCCFILTR_EL0, HDFGRTR, PMCCFILTR_EL0, 1),
1633 SR_FGT(SYS_PMEVTYPERn_EL0(0), HDFGRTR, PMEVTYPERn_EL0, 1),
1634 SR_FGT(SYS_PMEVTYPERn_EL0(1), HDFGRTR, PMEVTYPERn_EL0, 1),
1635 SR_FGT(SYS_PMEVTYPERn_EL0(2), HDFGRTR, PMEVTYPERn_EL0, 1),
1636 SR_FGT(SYS_PMEVTYPERn_EL0(3), HDFGRTR, PMEVTYPERn_EL0, 1),
1637 SR_FGT(SYS_PMEVTYPERn_EL0(4), HDFGRTR, PMEVTYPERn_EL0, 1),
1638 SR_FGT(SYS_PMEVTYPERn_EL0(5), HDFGRTR, PMEVTYPERn_EL0, 1),
1639 SR_FGT(SYS_PMEVTYPERn_EL0(6), HDFGRTR, PMEVTYPERn_EL0, 1),
1640 SR_FGT(SYS_PMEVTYPERn_EL0(7), HDFGRTR, PMEVTYPERn_EL0, 1),
1641 SR_FGT(SYS_PMEVTYPERn_EL0(8), HDFGRTR, PMEVTYPERn_EL0, 1),
1642 SR_FGT(SYS_PMEVTYPERn_EL0(9), HDFGRTR, PMEVTYPERn_EL0, 1),
1643 SR_FGT(SYS_PMEVTYPERn_EL0(10), HDFGRTR, PMEVTYPERn_EL0, 1),
1644 SR_FGT(SYS_PMEVTYPERn_EL0(11), HDFGRTR, PMEVTYPERn_EL0, 1),
1645 SR_FGT(SYS_PMEVTYPERn_EL0(12), HDFGRTR, PMEVTYPERn_EL0, 1),
1646 SR_FGT(SYS_PMEVTYPERn_EL0(13), HDFGRTR, PMEVTYPERn_EL0, 1),
1647 SR_FGT(SYS_PMEVTYPERn_EL0(14), HDFGRTR, PMEVTYPERn_EL0, 1),
1648 SR_FGT(SYS_PMEVTYPERn_EL0(15), HDFGRTR, PMEVTYPERn_EL0, 1),
1649 SR_FGT(SYS_PMEVTYPERn_EL0(16), HDFGRTR, PMEVTYPERn_EL0, 1),
1650 SR_FGT(SYS_PMEVTYPERn_EL0(17), HDFGRTR, PMEVTYPERn_EL0, 1),
1651 SR_FGT(SYS_PMEVTYPERn_EL0(18), HDFGRTR, PMEVTYPERn_EL0, 1),
1652 SR_FGT(SYS_PMEVTYPERn_EL0(19), HDFGRTR, PMEVTYPERn_EL0, 1),
1653 SR_FGT(SYS_PMEVTYPERn_EL0(20), HDFGRTR, PMEVTYPERn_EL0, 1),
1654 SR_FGT(SYS_PMEVTYPERn_EL0(21), HDFGRTR, PMEVTYPERn_EL0, 1),
1655 SR_FGT(SYS_PMEVTYPERn_EL0(22), HDFGRTR, PMEVTYPERn_EL0, 1),
1656 SR_FGT(SYS_PMEVTYPERn_EL0(23), HDFGRTR, PMEVTYPERn_EL0, 1),
1657 SR_FGT(SYS_PMEVTYPERn_EL0(24), HDFGRTR, PMEVTYPERn_EL0, 1),
1658 SR_FGT(SYS_PMEVTYPERn_EL0(25), HDFGRTR, PMEVTYPERn_EL0, 1),
1659 SR_FGT(SYS_PMEVTYPERn_EL0(26), HDFGRTR, PMEVTYPERn_EL0, 1),
1660 SR_FGT(SYS_PMEVTYPERn_EL0(27), HDFGRTR, PMEVTYPERn_EL0, 1),
1661 SR_FGT(SYS_PMEVTYPERn_EL0(28), HDFGRTR, PMEVTYPERn_EL0, 1),
1662 SR_FGT(SYS_PMEVTYPERn_EL0(29), HDFGRTR, PMEVTYPERn_EL0, 1),
1663 SR_FGT(SYS_PMEVTYPERn_EL0(30), HDFGRTR, PMEVTYPERn_EL0, 1),
1664 SR_FGT(SYS_PMEVCNTRn_EL0(0), HDFGRTR, PMEVCNTRn_EL0, 1),
1665 SR_FGT(SYS_PMEVCNTRn_EL0(1), HDFGRTR, PMEVCNTRn_EL0, 1),
1666 SR_FGT(SYS_PMEVCNTRn_EL0(2), HDFGRTR, PMEVCNTRn_EL0, 1),
1667 SR_FGT(SYS_PMEVCNTRn_EL0(3), HDFGRTR, PMEVCNTRn_EL0, 1),
1668 SR_FGT(SYS_PMEVCNTRn_EL0(4), HDFGRTR, PMEVCNTRn_EL0, 1),
1669 SR_FGT(SYS_PMEVCNTRn_EL0(5), HDFGRTR, PMEVCNTRn_EL0, 1),
1670 SR_FGT(SYS_PMEVCNTRn_EL0(6), HDFGRTR, PMEVCNTRn_EL0, 1),
1671 SR_FGT(SYS_PMEVCNTRn_EL0(7), HDFGRTR, PMEVCNTRn_EL0, 1),
1672 SR_FGT(SYS_PMEVCNTRn_EL0(8), HDFGRTR, PMEVCNTRn_EL0, 1),
1673 SR_FGT(SYS_PMEVCNTRn_EL0(9), HDFGRTR, PMEVCNTRn_EL0, 1),
1674 SR_FGT(SYS_PMEVCNTRn_EL0(10), HDFGRTR, PMEVCNTRn_EL0, 1),
1675 SR_FGT(SYS_PMEVCNTRn_EL0(11), HDFGRTR, PMEVCNTRn_EL0, 1),
1676 SR_FGT(SYS_PMEVCNTRn_EL0(12), HDFGRTR, PMEVCNTRn_EL0, 1),
1677 SR_FGT(SYS_PMEVCNTRn_EL0(13), HDFGRTR, PMEVCNTRn_EL0, 1),
1678 SR_FGT(SYS_PMEVCNTRn_EL0(14), HDFGRTR, PMEVCNTRn_EL0, 1),
1679 SR_FGT(SYS_PMEVCNTRn_EL0(15), HDFGRTR, PMEVCNTRn_EL0, 1),
1680 SR_FGT(SYS_PMEVCNTRn_EL0(16), HDFGRTR, PMEVCNTRn_EL0, 1),
1681 SR_FGT(SYS_PMEVCNTRn_EL0(17), HDFGRTR, PMEVCNTRn_EL0, 1),
1682 SR_FGT(SYS_PMEVCNTRn_EL0(18), HDFGRTR, PMEVCNTRn_EL0, 1),
1683 SR_FGT(SYS_PMEVCNTRn_EL0(19), HDFGRTR, PMEVCNTRn_EL0, 1),
1684 SR_FGT(SYS_PMEVCNTRn_EL0(20), HDFGRTR, PMEVCNTRn_EL0, 1),
1685 SR_FGT(SYS_PMEVCNTRn_EL0(21), HDFGRTR, PMEVCNTRn_EL0, 1),
1686 SR_FGT(SYS_PMEVCNTRn_EL0(22), HDFGRTR, PMEVCNTRn_EL0, 1),
1687 SR_FGT(SYS_PMEVCNTRn_EL0(23), HDFGRTR, PMEVCNTRn_EL0, 1),
1688 SR_FGT(SYS_PMEVCNTRn_EL0(24), HDFGRTR, PMEVCNTRn_EL0, 1),
1689 SR_FGT(SYS_PMEVCNTRn_EL0(25), HDFGRTR, PMEVCNTRn_EL0, 1),
1690 SR_FGT(SYS_PMEVCNTRn_EL0(26), HDFGRTR, PMEVCNTRn_EL0, 1),
1691 SR_FGT(SYS_PMEVCNTRn_EL0(27), HDFGRTR, PMEVCNTRn_EL0, 1),
1692 SR_FGT(SYS_PMEVCNTRn_EL0(28), HDFGRTR, PMEVCNTRn_EL0, 1),
1693 SR_FGT(SYS_PMEVCNTRn_EL0(29), HDFGRTR, PMEVCNTRn_EL0, 1),
1694 SR_FGT(SYS_PMEVCNTRn_EL0(30), HDFGRTR, PMEVCNTRn_EL0, 1),
1695 SR_FGT(SYS_OSDLR_EL1, HDFGRTR, OSDLR_EL1, 1),
1696 SR_FGT(SYS_OSECCR_EL1, HDFGRTR, OSECCR_EL1, 1),
1697 SR_FGT(SYS_OSLSR_EL1, HDFGRTR, OSLSR_EL1, 1),
1698 SR_FGT(SYS_DBGPRCR_EL1, HDFGRTR, DBGPRCR_EL1, 1),
1699 SR_FGT(SYS_DBGAUTHSTATUS_EL1, HDFGRTR, DBGAUTHSTATUS_EL1, 1),
1700 SR_FGT(SYS_DBGCLAIMSET_EL1, HDFGRTR, DBGCLAIM, 1),
1701 SR_FGT(SYS_DBGCLAIMCLR_EL1, HDFGRTR, DBGCLAIM, 1),
1702 SR_FGT(SYS_MDSCR_EL1, HDFGRTR, MDSCR_EL1, 1),
1703 /*
1704 * The trap bits capture *64* debug registers per bit, but the
1705 * ARM ARM only describes the encoding for the first 16, and
1706 * we don't really support more than that anyway.
1707 */
1708 SR_FGT(SYS_DBGWVRn_EL1(0), HDFGRTR, DBGWVRn_EL1, 1),
1709 SR_FGT(SYS_DBGWVRn_EL1(1), HDFGRTR, DBGWVRn_EL1, 1),
1710 SR_FGT(SYS_DBGWVRn_EL1(2), HDFGRTR, DBGWVRn_EL1, 1),
1711 SR_FGT(SYS_DBGWVRn_EL1(3), HDFGRTR, DBGWVRn_EL1, 1),
1712 SR_FGT(SYS_DBGWVRn_EL1(4), HDFGRTR, DBGWVRn_EL1, 1),
1713 SR_FGT(SYS_DBGWVRn_EL1(5), HDFGRTR, DBGWVRn_EL1, 1),
1714 SR_FGT(SYS_DBGWVRn_EL1(6), HDFGRTR, DBGWVRn_EL1, 1),
1715 SR_FGT(SYS_DBGWVRn_EL1(7), HDFGRTR, DBGWVRn_EL1, 1),
1716 SR_FGT(SYS_DBGWVRn_EL1(8), HDFGRTR, DBGWVRn_EL1, 1),
1717 SR_FGT(SYS_DBGWVRn_EL1(9), HDFGRTR, DBGWVRn_EL1, 1),
1718 SR_FGT(SYS_DBGWVRn_EL1(10), HDFGRTR, DBGWVRn_EL1, 1),
1719 SR_FGT(SYS_DBGWVRn_EL1(11), HDFGRTR, DBGWVRn_EL1, 1),
1720 SR_FGT(SYS_DBGWVRn_EL1(12), HDFGRTR, DBGWVRn_EL1, 1),
1721 SR_FGT(SYS_DBGWVRn_EL1(13), HDFGRTR, DBGWVRn_EL1, 1),
1722 SR_FGT(SYS_DBGWVRn_EL1(14), HDFGRTR, DBGWVRn_EL1, 1),
1723 SR_FGT(SYS_DBGWVRn_EL1(15), HDFGRTR, DBGWVRn_EL1, 1),
1724 SR_FGT(SYS_DBGWCRn_EL1(0), HDFGRTR, DBGWCRn_EL1, 1),
1725 SR_FGT(SYS_DBGWCRn_EL1(1), HDFGRTR, DBGWCRn_EL1, 1),
1726 SR_FGT(SYS_DBGWCRn_EL1(2), HDFGRTR, DBGWCRn_EL1, 1),
1727 SR_FGT(SYS_DBGWCRn_EL1(3), HDFGRTR, DBGWCRn_EL1, 1),
1728 SR_FGT(SYS_DBGWCRn_EL1(4), HDFGRTR, DBGWCRn_EL1, 1),
1729 SR_FGT(SYS_DBGWCRn_EL1(5), HDFGRTR, DBGWCRn_EL1, 1),
1730 SR_FGT(SYS_DBGWCRn_EL1(6), HDFGRTR, DBGWCRn_EL1, 1),
1731 SR_FGT(SYS_DBGWCRn_EL1(7), HDFGRTR, DBGWCRn_EL1, 1),
1732 SR_FGT(SYS_DBGWCRn_EL1(8), HDFGRTR, DBGWCRn_EL1, 1),
1733 SR_FGT(SYS_DBGWCRn_EL1(9), HDFGRTR, DBGWCRn_EL1, 1),
1734 SR_FGT(SYS_DBGWCRn_EL1(10), HDFGRTR, DBGWCRn_EL1, 1),
1735 SR_FGT(SYS_DBGWCRn_EL1(11), HDFGRTR, DBGWCRn_EL1, 1),
1736 SR_FGT(SYS_DBGWCRn_EL1(12), HDFGRTR, DBGWCRn_EL1, 1),
1737 SR_FGT(SYS_DBGWCRn_EL1(13), HDFGRTR, DBGWCRn_EL1, 1),
1738 SR_FGT(SYS_DBGWCRn_EL1(14), HDFGRTR, DBGWCRn_EL1, 1),
1739 SR_FGT(SYS_DBGWCRn_EL1(15), HDFGRTR, DBGWCRn_EL1, 1),
1740 SR_FGT(SYS_DBGBVRn_EL1(0), HDFGRTR, DBGBVRn_EL1, 1),
1741 SR_FGT(SYS_DBGBVRn_EL1(1), HDFGRTR, DBGBVRn_EL1, 1),
1742 SR_FGT(SYS_DBGBVRn_EL1(2), HDFGRTR, DBGBVRn_EL1, 1),
1743 SR_FGT(SYS_DBGBVRn_EL1(3), HDFGRTR, DBGBVRn_EL1, 1),
1744 SR_FGT(SYS_DBGBVRn_EL1(4), HDFGRTR, DBGBVRn_EL1, 1),
1745 SR_FGT(SYS_DBGBVRn_EL1(5), HDFGRTR, DBGBVRn_EL1, 1),
1746 SR_FGT(SYS_DBGBVRn_EL1(6), HDFGRTR, DBGBVRn_EL1, 1),
1747 SR_FGT(SYS_DBGBVRn_EL1(7), HDFGRTR, DBGBVRn_EL1, 1),
1748 SR_FGT(SYS_DBGBVRn_EL1(8), HDFGRTR, DBGBVRn_EL1, 1),
1749 SR_FGT(SYS_DBGBVRn_EL1(9), HDFGRTR, DBGBVRn_EL1, 1),
1750 SR_FGT(SYS_DBGBVRn_EL1(10), HDFGRTR, DBGBVRn_EL1, 1),
1751 SR_FGT(SYS_DBGBVRn_EL1(11), HDFGRTR, DBGBVRn_EL1, 1),
1752 SR_FGT(SYS_DBGBVRn_EL1(12), HDFGRTR, DBGBVRn_EL1, 1),
1753 SR_FGT(SYS_DBGBVRn_EL1(13), HDFGRTR, DBGBVRn_EL1, 1),
1754 SR_FGT(SYS_DBGBVRn_EL1(14), HDFGRTR, DBGBVRn_EL1, 1),
1755 SR_FGT(SYS_DBGBVRn_EL1(15), HDFGRTR, DBGBVRn_EL1, 1),
1756 SR_FGT(SYS_DBGBCRn_EL1(0), HDFGRTR, DBGBCRn_EL1, 1),
1757 SR_FGT(SYS_DBGBCRn_EL1(1), HDFGRTR, DBGBCRn_EL1, 1),
1758 SR_FGT(SYS_DBGBCRn_EL1(2), HDFGRTR, DBGBCRn_EL1, 1),
1759 SR_FGT(SYS_DBGBCRn_EL1(3), HDFGRTR, DBGBCRn_EL1, 1),
1760 SR_FGT(SYS_DBGBCRn_EL1(4), HDFGRTR, DBGBCRn_EL1, 1),
1761 SR_FGT(SYS_DBGBCRn_EL1(5), HDFGRTR, DBGBCRn_EL1, 1),
1762 SR_FGT(SYS_DBGBCRn_EL1(6), HDFGRTR, DBGBCRn_EL1, 1),
1763 SR_FGT(SYS_DBGBCRn_EL1(7), HDFGRTR, DBGBCRn_EL1, 1),
1764 SR_FGT(SYS_DBGBCRn_EL1(8), HDFGRTR, DBGBCRn_EL1, 1),
1765 SR_FGT(SYS_DBGBCRn_EL1(9), HDFGRTR, DBGBCRn_EL1, 1),
1766 SR_FGT(SYS_DBGBCRn_EL1(10), HDFGRTR, DBGBCRn_EL1, 1),
1767 SR_FGT(SYS_DBGBCRn_EL1(11), HDFGRTR, DBGBCRn_EL1, 1),
1768 SR_FGT(SYS_DBGBCRn_EL1(12), HDFGRTR, DBGBCRn_EL1, 1),
1769 SR_FGT(SYS_DBGBCRn_EL1(13), HDFGRTR, DBGBCRn_EL1, 1),
1770 SR_FGT(SYS_DBGBCRn_EL1(14), HDFGRTR, DBGBCRn_EL1, 1),
1771 SR_FGT(SYS_DBGBCRn_EL1(15), HDFGRTR, DBGBCRn_EL1, 1),
1772 /*
1773 * HDFGWTR_EL2
1774 *
1775 * Although HDFGRTR_EL2 and HDFGWTR_EL2 registers largely
1776 * overlap in their bit assignment, there are a number of bits
1777 * that are RES0 on one side, and an actual trap bit on the
1778 * other. The policy chosen here is to describe all the
1779 * read-side mappings, and only the write-side mappings that
1780 * differ from the read side, and the trap handler will pick
1781 * the correct shadow register based on the access type.
1782 */
1783 SR_FGT(SYS_TRFCR_EL1, HDFGWTR, TRFCR_EL1, 1),
1784 SR_FGT(SYS_TRCOSLAR, HDFGWTR, TRCOSLAR, 1),
1785 SR_FGT(SYS_PMCR_EL0, HDFGWTR, PMCR_EL0, 1),
1786 SR_FGT(SYS_PMSWINC_EL0, HDFGWTR, PMSWINC_EL0, 1),
1787 SR_FGT(SYS_OSLAR_EL1, HDFGWTR, OSLAR_EL1, 1),
1788 /*
1789 * HAFGRTR_EL2
1790 */
1791 SR_FGT(SYS_AMEVTYPER1_EL0(15), HAFGRTR, AMEVTYPER115_EL0, 1),
1792 SR_FGT(SYS_AMEVTYPER1_EL0(14), HAFGRTR, AMEVTYPER114_EL0, 1),
1793 SR_FGT(SYS_AMEVTYPER1_EL0(13), HAFGRTR, AMEVTYPER113_EL0, 1),
1794 SR_FGT(SYS_AMEVTYPER1_EL0(12), HAFGRTR, AMEVTYPER112_EL0, 1),
1795 SR_FGT(SYS_AMEVTYPER1_EL0(11), HAFGRTR, AMEVTYPER111_EL0, 1),
1796 SR_FGT(SYS_AMEVTYPER1_EL0(10), HAFGRTR, AMEVTYPER110_EL0, 1),
1797 SR_FGT(SYS_AMEVTYPER1_EL0(9), HAFGRTR, AMEVTYPER19_EL0, 1),
1798 SR_FGT(SYS_AMEVTYPER1_EL0(8), HAFGRTR, AMEVTYPER18_EL0, 1),
1799 SR_FGT(SYS_AMEVTYPER1_EL0(7), HAFGRTR, AMEVTYPER17_EL0, 1),
1800 SR_FGT(SYS_AMEVTYPER1_EL0(6), HAFGRTR, AMEVTYPER16_EL0, 1),
1801 SR_FGT(SYS_AMEVTYPER1_EL0(5), HAFGRTR, AMEVTYPER15_EL0, 1),
1802 SR_FGT(SYS_AMEVTYPER1_EL0(4), HAFGRTR, AMEVTYPER14_EL0, 1),
1803 SR_FGT(SYS_AMEVTYPER1_EL0(3), HAFGRTR, AMEVTYPER13_EL0, 1),
1804 SR_FGT(SYS_AMEVTYPER1_EL0(2), HAFGRTR, AMEVTYPER12_EL0, 1),
1805 SR_FGT(SYS_AMEVTYPER1_EL0(1), HAFGRTR, AMEVTYPER11_EL0, 1),
1806 SR_FGT(SYS_AMEVTYPER1_EL0(0), HAFGRTR, AMEVTYPER10_EL0, 1),
1807 SR_FGT(SYS_AMEVCNTR1_EL0(15), HAFGRTR, AMEVCNTR115_EL0, 1),
1808 SR_FGT(SYS_AMEVCNTR1_EL0(14), HAFGRTR, AMEVCNTR114_EL0, 1),
1809 SR_FGT(SYS_AMEVCNTR1_EL0(13), HAFGRTR, AMEVCNTR113_EL0, 1),
1810 SR_FGT(SYS_AMEVCNTR1_EL0(12), HAFGRTR, AMEVCNTR112_EL0, 1),
1811 SR_FGT(SYS_AMEVCNTR1_EL0(11), HAFGRTR, AMEVCNTR111_EL0, 1),
1812 SR_FGT(SYS_AMEVCNTR1_EL0(10), HAFGRTR, AMEVCNTR110_EL0, 1),
1813 SR_FGT(SYS_AMEVCNTR1_EL0(9), HAFGRTR, AMEVCNTR19_EL0, 1),
1814 SR_FGT(SYS_AMEVCNTR1_EL0(8), HAFGRTR, AMEVCNTR18_EL0, 1),
1815 SR_FGT(SYS_AMEVCNTR1_EL0(7), HAFGRTR, AMEVCNTR17_EL0, 1),
1816 SR_FGT(SYS_AMEVCNTR1_EL0(6), HAFGRTR, AMEVCNTR16_EL0, 1),
1817 SR_FGT(SYS_AMEVCNTR1_EL0(5), HAFGRTR, AMEVCNTR15_EL0, 1),
1818 SR_FGT(SYS_AMEVCNTR1_EL0(4), HAFGRTR, AMEVCNTR14_EL0, 1),
1819 SR_FGT(SYS_AMEVCNTR1_EL0(3), HAFGRTR, AMEVCNTR13_EL0, 1),
1820 SR_FGT(SYS_AMEVCNTR1_EL0(2), HAFGRTR, AMEVCNTR12_EL0, 1),
1821 SR_FGT(SYS_AMEVCNTR1_EL0(1), HAFGRTR, AMEVCNTR11_EL0, 1),
1822 SR_FGT(SYS_AMEVCNTR1_EL0(0), HAFGRTR, AMEVCNTR10_EL0, 1),
1823 SR_FGT(SYS_AMCNTENCLR1_EL0, HAFGRTR, AMCNTEN1, 1),
1824 SR_FGT(SYS_AMCNTENSET1_EL0, HAFGRTR, AMCNTEN1, 1),
1825 SR_FGT(SYS_AMCNTENCLR0_EL0, HAFGRTR, AMCNTEN0, 1),
1826 SR_FGT(SYS_AMCNTENSET0_EL0, HAFGRTR, AMCNTEN0, 1),
1827 SR_FGT(SYS_AMEVCNTR0_EL0(3), HAFGRTR, AMEVCNTR03_EL0, 1),
1828 SR_FGT(SYS_AMEVCNTR0_EL0(2), HAFGRTR, AMEVCNTR02_EL0, 1),
1829 SR_FGT(SYS_AMEVCNTR0_EL0(1), HAFGRTR, AMEVCNTR01_EL0, 1),
1830 SR_FGT(SYS_AMEVCNTR0_EL0(0), HAFGRTR, AMEVCNTR00_EL0, 1),
1831 };
1832
1833 static union trap_config get_trap_config(u32 sysreg)
1834 {
1835 return (union trap_config) {
1836 .val = xa_to_value(xa_load(&sr_forward_xa, sysreg)),
1837 };
1838 }
1839
1840 static __init void print_nv_trap_error(const struct encoding_to_trap_config *tc,
1841 const char *type, int err)
1842 {
1843 kvm_err("%s line %d encoding range "
1844 "(%d, %d, %d, %d, %d) - (%d, %d, %d, %d, %d) (err=%d)\n",
1845 type, tc->line,
1846 sys_reg_Op0(tc->encoding), sys_reg_Op1(tc->encoding),
1847 sys_reg_CRn(tc->encoding), sys_reg_CRm(tc->encoding),
1848 sys_reg_Op2(tc->encoding),
1849 sys_reg_Op0(tc->end), sys_reg_Op1(tc->end),
1850 sys_reg_CRn(tc->end), sys_reg_CRm(tc->end),
1851 sys_reg_Op2(tc->end),
1852 err);
1853 }
1854
1855 static u32 encoding_next(u32 encoding)
1856 {
1857 u8 op0, op1, crn, crm, op2;
1858
1859 op0 = sys_reg_Op0(encoding);
1860 op1 = sys_reg_Op1(encoding);
1861 crn = sys_reg_CRn(encoding);
1862 crm = sys_reg_CRm(encoding);
1863 op2 = sys_reg_Op2(encoding);
1864
1865 if (op2 < Op2_mask)
1866 return sys_reg(op0, op1, crn, crm, op2 + 1);
1867 if (crm < CRm_mask)
1868 return sys_reg(op0, op1, crn, crm + 1, 0);
1869 if (crn < CRn_mask)
1870 return sys_reg(op0, op1, crn + 1, 0, 0);
1871 if (op1 < Op1_mask)
1872 return sys_reg(op0, op1 + 1, 0, 0, 0);
1873
1874 return sys_reg(op0 + 1, 0, 0, 0, 0);
1875 }
1876
1877 int __init populate_nv_trap_config(void)
1878 {
1879 int ret = 0;
1880
1881 BUILD_BUG_ON(sizeof(union trap_config) != sizeof(void *));
1882 BUILD_BUG_ON(__NR_CGT_GROUP_IDS__ > BIT(TC_CGT_BITS));
1883 BUILD_BUG_ON(__NR_FGT_GROUP_IDS__ > BIT(TC_FGT_BITS));
1884 BUILD_BUG_ON(__NR_FG_FILTER_IDS__ > BIT(TC_FGF_BITS));
1885
1886 for (int i = 0; i < ARRAY_SIZE(encoding_to_cgt); i++) {
1887 const struct encoding_to_trap_config *cgt = &encoding_to_cgt[i];
1888 void *prev;
1889
1890 if (cgt->tc.val & BIT(63)) {
1891 kvm_err("CGT[%d] has MBZ bit set\n", i);
1892 ret = -EINVAL;
1893 }
1894
1895 for (u32 enc = cgt->encoding; enc <= cgt->end; enc = encoding_next(enc)) {
1896 prev = xa_store(&sr_forward_xa, enc,
1897 xa_mk_value(cgt->tc.val), GFP_KERNEL);
1898 if (prev && !xa_is_err(prev)) {
1899 ret = -EINVAL;
1900 print_nv_trap_error(cgt, "Duplicate CGT", ret);
1901 }
1902
1903 if (xa_is_err(prev)) {
1904 ret = xa_err(prev);
1905 print_nv_trap_error(cgt, "Failed CGT insertion", ret);
1906 }
1907 }
1908 }
1909
1910 kvm_info("nv: %ld coarse grained trap handlers\n",
1911 ARRAY_SIZE(encoding_to_cgt));
1912
1913 if (!cpus_have_final_cap(ARM64_HAS_FGT))
1914 goto check_mcb;
1915
1916 for (int i = 0; i < ARRAY_SIZE(encoding_to_fgt); i++) {
1917 const struct encoding_to_trap_config *fgt = &encoding_to_fgt[i];
1918 union trap_config tc;
1919 void *prev;
1920
1921 if (fgt->tc.fgt >= __NR_FGT_GROUP_IDS__) {
1922 ret = -EINVAL;
1923 print_nv_trap_error(fgt, "Invalid FGT", ret);
1924 }
1925
1926 tc = get_trap_config(fgt->encoding);
1927
1928 if (tc.fgt) {
1929 ret = -EINVAL;
1930 print_nv_trap_error(fgt, "Duplicate FGT", ret);
1931 }
1932
1933 tc.val |= fgt->tc.val;
1934 prev = xa_store(&sr_forward_xa, fgt->encoding,
1935 xa_mk_value(tc.val), GFP_KERNEL);
1936
1937 if (xa_is_err(prev)) {
1938 ret = xa_err(prev);
1939 print_nv_trap_error(fgt, "Failed FGT insertion", ret);
1940 }
1941 }
1942
1943 kvm_info("nv: %ld fine grained trap handlers\n",
1944 ARRAY_SIZE(encoding_to_fgt));
1945
1946 check_mcb:
1947 for (int id = __MULTIPLE_CONTROL_BITS__; id < __COMPLEX_CONDITIONS__; id++) {
1948 const enum cgt_group_id *cgids;
1949
1950 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__];
1951
1952 for (int i = 0; cgids[i] != __RESERVED__; i++) {
1953 if (cgids[i] >= __MULTIPLE_CONTROL_BITS__) {
1954 kvm_err("Recursive MCB %d/%d\n", id, cgids[i]);
1955 ret = -EINVAL;
1956 }
1957 }
1958 }
1959
1960 if (ret)
1961 xa_destroy(&sr_forward_xa);
1962
1963 return ret;
1964 }
1965
1966 int __init populate_sysreg_config(const struct sys_reg_desc *sr,
1967 unsigned int idx)
1968 {
1969 union trap_config tc;
1970 u32 encoding;
1971 void *ret;
1972
1973 /*
1974 * 0 is a valid value for the index, but not for the storage.
1975 * We'll store (idx+1), so check against an offset'd limit.
1976 */
1977 if (idx >= (BIT(TC_SRI_BITS) - 1)) {
1978 kvm_err("sysreg %s (%d) out of range\n", sr->name, idx);
1979 return -EINVAL;
1980 }
1981
1982 encoding = sys_reg(sr->Op0, sr->Op1, sr->CRn, sr->CRm, sr->Op2);
1983 tc = get_trap_config(encoding);
1984
1985 if (tc.sri) {
1986 kvm_err("sysreg %s (%d) duplicate entry (%d)\n",
1987 sr->name, idx - 1, tc.sri);
1988 return -EINVAL;
1989 }
1990
1991 tc.sri = idx + 1;
1992 ret = xa_store(&sr_forward_xa, encoding,
1993 xa_mk_value(tc.val), GFP_KERNEL);
1994
1995 return xa_err(ret);
1996 }
1997
1998 static enum trap_behaviour get_behaviour(struct kvm_vcpu *vcpu,
1999 const struct trap_bits *tb)
2000 {
2001 enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY;
2002 u64 val;
2003
2004 val = __vcpu_sys_reg(vcpu, tb->index);
2005 if ((val & tb->mask) == tb->value)
2006 b |= tb->behaviour;
2007
2008 return b;
2009 }
2010
2011 static enum trap_behaviour __compute_trap_behaviour(struct kvm_vcpu *vcpu,
2012 const enum cgt_group_id id,
2013 enum trap_behaviour b)
2014 {
2015 switch (id) {
2016 const enum cgt_group_id *cgids;
2017
2018 case __RESERVED__ ... __MULTIPLE_CONTROL_BITS__ - 1:
2019 if (likely(id != __RESERVED__))
2020 b |= get_behaviour(vcpu, &coarse_trap_bits[id]);
2021 break;
2022 case __MULTIPLE_CONTROL_BITS__ ... __COMPLEX_CONDITIONS__ - 1:
2023 /* Yes, this is recursive. Don't do anything stupid. */
2024 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__];
2025 for (int i = 0; cgids[i] != __RESERVED__; i++)
2026 b |= __compute_trap_behaviour(vcpu, cgids[i], b);
2027 break;
2028 default:
2029 if (ARRAY_SIZE(ccc))
2030 b |= ccc[id - __COMPLEX_CONDITIONS__](vcpu);
2031 break;
2032 }
2033
2034 return b;
2035 }
2036
2037 static enum trap_behaviour compute_trap_behaviour(struct kvm_vcpu *vcpu,
2038 const union trap_config tc)
2039 {
2040 enum trap_behaviour b = BEHAVE_HANDLE_LOCALLY;
2041
2042 return __compute_trap_behaviour(vcpu, tc.cgt, b);
2043 }
2044
2045 static u64 kvm_get_sysreg_res0(struct kvm *kvm, enum vcpu_sysreg sr)
2046 {
2047 struct kvm_sysreg_masks *masks;
2048
2049 /* Only handle the VNCR-backed regs for now */
2050 if (sr < __VNCR_START__)
2051 return 0;
2052
2053 masks = kvm->arch.sysreg_masks;
2054
2055 return masks->mask[sr - __VNCR_START__].res0;
2056 }
2057
2058 static bool check_fgt_bit(struct kvm *kvm, bool is_read,
2059 u64 val, const union trap_config tc)
2060 {
2061 enum vcpu_sysreg sr;
2062
2063 if (tc.pol)
2064 return (val & BIT(tc.bit));
2065
2066 /*
2067 * FGTs with negative polarities are an absolute nightmare, as
2068 * we need to evaluate the bit in the light of the feature
2069 * that defines it. WTF were they thinking?
2070 *
2071 * So let's check if the bit has been earmarked as RES0, as
2072 * this indicates an unimplemented feature.
2073 */
2074 if (val & BIT(tc.bit))
2075 return false;
2076
2077 switch ((enum fgt_group_id)tc.fgt) {
2078 case HFGxTR_GROUP:
2079 sr = is_read ? HFGRTR_EL2 : HFGWTR_EL2;
2080 break;
2081
2082 case HDFGRTR_GROUP:
2083 sr = is_read ? HDFGRTR_EL2 : HDFGWTR_EL2;
2084 break;
2085
2086 case HAFGRTR_GROUP:
2087 sr = HAFGRTR_EL2;
2088 break;
2089
2090 case HFGITR_GROUP:
2091 sr = HFGITR_EL2;
2092 break;
2093
2094 default:
2095 WARN_ONCE(1, "Unhandled FGT group");
2096 return false;
2097 }
2098
2099 return !(kvm_get_sysreg_res0(kvm, sr) & BIT(tc.bit));
2100 }
2101
2102 bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *sr_index)
2103 {
2104 union trap_config tc;
2105 enum trap_behaviour b;
2106 bool is_read;
2107 u32 sysreg;
2108 u64 esr, val;
2109
2110 esr = kvm_vcpu_get_esr(vcpu);
2111 sysreg = esr_sys64_to_sysreg(esr);
2112 is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
2113
2114 tc = get_trap_config(sysreg);
2115
2116 /*
2117 * A value of 0 for the whole entry means that we know nothing
2118 * for this sysreg, and that it cannot be re-injected into the
2119 * nested hypervisor. In this situation, let's cut it short.
2120 */
2121 if (!tc.val)
2122 goto local;
2123
2124 /*
2125 * If a sysreg can be trapped using a FGT, first check whether we
2126 * trap for the purpose of forbidding the feature. In that case,
2127 * inject an UNDEF.
2128 */
2129 if (tc.fgt != __NO_FGT_GROUP__ &&
2130 (vcpu->kvm->arch.fgu[tc.fgt] & BIT(tc.bit))) {
2131 kvm_inject_undefined(vcpu);
2132 return true;
2133 }
2134
2135 /*
2136 * If we're not nesting, immediately return to the caller, with the
2137 * sysreg index, should we have it.
2138 */
2139 if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu))
2140 goto local;
2141
2142 switch ((enum fgt_group_id)tc.fgt) {
2143 case __NO_FGT_GROUP__:
2144 break;
2145
2146 case HFGxTR_GROUP:
2147 if (is_read)
2148 val = __vcpu_sys_reg(vcpu, HFGRTR_EL2);
2149 else
2150 val = __vcpu_sys_reg(vcpu, HFGWTR_EL2);
2151 break;
2152
2153 case HDFGRTR_GROUP:
2154 if (is_read)
2155 val = __vcpu_sys_reg(vcpu, HDFGRTR_EL2);
2156 else
2157 val = __vcpu_sys_reg(vcpu, HDFGWTR_EL2);
2158 break;
2159
2160 case HAFGRTR_GROUP:
2161 val = __vcpu_sys_reg(vcpu, HAFGRTR_EL2);
2162 break;
2163
2164 case HFGITR_GROUP:
2165 val = __vcpu_sys_reg(vcpu, HFGITR_EL2);
2166 switch (tc.fgf) {
2167 u64 tmp;
2168
2169 case __NO_FGF__:
2170 break;
2171
2172 case HCRX_FGTnXS:
2173 tmp = __vcpu_sys_reg(vcpu, HCRX_EL2);
2174 if (tmp & HCRX_EL2_FGTnXS)
2175 tc.fgt = __NO_FGT_GROUP__;
2176 }
2177 break;
2178
2179 case __NR_FGT_GROUP_IDS__:
2180 /* Something is really wrong, bail out */
2181 WARN_ONCE(1, "__NR_FGT_GROUP_IDS__");
2182 goto local;
2183 }
2184
2185 if (tc.fgt != __NO_FGT_GROUP__ && check_fgt_bit(vcpu->kvm, is_read,
2186 val, tc))
2187 goto inject;
2188
2189 b = compute_trap_behaviour(vcpu, tc);
2190
2191 if (((b & BEHAVE_FORWARD_READ) && is_read) ||
2192 ((b & BEHAVE_FORWARD_WRITE) && !is_read))
2193 goto inject;
2194
2195 local:
2196 if (!tc.sri) {
2197 struct sys_reg_params params;
2198
2199 params = esr_sys64_to_params(esr);
2200
2201 /*
2202 * Check for the IMPDEF range, as per DDI0487 J.a,
2203 * D18.3.2 Reserved encodings for IMPLEMENTATION
2204 * DEFINED registers.
2205 */
2206 if (!(params.Op0 == 3 && (params.CRn & 0b1011) == 0b1011))
2207 print_sys_reg_msg(¶ms,
2208 "Unsupported guest access at: %lx\n",
2209 *vcpu_pc(vcpu));
2210 kvm_inject_undefined(vcpu);
2211 return true;
2212 }
2213
2214 *sr_index = tc.sri - 1;
2215 return false;
2216
2217 inject:
2218 trace_kvm_forward_sysreg_trap(vcpu, sysreg, is_read);
2219
2220 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu));
2221 return true;
2222 }
2223
2224 static bool forward_traps(struct kvm_vcpu *vcpu, u64 control_bit)
2225 {
2226 bool control_bit_set;
2227
2228 if (!vcpu_has_nv(vcpu))
2229 return false;
2230
2231 control_bit_set = __vcpu_sys_reg(vcpu, HCR_EL2) & control_bit;
2232 if (!is_hyp_ctxt(vcpu) && control_bit_set) {
2233 kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu));
2234 return true;
2235 }
2236 return false;
2237 }
2238
2239 bool forward_smc_trap(struct kvm_vcpu *vcpu)
2240 {
2241 return forward_traps(vcpu, HCR_TSC);
2242 }
2243
2244 static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr)
2245 {
2246 u64 mode = spsr & PSR_MODE_MASK;
2247
2248 /*
2249 * Possible causes for an Illegal Exception Return from EL2:
2250 * - trying to return to EL3
2251 * - trying to return to an illegal M value
2252 * - trying to return to a 32bit EL
2253 * - trying to return to EL1 with HCR_EL2.TGE set
2254 */
2255 if (mode == PSR_MODE_EL3t || mode == PSR_MODE_EL3h ||
2256 mode == 0b00001 || (mode & BIT(1)) ||
2257 (spsr & PSR_MODE32_BIT) ||
2258 (vcpu_el2_tge_is_set(vcpu) && (mode == PSR_MODE_EL1t ||
2259 mode == PSR_MODE_EL1h))) {
2260 /*
2261 * The guest is playing with our nerves. Preserve EL, SP,
2262 * masks, flags from the existing PSTATE, and set IL.
2263 * The HW will then generate an Illegal State Exception
2264 * immediately after ERET.
2265 */
2266 spsr = *vcpu_cpsr(vcpu);
2267
2268 spsr &= (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT |
2269 PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT |
2270 PSR_MODE_MASK | PSR_MODE32_BIT);
2271 spsr |= PSR_IL_BIT;
2272 }
2273
2274 return spsr;
2275 }
2276
2277 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu)
2278 {
2279 u64 spsr, elr, esr;
2280
2281 /*
2282 * Forward this trap to the virtual EL2 if the virtual
2283 * HCR_EL2.NV bit is set and this is coming from !EL2.
2284 */
2285 if (forward_traps(vcpu, HCR_NV))
2286 return;
2287
2288 spsr = vcpu_read_sys_reg(vcpu, SPSR_EL2);
2289 spsr = kvm_check_illegal_exception_return(vcpu, spsr);
2290
2291 /* Check for an ERETAx */
2292 esr = kvm_vcpu_get_esr(vcpu);
2293 if (esr_iss_is_eretax(esr) && !kvm_auth_eretax(vcpu, &elr)) {
2294 /*
2295 * Oh no, ERETAx failed to authenticate.
2296 *
2297 * If we have FPACCOMBINE and we don't have a pending
2298 * Illegal Execution State exception (which has priority
2299 * over FPAC), deliver an exception right away.
2300 *
2301 * Otherwise, let the mangled ELR value trickle down the
2302 * ERET handling, and the guest will have a little surprise.
2303 */
2304 if (kvm_has_pauth(vcpu->kvm, FPACCOMBINE) && !(spsr & PSR_IL_BIT)) {
2305 esr &= ESR_ELx_ERET_ISS_ERETA;
2306 esr |= FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_FPAC);
2307 kvm_inject_nested_sync(vcpu, esr);
2308 return;
2309 }
2310 }
2311
2312 preempt_disable();
2313 kvm_arch_vcpu_put(vcpu);
2314
2315 if (!esr_iss_is_eretax(esr))
2316 elr = __vcpu_sys_reg(vcpu, ELR_EL2);
2317
2318 trace_kvm_nested_eret(vcpu, elr, spsr);
2319
2320 *vcpu_pc(vcpu) = elr;
2321 *vcpu_cpsr(vcpu) = spsr;
2322
2323 kvm_arch_vcpu_load(vcpu, smp_processor_id());
2324 preempt_enable();
2325 }
2326
2327 static void kvm_inject_el2_exception(struct kvm_vcpu *vcpu, u64 esr_el2,
2328 enum exception_type type)
2329 {
2330 trace_kvm_inject_nested_exception(vcpu, esr_el2, type);
2331
2332 switch (type) {
2333 case except_type_sync:
2334 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_SYNC);
2335 vcpu_write_sys_reg(vcpu, esr_el2, ESR_EL2);
2336 break;
2337 case except_type_irq:
2338 kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_IRQ);
2339 break;
2340 default:
2341 WARN_ONCE(1, "Unsupported EL2 exception injection %d\n", type);
2342 }
2343 }
2344
2345 /*
2346 * Emulate taking an exception to EL2.
2347 * See ARM ARM J8.1.2 AArch64.TakeException()
2348 */
2349 static int kvm_inject_nested(struct kvm_vcpu *vcpu, u64 esr_el2,
2350 enum exception_type type)
2351 {
2352 u64 pstate, mode;
2353 bool direct_inject;
2354
2355 if (!vcpu_has_nv(vcpu)) {
2356 kvm_err("Unexpected call to %s for the non-nesting configuration\n",
2357 __func__);
2358 return -EINVAL;
2359 }
2360
2361 /*
2362 * As for ERET, we can avoid doing too much on the injection path by
2363 * checking that we either took the exception from a VHE host
2364 * userspace or from vEL2. In these cases, there is no change in
2365 * translation regime (or anything else), so let's do as little as
2366 * possible.
2367 */
2368 pstate = *vcpu_cpsr(vcpu);
2369 mode = pstate & (PSR_MODE_MASK | PSR_MODE32_BIT);
2370
2371 direct_inject = (mode == PSR_MODE_EL0t &&
2372 vcpu_el2_e2h_is_set(vcpu) &&
2373 vcpu_el2_tge_is_set(vcpu));
2374 direct_inject |= (mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t);
2375
2376 if (direct_inject) {
2377 kvm_inject_el2_exception(vcpu, esr_el2, type);
2378 return 1;
2379 }
2380
2381 preempt_disable();
2382
2383 /*
2384 * We may have an exception or PC update in the EL0/EL1 context.
2385 * Commit it before entering EL2.
2386 */
2387 __kvm_adjust_pc(vcpu);
2388
2389 kvm_arch_vcpu_put(vcpu);
2390
2391 kvm_inject_el2_exception(vcpu, esr_el2, type);
2392
2393 /*
2394 * A hard requirement is that a switch between EL1 and EL2
2395 * contexts has to happen between a put/load, so that we can
2396 * pick the correct timer and interrupt configuration, among
2397 * other things.
2398 *
2399 * Make sure the exception actually took place before we load
2400 * the new context.
2401 */
2402 __kvm_adjust_pc(vcpu);
2403
2404 kvm_arch_vcpu_load(vcpu, smp_processor_id());
2405 preempt_enable();
2406
2407 return 1;
2408 }
2409
2410 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2)
2411 {
2412 return kvm_inject_nested(vcpu, esr_el2, except_type_sync);
2413 }
2414
2415 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu)
2416 {
2417 /*
2418 * Do not inject an irq if the:
2419 * - Current exception level is EL2, and
2420 * - virtual HCR_EL2.TGE == 0
2421 * - virtual HCR_EL2.IMO == 0
2422 *
2423 * See Table D1-17 "Physical interrupt target and masking when EL3 is
2424 * not implemented and EL2 is implemented" in ARM DDI 0487C.a.
2425 */
2426
2427 if (vcpu_is_el2(vcpu) && !vcpu_el2_tge_is_set(vcpu) &&
2428 !(__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_IMO))
2429 return 1;
2430
2431 /* esr_el2 value doesn't matter for exits due to irqs. */
2432 return kvm_inject_nested(vcpu, 0, except_type_irq);
2433 }
2434
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