1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/guest.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11 #include <linux/bits.h>
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/nospec.h>
15 #include <linux/kvm_host.h>
16 #include <linux/module.h>
17 #include <linux/stddef.h>
18 #include <linux/string.h>
19 #include <linux/vmalloc.h>
20 #include <linux/fs.h>
21 #include <kvm/arm_hypercalls.h>
22 #include <asm/cputype.h>
23 #include <linux/uaccess.h>
24 #include <asm/fpsimd.h>
25 #include <asm/kvm.h>
26 #include <asm/kvm_emulate.h>
27 #include <asm/kvm_nested.h>
28 #include <asm/sigcontext.h>
29
30 #include "trace.h"
31
32 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
33 KVM_GENERIC_VM_STATS()
34 };
35
36 const struct kvm_stats_header kvm_vm_stats_header = {
37 .name_size = KVM_STATS_NAME_SIZE,
38 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
39 .id_offset = sizeof(struct kvm_stats_header),
40 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
41 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
42 sizeof(kvm_vm_stats_desc),
43 };
44
45 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
46 KVM_GENERIC_VCPU_STATS(),
47 STATS_DESC_COUNTER(VCPU, hvc_exit_stat),
48 STATS_DESC_COUNTER(VCPU, wfe_exit_stat),
49 STATS_DESC_COUNTER(VCPU, wfi_exit_stat),
50 STATS_DESC_COUNTER(VCPU, mmio_exit_user),
51 STATS_DESC_COUNTER(VCPU, mmio_exit_kernel),
52 STATS_DESC_COUNTER(VCPU, signal_exits),
53 STATS_DESC_COUNTER(VCPU, exits)
54 };
55
56 const struct kvm_stats_header kvm_vcpu_stats_header = {
57 .name_size = KVM_STATS_NAME_SIZE,
58 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
59 .id_offset = sizeof(struct kvm_stats_header),
60 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
61 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
62 sizeof(kvm_vcpu_stats_desc),
63 };
64
65 static bool core_reg_offset_is_vreg(u64 off)
66 {
67 return off >= KVM_REG_ARM_CORE_REG(fp_regs.vregs) &&
68 off < KVM_REG_ARM_CORE_REG(fp_regs.fpsr);
69 }
70
71 static u64 core_reg_offset_from_id(u64 id)
72 {
73 return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
74 }
75
76 static int core_reg_size_from_offset(const struct kvm_vcpu *vcpu, u64 off)
77 {
78 int size;
79
80 switch (off) {
81 case KVM_REG_ARM_CORE_REG(regs.regs[0]) ...
82 KVM_REG_ARM_CORE_REG(regs.regs[30]):
83 case KVM_REG_ARM_CORE_REG(regs.sp):
84 case KVM_REG_ARM_CORE_REG(regs.pc):
85 case KVM_REG_ARM_CORE_REG(regs.pstate):
86 case KVM_REG_ARM_CORE_REG(sp_el1):
87 case KVM_REG_ARM_CORE_REG(elr_el1):
88 case KVM_REG_ARM_CORE_REG(spsr[0]) ...
89 KVM_REG_ARM_CORE_REG(spsr[KVM_NR_SPSR - 1]):
90 size = sizeof(__u64);
91 break;
92
93 case KVM_REG_ARM_CORE_REG(fp_regs.vregs[0]) ...
94 KVM_REG_ARM_CORE_REG(fp_regs.vregs[31]):
95 size = sizeof(__uint128_t);
96 break;
97
98 case KVM_REG_ARM_CORE_REG(fp_regs.fpsr):
99 case KVM_REG_ARM_CORE_REG(fp_regs.fpcr):
100 size = sizeof(__u32);
101 break;
102
103 default:
104 return -EINVAL;
105 }
106
107 if (!IS_ALIGNED(off, size / sizeof(__u32)))
108 return -EINVAL;
109
110 /*
111 * The KVM_REG_ARM64_SVE regs must be used instead of
112 * KVM_REG_ARM_CORE for accessing the FPSIMD V-registers on
113 * SVE-enabled vcpus:
114 */
115 if (vcpu_has_sve(vcpu) && core_reg_offset_is_vreg(off))
116 return -EINVAL;
117
118 return size;
119 }
120
121 static void *core_reg_addr(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
122 {
123 u64 off = core_reg_offset_from_id(reg->id);
124 int size = core_reg_size_from_offset(vcpu, off);
125
126 if (size < 0)
127 return NULL;
128
129 if (KVM_REG_SIZE(reg->id) != size)
130 return NULL;
131
132 switch (off) {
133 case KVM_REG_ARM_CORE_REG(regs.regs[0]) ...
134 KVM_REG_ARM_CORE_REG(regs.regs[30]):
135 off -= KVM_REG_ARM_CORE_REG(regs.regs[0]);
136 off /= 2;
137 return &vcpu->arch.ctxt.regs.regs[off];
138
139 case KVM_REG_ARM_CORE_REG(regs.sp):
140 return &vcpu->arch.ctxt.regs.sp;
141
142 case KVM_REG_ARM_CORE_REG(regs.pc):
143 return &vcpu->arch.ctxt.regs.pc;
144
145 case KVM_REG_ARM_CORE_REG(regs.pstate):
146 return &vcpu->arch.ctxt.regs.pstate;
147
148 case KVM_REG_ARM_CORE_REG(sp_el1):
149 return __ctxt_sys_reg(&vcpu->arch.ctxt, SP_EL1);
150
151 case KVM_REG_ARM_CORE_REG(elr_el1):
152 return __ctxt_sys_reg(&vcpu->arch.ctxt, ELR_EL1);
153
154 case KVM_REG_ARM_CORE_REG(spsr[KVM_SPSR_EL1]):
155 return __ctxt_sys_reg(&vcpu->arch.ctxt, SPSR_EL1);
156
157 case KVM_REG_ARM_CORE_REG(spsr[KVM_SPSR_ABT]):
158 return &vcpu->arch.ctxt.spsr_abt;
159
160 case KVM_REG_ARM_CORE_REG(spsr[KVM_SPSR_UND]):
161 return &vcpu->arch.ctxt.spsr_und;
162
163 case KVM_REG_ARM_CORE_REG(spsr[KVM_SPSR_IRQ]):
164 return &vcpu->arch.ctxt.spsr_irq;
165
166 case KVM_REG_ARM_CORE_REG(spsr[KVM_SPSR_FIQ]):
167 return &vcpu->arch.ctxt.spsr_fiq;
168
169 case KVM_REG_ARM_CORE_REG(fp_regs.vregs[0]) ...
170 KVM_REG_ARM_CORE_REG(fp_regs.vregs[31]):
171 off -= KVM_REG_ARM_CORE_REG(fp_regs.vregs[0]);
172 off /= 4;
173 return &vcpu->arch.ctxt.fp_regs.vregs[off];
174
175 case KVM_REG_ARM_CORE_REG(fp_regs.fpsr):
176 return &vcpu->arch.ctxt.fp_regs.fpsr;
177
178 case KVM_REG_ARM_CORE_REG(fp_regs.fpcr):
179 return &vcpu->arch.ctxt.fp_regs.fpcr;
180
181 default:
182 return NULL;
183 }
184 }
185
186 static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
187 {
188 /*
189 * Because the kvm_regs structure is a mix of 32, 64 and
190 * 128bit fields, we index it as if it was a 32bit
191 * array. Hence below, nr_regs is the number of entries, and
192 * off the index in the "array".
193 */
194 __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
195 int nr_regs = sizeof(struct kvm_regs) / sizeof(__u32);
196 void *addr;
197 u32 off;
198
199 /* Our ID is an index into the kvm_regs struct. */
200 off = core_reg_offset_from_id(reg->id);
201 if (off >= nr_regs ||
202 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
203 return -ENOENT;
204
205 addr = core_reg_addr(vcpu, reg);
206 if (!addr)
207 return -EINVAL;
208
209 if (copy_to_user(uaddr, addr, KVM_REG_SIZE(reg->id)))
210 return -EFAULT;
211
212 return 0;
213 }
214
215 static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
216 {
217 __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
218 int nr_regs = sizeof(struct kvm_regs) / sizeof(__u32);
219 __uint128_t tmp;
220 void *valp = &tmp, *addr;
221 u64 off;
222 int err = 0;
223
224 /* Our ID is an index into the kvm_regs struct. */
225 off = core_reg_offset_from_id(reg->id);
226 if (off >= nr_regs ||
227 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
228 return -ENOENT;
229
230 addr = core_reg_addr(vcpu, reg);
231 if (!addr)
232 return -EINVAL;
233
234 if (KVM_REG_SIZE(reg->id) > sizeof(tmp))
235 return -EINVAL;
236
237 if (copy_from_user(valp, uaddr, KVM_REG_SIZE(reg->id))) {
238 err = -EFAULT;
239 goto out;
240 }
241
242 if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {
243 u64 mode = (*(u64 *)valp) & PSR_AA32_MODE_MASK;
244 switch (mode) {
245 case PSR_AA32_MODE_USR:
246 if (!kvm_supports_32bit_el0())
247 return -EINVAL;
248 break;
249 case PSR_AA32_MODE_FIQ:
250 case PSR_AA32_MODE_IRQ:
251 case PSR_AA32_MODE_SVC:
252 case PSR_AA32_MODE_ABT:
253 case PSR_AA32_MODE_UND:
254 case PSR_AA32_MODE_SYS:
255 if (!vcpu_el1_is_32bit(vcpu))
256 return -EINVAL;
257 break;
258 case PSR_MODE_EL2h:
259 case PSR_MODE_EL2t:
260 if (!vcpu_has_nv(vcpu))
261 return -EINVAL;
262 fallthrough;
263 case PSR_MODE_EL0t:
264 case PSR_MODE_EL1t:
265 case PSR_MODE_EL1h:
266 if (vcpu_el1_is_32bit(vcpu))
267 return -EINVAL;
268 break;
269 default:
270 err = -EINVAL;
271 goto out;
272 }
273 }
274
275 memcpy(addr, valp, KVM_REG_SIZE(reg->id));
276
277 if (*vcpu_cpsr(vcpu) & PSR_MODE32_BIT) {
278 int i, nr_reg;
279
280 switch (*vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK) {
281 /*
282 * Either we are dealing with user mode, and only the
283 * first 15 registers (+ PC) must be narrowed to 32bit.
284 * AArch32 r0-r14 conveniently map to AArch64 x0-x14.
285 */
286 case PSR_AA32_MODE_USR:
287 case PSR_AA32_MODE_SYS:
288 nr_reg = 15;
289 break;
290
291 /*
292 * Otherwise, this is a privileged mode, and *all* the
293 * registers must be narrowed to 32bit.
294 */
295 default:
296 nr_reg = 31;
297 break;
298 }
299
300 for (i = 0; i < nr_reg; i++)
301 vcpu_set_reg(vcpu, i, (u32)vcpu_get_reg(vcpu, i));
302
303 *vcpu_pc(vcpu) = (u32)*vcpu_pc(vcpu);
304 }
305 out:
306 return err;
307 }
308
309 #define vq_word(vq) (((vq) - SVE_VQ_MIN) / 64)
310 #define vq_mask(vq) ((u64)1 << ((vq) - SVE_VQ_MIN) % 64)
311 #define vq_present(vqs, vq) (!!((vqs)[vq_word(vq)] & vq_mask(vq)))
312
313 static int get_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
314 {
315 unsigned int max_vq, vq;
316 u64 vqs[KVM_ARM64_SVE_VLS_WORDS];
317
318 if (!vcpu_has_sve(vcpu))
319 return -ENOENT;
320
321 if (WARN_ON(!sve_vl_valid(vcpu->arch.sve_max_vl)))
322 return -EINVAL;
323
324 memset(vqs, 0, sizeof(vqs));
325
326 max_vq = vcpu_sve_max_vq(vcpu);
327 for (vq = SVE_VQ_MIN; vq <= max_vq; ++vq)
328 if (sve_vq_available(vq))
329 vqs[vq_word(vq)] |= vq_mask(vq);
330
331 if (copy_to_user((void __user *)reg->addr, vqs, sizeof(vqs)))
332 return -EFAULT;
333
334 return 0;
335 }
336
337 static int set_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
338 {
339 unsigned int max_vq, vq;
340 u64 vqs[KVM_ARM64_SVE_VLS_WORDS];
341
342 if (!vcpu_has_sve(vcpu))
343 return -ENOENT;
344
345 if (kvm_arm_vcpu_sve_finalized(vcpu))
346 return -EPERM; /* too late! */
347
348 if (WARN_ON(vcpu->arch.sve_state))
349 return -EINVAL;
350
351 if (copy_from_user(vqs, (const void __user *)reg->addr, sizeof(vqs)))
352 return -EFAULT;
353
354 max_vq = 0;
355 for (vq = SVE_VQ_MIN; vq <= SVE_VQ_MAX; ++vq)
356 if (vq_present(vqs, vq))
357 max_vq = vq;
358
359 if (max_vq > sve_vq_from_vl(kvm_sve_max_vl))
360 return -EINVAL;
361
362 /*
363 * Vector lengths supported by the host can't currently be
364 * hidden from the guest individually: instead we can only set a
365 * maximum via ZCR_EL2.LEN. So, make sure the available vector
366 * lengths match the set requested exactly up to the requested
367 * maximum:
368 */
369 for (vq = SVE_VQ_MIN; vq <= max_vq; ++vq)
370 if (vq_present(vqs, vq) != sve_vq_available(vq))
371 return -EINVAL;
372
373 /* Can't run with no vector lengths at all: */
374 if (max_vq < SVE_VQ_MIN)
375 return -EINVAL;
376
377 /* vcpu->arch.sve_state will be alloc'd by kvm_vcpu_finalize_sve() */
378 vcpu->arch.sve_max_vl = sve_vl_from_vq(max_vq);
379
380 return 0;
381 }
382
383 #define SVE_REG_SLICE_SHIFT 0
384 #define SVE_REG_SLICE_BITS 5
385 #define SVE_REG_ID_SHIFT (SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS)
386 #define SVE_REG_ID_BITS 5
387
388 #define SVE_REG_SLICE_MASK \
389 GENMASK(SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS - 1, \
390 SVE_REG_SLICE_SHIFT)
391 #define SVE_REG_ID_MASK \
392 GENMASK(SVE_REG_ID_SHIFT + SVE_REG_ID_BITS - 1, SVE_REG_ID_SHIFT)
393
394 #define SVE_NUM_SLICES (1 << SVE_REG_SLICE_BITS)
395
396 #define KVM_SVE_ZREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_ZREG(0, 0))
397 #define KVM_SVE_PREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_PREG(0, 0))
398
399 /*
400 * Number of register slices required to cover each whole SVE register.
401 * NOTE: Only the first slice every exists, for now.
402 * If you are tempted to modify this, you must also rework sve_reg_to_region()
403 * to match:
404 */
405 #define vcpu_sve_slices(vcpu) 1
406
407 /* Bounds of a single SVE register slice within vcpu->arch.sve_state */
408 struct sve_state_reg_region {
409 unsigned int koffset; /* offset into sve_state in kernel memory */
410 unsigned int klen; /* length in kernel memory */
411 unsigned int upad; /* extra trailing padding in user memory */
412 };
413
414 /*
415 * Validate SVE register ID and get sanitised bounds for user/kernel SVE
416 * register copy
417 */
418 static int sve_reg_to_region(struct sve_state_reg_region *region,
419 struct kvm_vcpu *vcpu,
420 const struct kvm_one_reg *reg)
421 {
422 /* reg ID ranges for Z- registers */
423 const u64 zreg_id_min = KVM_REG_ARM64_SVE_ZREG(0, 0);
424 const u64 zreg_id_max = KVM_REG_ARM64_SVE_ZREG(SVE_NUM_ZREGS - 1,
425 SVE_NUM_SLICES - 1);
426
427 /* reg ID ranges for P- registers and FFR (which are contiguous) */
428 const u64 preg_id_min = KVM_REG_ARM64_SVE_PREG(0, 0);
429 const u64 preg_id_max = KVM_REG_ARM64_SVE_FFR(SVE_NUM_SLICES - 1);
430
431 unsigned int vq;
432 unsigned int reg_num;
433
434 unsigned int reqoffset, reqlen; /* User-requested offset and length */
435 unsigned int maxlen; /* Maximum permitted length */
436
437 size_t sve_state_size;
438
439 const u64 last_preg_id = KVM_REG_ARM64_SVE_PREG(SVE_NUM_PREGS - 1,
440 SVE_NUM_SLICES - 1);
441
442 /* Verify that the P-regs and FFR really do have contiguous IDs: */
443 BUILD_BUG_ON(KVM_REG_ARM64_SVE_FFR(0) != last_preg_id + 1);
444
445 /* Verify that we match the UAPI header: */
446 BUILD_BUG_ON(SVE_NUM_SLICES != KVM_ARM64_SVE_MAX_SLICES);
447
448 reg_num = (reg->id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT;
449
450 if (reg->id >= zreg_id_min && reg->id <= zreg_id_max) {
451 if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0)
452 return -ENOENT;
453
454 vq = vcpu_sve_max_vq(vcpu);
455
456 reqoffset = SVE_SIG_ZREG_OFFSET(vq, reg_num) -
457 SVE_SIG_REGS_OFFSET;
458 reqlen = KVM_SVE_ZREG_SIZE;
459 maxlen = SVE_SIG_ZREG_SIZE(vq);
460 } else if (reg->id >= preg_id_min && reg->id <= preg_id_max) {
461 if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0)
462 return -ENOENT;
463
464 vq = vcpu_sve_max_vq(vcpu);
465
466 reqoffset = SVE_SIG_PREG_OFFSET(vq, reg_num) -
467 SVE_SIG_REGS_OFFSET;
468 reqlen = KVM_SVE_PREG_SIZE;
469 maxlen = SVE_SIG_PREG_SIZE(vq);
470 } else {
471 return -EINVAL;
472 }
473
474 sve_state_size = vcpu_sve_state_size(vcpu);
475 if (WARN_ON(!sve_state_size))
476 return -EINVAL;
477
478 region->koffset = array_index_nospec(reqoffset, sve_state_size);
479 region->klen = min(maxlen, reqlen);
480 region->upad = reqlen - region->klen;
481
482 return 0;
483 }
484
485 static int get_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
486 {
487 int ret;
488 struct sve_state_reg_region region;
489 char __user *uptr = (char __user *)reg->addr;
490
491 /* Handle the KVM_REG_ARM64_SVE_VLS pseudo-reg as a special case: */
492 if (reg->id == KVM_REG_ARM64_SVE_VLS)
493 return get_sve_vls(vcpu, reg);
494
495 /* Try to interpret reg ID as an architectural SVE register... */
496 ret = sve_reg_to_region(®ion, vcpu, reg);
497 if (ret)
498 return ret;
499
500 if (!kvm_arm_vcpu_sve_finalized(vcpu))
501 return -EPERM;
502
503 if (copy_to_user(uptr, vcpu->arch.sve_state + region.koffset,
504 region.klen) ||
505 clear_user(uptr + region.klen, region.upad))
506 return -EFAULT;
507
508 return 0;
509 }
510
511 static int set_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
512 {
513 int ret;
514 struct sve_state_reg_region region;
515 const char __user *uptr = (const char __user *)reg->addr;
516
517 /* Handle the KVM_REG_ARM64_SVE_VLS pseudo-reg as a special case: */
518 if (reg->id == KVM_REG_ARM64_SVE_VLS)
519 return set_sve_vls(vcpu, reg);
520
521 /* Try to interpret reg ID as an architectural SVE register... */
522 ret = sve_reg_to_region(®ion, vcpu, reg);
523 if (ret)
524 return ret;
525
526 if (!kvm_arm_vcpu_sve_finalized(vcpu))
527 return -EPERM;
528
529 if (copy_from_user(vcpu->arch.sve_state + region.koffset, uptr,
530 region.klen))
531 return -EFAULT;
532
533 return 0;
534 }
535
536 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
537 {
538 return -EINVAL;
539 }
540
541 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
542 {
543 return -EINVAL;
544 }
545
546 static int copy_core_reg_indices(const struct kvm_vcpu *vcpu,
547 u64 __user *uindices)
548 {
549 unsigned int i;
550 int n = 0;
551
552 for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) {
553 u64 reg = KVM_REG_ARM64 | KVM_REG_ARM_CORE | i;
554 int size = core_reg_size_from_offset(vcpu, i);
555
556 if (size < 0)
557 continue;
558
559 switch (size) {
560 case sizeof(__u32):
561 reg |= KVM_REG_SIZE_U32;
562 break;
563
564 case sizeof(__u64):
565 reg |= KVM_REG_SIZE_U64;
566 break;
567
568 case sizeof(__uint128_t):
569 reg |= KVM_REG_SIZE_U128;
570 break;
571
572 default:
573 WARN_ON(1);
574 continue;
575 }
576
577 if (uindices) {
578 if (put_user(reg, uindices))
579 return -EFAULT;
580 uindices++;
581 }
582
583 n++;
584 }
585
586 return n;
587 }
588
589 static unsigned long num_core_regs(const struct kvm_vcpu *vcpu)
590 {
591 return copy_core_reg_indices(vcpu, NULL);
592 }
593
594 static const u64 timer_reg_list[] = {
595 KVM_REG_ARM_TIMER_CTL,
596 KVM_REG_ARM_TIMER_CNT,
597 KVM_REG_ARM_TIMER_CVAL,
598 KVM_REG_ARM_PTIMER_CTL,
599 KVM_REG_ARM_PTIMER_CNT,
600 KVM_REG_ARM_PTIMER_CVAL,
601 };
602
603 #define NUM_TIMER_REGS ARRAY_SIZE(timer_reg_list)
604
605 static bool is_timer_reg(u64 index)
606 {
607 switch (index) {
608 case KVM_REG_ARM_TIMER_CTL:
609 case KVM_REG_ARM_TIMER_CNT:
610 case KVM_REG_ARM_TIMER_CVAL:
611 case KVM_REG_ARM_PTIMER_CTL:
612 case KVM_REG_ARM_PTIMER_CNT:
613 case KVM_REG_ARM_PTIMER_CVAL:
614 return true;
615 }
616 return false;
617 }
618
619 static int copy_timer_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
620 {
621 for (int i = 0; i < NUM_TIMER_REGS; i++) {
622 if (put_user(timer_reg_list[i], uindices))
623 return -EFAULT;
624 uindices++;
625 }
626
627 return 0;
628 }
629
630 static int set_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
631 {
632 void __user *uaddr = (void __user *)(long)reg->addr;
633 u64 val;
634 int ret;
635
636 ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id));
637 if (ret != 0)
638 return -EFAULT;
639
640 return kvm_arm_timer_set_reg(vcpu, reg->id, val);
641 }
642
643 static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
644 {
645 void __user *uaddr = (void __user *)(long)reg->addr;
646 u64 val;
647
648 val = kvm_arm_timer_get_reg(vcpu, reg->id);
649 return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0;
650 }
651
652 static unsigned long num_sve_regs(const struct kvm_vcpu *vcpu)
653 {
654 const unsigned int slices = vcpu_sve_slices(vcpu);
655
656 if (!vcpu_has_sve(vcpu))
657 return 0;
658
659 /* Policed by KVM_GET_REG_LIST: */
660 WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu));
661
662 return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */)
663 + 1; /* KVM_REG_ARM64_SVE_VLS */
664 }
665
666 static int copy_sve_reg_indices(const struct kvm_vcpu *vcpu,
667 u64 __user *uindices)
668 {
669 const unsigned int slices = vcpu_sve_slices(vcpu);
670 u64 reg;
671 unsigned int i, n;
672 int num_regs = 0;
673
674 if (!vcpu_has_sve(vcpu))
675 return 0;
676
677 /* Policed by KVM_GET_REG_LIST: */
678 WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu));
679
680 /*
681 * Enumerate this first, so that userspace can save/restore in
682 * the order reported by KVM_GET_REG_LIST:
683 */
684 reg = KVM_REG_ARM64_SVE_VLS;
685 if (put_user(reg, uindices++))
686 return -EFAULT;
687 ++num_regs;
688
689 for (i = 0; i < slices; i++) {
690 for (n = 0; n < SVE_NUM_ZREGS; n++) {
691 reg = KVM_REG_ARM64_SVE_ZREG(n, i);
692 if (put_user(reg, uindices++))
693 return -EFAULT;
694 num_regs++;
695 }
696
697 for (n = 0; n < SVE_NUM_PREGS; n++) {
698 reg = KVM_REG_ARM64_SVE_PREG(n, i);
699 if (put_user(reg, uindices++))
700 return -EFAULT;
701 num_regs++;
702 }
703
704 reg = KVM_REG_ARM64_SVE_FFR(i);
705 if (put_user(reg, uindices++))
706 return -EFAULT;
707 num_regs++;
708 }
709
710 return num_regs;
711 }
712
713 /**
714 * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG
715 * @vcpu: the vCPU pointer
716 *
717 * This is for all registers.
718 */
719 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
720 {
721 unsigned long res = 0;
722
723 res += num_core_regs(vcpu);
724 res += num_sve_regs(vcpu);
725 res += kvm_arm_num_sys_reg_descs(vcpu);
726 res += kvm_arm_get_fw_num_regs(vcpu);
727 res += NUM_TIMER_REGS;
728
729 return res;
730 }
731
732 /**
733 * kvm_arm_copy_reg_indices - get indices of all registers.
734 * @vcpu: the vCPU pointer
735 * @uindices: register list to copy
736 *
737 * We do core registers right here, then we append system regs.
738 */
739 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
740 {
741 int ret;
742
743 ret = copy_core_reg_indices(vcpu, uindices);
744 if (ret < 0)
745 return ret;
746 uindices += ret;
747
748 ret = copy_sve_reg_indices(vcpu, uindices);
749 if (ret < 0)
750 return ret;
751 uindices += ret;
752
753 ret = kvm_arm_copy_fw_reg_indices(vcpu, uindices);
754 if (ret < 0)
755 return ret;
756 uindices += kvm_arm_get_fw_num_regs(vcpu);
757
758 ret = copy_timer_indices(vcpu, uindices);
759 if (ret < 0)
760 return ret;
761 uindices += NUM_TIMER_REGS;
762
763 return kvm_arm_copy_sys_reg_indices(vcpu, uindices);
764 }
765
766 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
767 {
768 /* We currently use nothing arch-specific in upper 32 bits */
769 if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
770 return -EINVAL;
771
772 switch (reg->id & KVM_REG_ARM_COPROC_MASK) {
773 case KVM_REG_ARM_CORE: return get_core_reg(vcpu, reg);
774 case KVM_REG_ARM_FW:
775 case KVM_REG_ARM_FW_FEAT_BMAP:
776 return kvm_arm_get_fw_reg(vcpu, reg);
777 case KVM_REG_ARM64_SVE: return get_sve_reg(vcpu, reg);
778 }
779
780 if (is_timer_reg(reg->id))
781 return get_timer_reg(vcpu, reg);
782
783 return kvm_arm_sys_reg_get_reg(vcpu, reg);
784 }
785
786 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
787 {
788 /* We currently use nothing arch-specific in upper 32 bits */
789 if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
790 return -EINVAL;
791
792 switch (reg->id & KVM_REG_ARM_COPROC_MASK) {
793 case KVM_REG_ARM_CORE: return set_core_reg(vcpu, reg);
794 case KVM_REG_ARM_FW:
795 case KVM_REG_ARM_FW_FEAT_BMAP:
796 return kvm_arm_set_fw_reg(vcpu, reg);
797 case KVM_REG_ARM64_SVE: return set_sve_reg(vcpu, reg);
798 }
799
800 if (is_timer_reg(reg->id))
801 return set_timer_reg(vcpu, reg);
802
803 return kvm_arm_sys_reg_set_reg(vcpu, reg);
804 }
805
806 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
807 struct kvm_sregs *sregs)
808 {
809 return -EINVAL;
810 }
811
812 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
813 struct kvm_sregs *sregs)
814 {
815 return -EINVAL;
816 }
817
818 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
819 struct kvm_vcpu_events *events)
820 {
821 events->exception.serror_pending = !!(vcpu->arch.hcr_el2 & HCR_VSE);
822 events->exception.serror_has_esr = cpus_have_final_cap(ARM64_HAS_RAS_EXTN);
823
824 if (events->exception.serror_pending && events->exception.serror_has_esr)
825 events->exception.serror_esr = vcpu_get_vsesr(vcpu);
826
827 /*
828 * We never return a pending ext_dabt here because we deliver it to
829 * the virtual CPU directly when setting the event and it's no longer
830 * 'pending' at this point.
831 */
832
833 return 0;
834 }
835
836 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
837 struct kvm_vcpu_events *events)
838 {
839 bool serror_pending = events->exception.serror_pending;
840 bool has_esr = events->exception.serror_has_esr;
841 bool ext_dabt_pending = events->exception.ext_dabt_pending;
842
843 if (serror_pending && has_esr) {
844 if (!cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
845 return -EINVAL;
846
847 if (!((events->exception.serror_esr) & ~ESR_ELx_ISS_MASK))
848 kvm_set_sei_esr(vcpu, events->exception.serror_esr);
849 else
850 return -EINVAL;
851 } else if (serror_pending) {
852 kvm_inject_vabt(vcpu);
853 }
854
855 if (ext_dabt_pending)
856 kvm_inject_dabt(vcpu, kvm_vcpu_get_hfar(vcpu));
857
858 return 0;
859 }
860
861 u32 __attribute_const__ kvm_target_cpu(void)
862 {
863 unsigned long implementor = read_cpuid_implementor();
864 unsigned long part_number = read_cpuid_part_number();
865
866 switch (implementor) {
867 case ARM_CPU_IMP_ARM:
868 switch (part_number) {
869 case ARM_CPU_PART_AEM_V8:
870 return KVM_ARM_TARGET_AEM_V8;
871 case ARM_CPU_PART_FOUNDATION:
872 return KVM_ARM_TARGET_FOUNDATION_V8;
873 case ARM_CPU_PART_CORTEX_A53:
874 return KVM_ARM_TARGET_CORTEX_A53;
875 case ARM_CPU_PART_CORTEX_A57:
876 return KVM_ARM_TARGET_CORTEX_A57;
877 }
878 break;
879 case ARM_CPU_IMP_APM:
880 switch (part_number) {
881 case APM_CPU_PART_XGENE:
882 return KVM_ARM_TARGET_XGENE_POTENZA;
883 }
884 break;
885 }
886
887 /* Return a default generic target */
888 return KVM_ARM_TARGET_GENERIC_V8;
889 }
890
891 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
892 {
893 return -EINVAL;
894 }
895
896 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
897 {
898 return -EINVAL;
899 }
900
901 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
902 struct kvm_translation *tr)
903 {
904 return -EINVAL;
905 }
906
907 /**
908 * kvm_arch_vcpu_ioctl_set_guest_debug - set up guest debugging
909 * @vcpu: the vCPU pointer
910 * @dbg: the ioctl data buffer
911 *
912 * This sets up and enables the VM for guest debugging. Userspace
913 * passes in a control flag to enable different debug types and
914 * potentially other architecture specific information in the rest of
915 * the structure.
916 */
917 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
918 struct kvm_guest_debug *dbg)
919 {
920 int ret = 0;
921
922 trace_kvm_set_guest_debug(vcpu, dbg->control);
923
924 if (dbg->control & ~KVM_GUESTDBG_VALID_MASK) {
925 ret = -EINVAL;
926 goto out;
927 }
928
929 if (dbg->control & KVM_GUESTDBG_ENABLE) {
930 vcpu->guest_debug = dbg->control;
931
932 /* Hardware assisted Break and Watch points */
933 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW) {
934 vcpu->arch.external_debug_state = dbg->arch;
935 }
936
937 } else {
938 /* If not enabled clear all flags */
939 vcpu->guest_debug = 0;
940 vcpu_clear_flag(vcpu, DBG_SS_ACTIVE_PENDING);
941 }
942
943 out:
944 return ret;
945 }
946
947 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
948 struct kvm_device_attr *attr)
949 {
950 int ret;
951
952 switch (attr->group) {
953 case KVM_ARM_VCPU_PMU_V3_CTRL:
954 mutex_lock(&vcpu->kvm->arch.config_lock);
955 ret = kvm_arm_pmu_v3_set_attr(vcpu, attr);
956 mutex_unlock(&vcpu->kvm->arch.config_lock);
957 break;
958 case KVM_ARM_VCPU_TIMER_CTRL:
959 ret = kvm_arm_timer_set_attr(vcpu, attr);
960 break;
961 case KVM_ARM_VCPU_PVTIME_CTRL:
962 ret = kvm_arm_pvtime_set_attr(vcpu, attr);
963 break;
964 default:
965 ret = -ENXIO;
966 break;
967 }
968
969 return ret;
970 }
971
972 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
973 struct kvm_device_attr *attr)
974 {
975 int ret;
976
977 switch (attr->group) {
978 case KVM_ARM_VCPU_PMU_V3_CTRL:
979 ret = kvm_arm_pmu_v3_get_attr(vcpu, attr);
980 break;
981 case KVM_ARM_VCPU_TIMER_CTRL:
982 ret = kvm_arm_timer_get_attr(vcpu, attr);
983 break;
984 case KVM_ARM_VCPU_PVTIME_CTRL:
985 ret = kvm_arm_pvtime_get_attr(vcpu, attr);
986 break;
987 default:
988 ret = -ENXIO;
989 break;
990 }
991
992 return ret;
993 }
994
995 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
996 struct kvm_device_attr *attr)
997 {
998 int ret;
999
1000 switch (attr->group) {
1001 case KVM_ARM_VCPU_PMU_V3_CTRL:
1002 ret = kvm_arm_pmu_v3_has_attr(vcpu, attr);
1003 break;
1004 case KVM_ARM_VCPU_TIMER_CTRL:
1005 ret = kvm_arm_timer_has_attr(vcpu, attr);
1006 break;
1007 case KVM_ARM_VCPU_PVTIME_CTRL:
1008 ret = kvm_arm_pvtime_has_attr(vcpu, attr);
1009 break;
1010 default:
1011 ret = -ENXIO;
1012 break;
1013 }
1014
1015 return ret;
1016 }
1017
1018 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1019 struct kvm_arm_copy_mte_tags *copy_tags)
1020 {
1021 gpa_t guest_ipa = copy_tags->guest_ipa;
1022 size_t length = copy_tags->length;
1023 void __user *tags = copy_tags->addr;
1024 gpa_t gfn;
1025 bool write = !(copy_tags->flags & KVM_ARM_TAGS_FROM_GUEST);
1026 int ret = 0;
1027
1028 if (!kvm_has_mte(kvm))
1029 return -EINVAL;
1030
1031 if (copy_tags->reserved[0] || copy_tags->reserved[1])
1032 return -EINVAL;
1033
1034 if (copy_tags->flags & ~KVM_ARM_TAGS_FROM_GUEST)
1035 return -EINVAL;
1036
1037 if (length & ~PAGE_MASK || guest_ipa & ~PAGE_MASK)
1038 return -EINVAL;
1039
1040 /* Lengths above INT_MAX cannot be represented in the return value */
1041 if (length > INT_MAX)
1042 return -EINVAL;
1043
1044 gfn = gpa_to_gfn(guest_ipa);
1045
1046 mutex_lock(&kvm->slots_lock);
1047
1048 while (length > 0) {
1049 kvm_pfn_t pfn = gfn_to_pfn_prot(kvm, gfn, write, NULL);
1050 void *maddr;
1051 unsigned long num_tags;
1052 struct page *page;
1053
1054 if (is_error_noslot_pfn(pfn)) {
1055 ret = -EFAULT;
1056 goto out;
1057 }
1058
1059 page = pfn_to_online_page(pfn);
1060 if (!page) {
1061 /* Reject ZONE_DEVICE memory */
1062 ret = -EFAULT;
1063 goto out;
1064 }
1065 maddr = page_address(page);
1066
1067 if (!write) {
1068 if (page_mte_tagged(page))
1069 num_tags = mte_copy_tags_to_user(tags, maddr,
1070 MTE_GRANULES_PER_PAGE);
1071 else
1072 /* No tags in memory, so write zeros */
1073 num_tags = MTE_GRANULES_PER_PAGE -
1074 clear_user(tags, MTE_GRANULES_PER_PAGE);
1075 kvm_release_pfn_clean(pfn);
1076 } else {
1077 /*
1078 * Only locking to serialise with a concurrent
1079 * __set_ptes() in the VMM but still overriding the
1080 * tags, hence ignoring the return value.
1081 */
1082 try_page_mte_tagging(page);
1083 num_tags = mte_copy_tags_from_user(maddr, tags,
1084 MTE_GRANULES_PER_PAGE);
1085
1086 /* uaccess failed, don't leave stale tags */
1087 if (num_tags != MTE_GRANULES_PER_PAGE)
1088 mte_clear_page_tags(maddr);
1089 set_page_mte_tagged(page);
1090
1091 kvm_release_pfn_dirty(pfn);
1092 }
1093
1094 if (num_tags != MTE_GRANULES_PER_PAGE) {
1095 ret = -EFAULT;
1096 goto out;
1097 }
1098
1099 gfn++;
1100 tags += num_tags;
1101 length -= PAGE_SIZE;
1102 }
1103
1104 out:
1105 mutex_unlock(&kvm->slots_lock);
1106 /* If some data has been copied report the number of bytes copied */
1107 if (length != copy_tags->length)
1108 return copy_tags->length - length;
1109 return ret;
1110 }
1111
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.