1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * cpu.h: Values of the PRID register used to match up
4 * various LoongArch CPU types.
5 *
6 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
7 */
8 #ifndef _ASM_CPU_H
9 #define _ASM_CPU_H
10
11 /*
12 * As described in LoongArch specs from Loongson Technology, the PRID register
13 * (CPUCFG.00) has the following layout:
14 *
15 * +---------------+----------------+------------+--------------------+
16 * | Reserved | Company ID | Series ID | Product ID |
17 * +---------------+----------------+------------+--------------------+
18 * 31 24 23 16 15 12 11 0
19 */
20
21 /*
22 * Assigned Company values for bits 23:16 of the PRID register.
23 */
24
25 #define PRID_COMP_MASK 0xff0000
26
27 #define PRID_COMP_LOONGSON 0x140000
28
29 /*
30 * Assigned Series ID values for bits 15:12 of the PRID register. In order
31 * to detect a certain CPU type exactly eventually additional registers may
32 * need to be examined.
33 */
34
35 #define PRID_SERIES_MASK 0xf000
36
37 #define PRID_SERIES_LA132 0x8000 /* Loongson 32bit */
38 #define PRID_SERIES_LA264 0xa000 /* Loongson 64bit, 2-issue */
39 #define PRID_SERIES_LA364 0xb000 /* Loongson 64bit, 3-issue */
40 #define PRID_SERIES_LA464 0xc000 /* Loongson 64bit, 4-issue */
41 #define PRID_SERIES_LA664 0xd000 /* Loongson 64bit, 6-issue */
42
43 /*
44 * Particular Product ID values for bits 11:0 of the PRID register.
45 */
46
47 #define PRID_PRODUCT_MASK 0x0fff
48
49 #if !defined(__ASSEMBLY__)
50
51 enum cpu_type_enum {
52 CPU_UNKNOWN,
53 CPU_LOONGSON32,
54 CPU_LOONGSON64,
55 CPU_LAST
56 };
57
58 #endif /* !__ASSEMBLY */
59
60 /*
61 * ISA Level encodings
62 *
63 */
64
65 #define LOONGARCH_CPU_ISA_LA32R 0x00000001
66 #define LOONGARCH_CPU_ISA_LA32S 0x00000002
67 #define LOONGARCH_CPU_ISA_LA64 0x00000004
68
69 #define LOONGARCH_CPU_ISA_32BIT (LOONGARCH_CPU_ISA_LA32R | LOONGARCH_CPU_ISA_LA32S)
70 #define LOONGARCH_CPU_ISA_64BIT LOONGARCH_CPU_ISA_LA64
71
72 /*
73 * CPU Option encodings
74 */
75 #define CPU_FEATURE_CPUCFG 0 /* CPU has CPUCFG */
76 #define CPU_FEATURE_LAM 1 /* CPU has Atomic instructions */
77 #define CPU_FEATURE_UAL 2 /* CPU supports unaligned access */
78 #define CPU_FEATURE_FPU 3 /* CPU has FPU */
79 #define CPU_FEATURE_LSX 4 /* CPU has LSX (128-bit SIMD) */
80 #define CPU_FEATURE_LASX 5 /* CPU has LASX (256-bit SIMD) */
81 #define CPU_FEATURE_CRC32 6 /* CPU has CRC32 instructions */
82 #define CPU_FEATURE_COMPLEX 7 /* CPU has Complex instructions */
83 #define CPU_FEATURE_CRYPTO 8 /* CPU has Crypto instructions */
84 #define CPU_FEATURE_LVZ 9 /* CPU has Virtualization extension */
85 #define CPU_FEATURE_LBT_X86 10 /* CPU has X86 Binary Translation */
86 #define CPU_FEATURE_LBT_ARM 11 /* CPU has ARM Binary Translation */
87 #define CPU_FEATURE_LBT_MIPS 12 /* CPU has MIPS Binary Translation */
88 #define CPU_FEATURE_TLB 13 /* CPU has TLB */
89 #define CPU_FEATURE_CSR 14 /* CPU has CSR */
90 #define CPU_FEATURE_WATCH 15 /* CPU has watchpoint registers */
91 #define CPU_FEATURE_VINT 16 /* CPU has vectored interrupts */
92 #define CPU_FEATURE_CSRIPI 17 /* CPU has CSR-IPI */
93 #define CPU_FEATURE_EXTIOI 18 /* CPU has EXT-IOI */
94 #define CPU_FEATURE_PREFETCH 19 /* CPU has prefetch instructions */
95 #define CPU_FEATURE_PMP 20 /* CPU has perfermance counter */
96 #define CPU_FEATURE_SCALEFREQ 21 /* CPU supports cpufreq scaling */
97 #define CPU_FEATURE_FLATMODE 22 /* CPU has flat mode */
98 #define CPU_FEATURE_EIODECODE 23 /* CPU has EXTIOI interrupt pin decode mode */
99 #define CPU_FEATURE_GUESTID 24 /* CPU has GuestID feature */
100 #define CPU_FEATURE_HYPERVISOR 25 /* CPU has hypervisor (running in VM) */
101 #define CPU_FEATURE_PTW 26 /* CPU has hardware page table walker */
102
103 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
104 #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
105 #define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)
106 #define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)
107 #define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX)
108 #define LOONGARCH_CPU_LASX BIT_ULL(CPU_FEATURE_LASX)
109 #define LOONGARCH_CPU_CRC32 BIT_ULL(CPU_FEATURE_CRC32)
110 #define LOONGARCH_CPU_COMPLEX BIT_ULL(CPU_FEATURE_COMPLEX)
111 #define LOONGARCH_CPU_CRYPTO BIT_ULL(CPU_FEATURE_CRYPTO)
112 #define LOONGARCH_CPU_LVZ BIT_ULL(CPU_FEATURE_LVZ)
113 #define LOONGARCH_CPU_LBT_X86 BIT_ULL(CPU_FEATURE_LBT_X86)
114 #define LOONGARCH_CPU_LBT_ARM BIT_ULL(CPU_FEATURE_LBT_ARM)
115 #define LOONGARCH_CPU_LBT_MIPS BIT_ULL(CPU_FEATURE_LBT_MIPS)
116 #define LOONGARCH_CPU_TLB BIT_ULL(CPU_FEATURE_TLB)
117 #define LOONGARCH_CPU_CSR BIT_ULL(CPU_FEATURE_CSR)
118 #define LOONGARCH_CPU_WATCH BIT_ULL(CPU_FEATURE_WATCH)
119 #define LOONGARCH_CPU_VINT BIT_ULL(CPU_FEATURE_VINT)
120 #define LOONGARCH_CPU_CSRIPI BIT_ULL(CPU_FEATURE_CSRIPI)
121 #define LOONGARCH_CPU_EXTIOI BIT_ULL(CPU_FEATURE_EXTIOI)
122 #define LOONGARCH_CPU_PREFETCH BIT_ULL(CPU_FEATURE_PREFETCH)
123 #define LOONGARCH_CPU_PMP BIT_ULL(CPU_FEATURE_PMP)
124 #define LOONGARCH_CPU_SCALEFREQ BIT_ULL(CPU_FEATURE_SCALEFREQ)
125 #define LOONGARCH_CPU_FLATMODE BIT_ULL(CPU_FEATURE_FLATMODE)
126 #define LOONGARCH_CPU_EIODECODE BIT_ULL(CPU_FEATURE_EIODECODE)
127 #define LOONGARCH_CPU_GUESTID BIT_ULL(CPU_FEATURE_GUESTID)
128 #define LOONGARCH_CPU_HYPERVISOR BIT_ULL(CPU_FEATURE_HYPERVISOR)
129 #define LOONGARCH_CPU_PTW BIT_ULL(CPU_FEATURE_PTW)
130
131 #endif /* _ASM_CPU_H */
132
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