1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MTX-1 platform devices registration (Au1500)
4 *
5 * Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org>
6 */
7
8 #include <linux/init.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/platform_device.h>
12 #include <linux/leds.h>
13 #include <linux/gpio.h>
14 #include <linux/gpio/machine.h>
15 #include <linux/gpio_keys.h>
16 #include <linux/input.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/mtd/physmap.h>
19 #include <mtd/mtd-abi.h>
20 #include <asm/bootinfo.h>
21 #include <asm/reboot.h>
22 #include <asm/setup.h>
23 #include <asm/mach-au1x00/au1000.h>
24 #include <asm/mach-au1x00/gpio-au1000.h>
25 #include <asm/mach-au1x00/au1xxx_eth.h>
26 #include <prom.h>
27
28 const char *get_system_type(void)
29 {
30 return "MTX-1";
31 }
32
33 void prom_putchar(char c)
34 {
35 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
36 }
37
38 static void mtx1_reset(char *c)
39 {
40 /* Jump to the reset vector */
41 __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000));
42 }
43
44 static void mtx1_power_off(void)
45 {
46 while (1)
47 asm volatile (
48 " .set mips32 \n"
49 " wait \n"
50 " .set mips0 \n");
51 }
52
53 void __init board_setup(void)
54 {
55 #if IS_ENABLED(CONFIG_USB_OHCI_HCD)
56 /* Enable USB power switch */
57 alchemy_gpio_direction_output(204, 0);
58 #endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
59
60 /* Initialize sys_pinfunc */
61 alchemy_wrsys(SYS_PF_NI2, AU1000_SYS_PINFUNC);
62
63 /* Initialize GPIO */
64 alchemy_wrsys(~0, AU1000_SYS_TRIOUTCLR);
65 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
66 alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
67 alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
68 alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */
69
70 /* Enable LED and set it to green */
71 alchemy_gpio_direction_output(211, 1); /* green on */
72 alchemy_gpio_direction_output(212, 0); /* red off */
73
74 pm_power_off = mtx1_power_off;
75 _machine_halt = mtx1_power_off;
76 _machine_restart = mtx1_reset;
77
78 printk(KERN_INFO "4G Systems MTX-1 Board\n");
79 }
80
81 /******************************************************************************/
82
83 static struct gpio_keys_button mtx1_gpio_button[] = {
84 {
85 .gpio = 207,
86 .code = BTN_0,
87 .desc = "System button",
88 }
89 };
90
91 static struct gpio_keys_platform_data mtx1_buttons_data = {
92 .buttons = mtx1_gpio_button,
93 .nbuttons = ARRAY_SIZE(mtx1_gpio_button),
94 };
95
96 static struct platform_device mtx1_button = {
97 .name = "gpio-keys",
98 .id = -1,
99 .dev = {
100 .platform_data = &mtx1_buttons_data,
101 }
102 };
103
104 static struct gpiod_lookup_table mtx1_wdt_gpio_table = {
105 .dev_id = "mtx1-wdt.0",
106 .table = {
107 /* Global number 215 is offset 15 on Alchemy GPIO 2 */
108 GPIO_LOOKUP("alchemy-gpio2", 15, NULL, GPIO_ACTIVE_HIGH),
109 { },
110 },
111 };
112
113 static struct platform_device mtx1_wdt = {
114 .name = "mtx1-wdt",
115 .id = 0,
116 };
117
118 static const struct gpio_led default_leds[] = {
119 {
120 .name = "mtx1:green",
121 .gpio = 211,
122 }, {
123 .name = "mtx1:red",
124 .gpio = 212,
125 },
126 };
127
128 static struct gpio_led_platform_data mtx1_led_data = {
129 .num_leds = ARRAY_SIZE(default_leds),
130 .leds = default_leds,
131 };
132
133 static struct platform_device mtx1_gpio_leds = {
134 .name = "leds-gpio",
135 .id = -1,
136 .dev = {
137 .platform_data = &mtx1_led_data,
138 }
139 };
140
141 static struct mtd_partition mtx1_mtd_partitions[] = {
142 {
143 .name = "filesystem",
144 .size = 0x01C00000,
145 .offset = 0,
146 },
147 {
148 .name = "yamon",
149 .size = 0x00100000,
150 .offset = MTDPART_OFS_APPEND,
151 .mask_flags = MTD_WRITEABLE,
152 },
153 {
154 .name = "kernel",
155 .size = 0x002c0000,
156 .offset = MTDPART_OFS_APPEND,
157 },
158 {
159 .name = "yamon env",
160 .size = 0x00040000,
161 .offset = MTDPART_OFS_APPEND,
162 },
163 };
164
165 static struct physmap_flash_data mtx1_flash_data = {
166 .width = 4,
167 .nr_parts = 4,
168 .parts = mtx1_mtd_partitions,
169 };
170
171 static struct resource mtx1_mtd_resource = {
172 .start = 0x1e000000,
173 .end = 0x1fffffff,
174 .flags = IORESOURCE_MEM,
175 };
176
177 static struct platform_device mtx1_mtd = {
178 .name = "physmap-flash",
179 .dev = {
180 .platform_data = &mtx1_flash_data,
181 },
182 .num_resources = 1,
183 .resource = &mtx1_mtd_resource,
184 };
185
186 static struct resource alchemy_pci_host_res[] = {
187 [0] = {
188 .start = AU1500_PCI_PHYS_ADDR,
189 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
190 .flags = IORESOURCE_MEM,
191 },
192 };
193
194 static int mtx1_pci_idsel(unsigned int devsel, int assert)
195 {
196 /* This function is only necessary to support a proprietary Cardbus
197 * adapter on the mtx-1 "singleboard" variant. It triggers a custom
198 * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
199 */
200 udelay(1);
201
202 if (assert && devsel != 0)
203 /* Suppress signal to Cardbus */
204 alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
205 else
206 alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
207
208 udelay(1);
209 return 1;
210 }
211
212 static const char mtx1_irqtab[][5] = {
213 [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
214 [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
215 [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
216 [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
217 [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
218 [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
219 [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
220 [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
221 };
222
223 static int mtx1_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
224 {
225 return mtx1_irqtab[slot][pin];
226 }
227
228 static struct alchemy_pci_platdata mtx1_pci_pd = {
229 .board_map_irq = mtx1_map_pci_irq,
230 .board_pci_idsel = mtx1_pci_idsel,
231 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
232 PCI_CONFIG_CH |
233 #if defined(__MIPSEB__)
234 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
235 #else
236 0,
237 #endif
238 };
239
240 static struct platform_device mtx1_pci_host = {
241 .dev.platform_data = &mtx1_pci_pd,
242 .name = "alchemy-pci",
243 .id = 0,
244 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
245 .resource = alchemy_pci_host_res,
246 };
247
248 static struct platform_device *mtx1_devs[] __initdata = {
249 &mtx1_pci_host,
250 &mtx1_gpio_leds,
251 &mtx1_wdt,
252 &mtx1_button,
253 &mtx1_mtd,
254 };
255
256 static struct au1000_eth_platform_data mtx1_au1000_eth0_pdata = {
257 .phy_search_highest_addr = 1,
258 .phy1_search_mac0 = 1,
259 };
260
261 static int __init mtx1_register_devices(void)
262 {
263 int rc;
264
265 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_HIGH);
266 irq_set_irq_type(AU1500_GPIO201_INT, IRQ_TYPE_LEVEL_LOW);
267 irq_set_irq_type(AU1500_GPIO202_INT, IRQ_TYPE_LEVEL_LOW);
268 irq_set_irq_type(AU1500_GPIO203_INT, IRQ_TYPE_LEVEL_LOW);
269 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
270
271 au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata);
272
273 rc = gpio_request(mtx1_gpio_button[0].gpio,
274 mtx1_gpio_button[0].desc);
275 if (rc < 0) {
276 printk(KERN_INFO "mtx1: failed to request %d\n",
277 mtx1_gpio_button[0].gpio);
278 goto out;
279 }
280 gpio_direction_input(mtx1_gpio_button[0].gpio);
281 out:
282 gpiod_add_lookup_table(&mtx1_wdt_gpio_table);
283 return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs));
284 }
285 arch_initcall(mtx1_register_devices);
286
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