1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * DBAu1200/PBAu1200 board platform device registration
4 *
5 * Copyright (C) 2008-2011 Manuel Lauss
6 */
7
8 #include <linux/clk.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/gpio.h>
11 #include <linux/i2c.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/leds.h>
16 #include <linux/mmc/host.h>
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/platnand.h>
19 #include <linux/platform_device.h>
20 #include <linux/serial_8250.h>
21 #include <linux/spi/spi.h>
22 #include <linux/spi/flash.h>
23 #include <linux/smc91x.h>
24 #include <linux/ata_platform.h>
25 #include <asm/mach-au1x00/au1000.h>
26 #include <asm/mach-au1x00/au1100_mmc.h>
27 #include <asm/mach-au1x00/au1xxx_dbdma.h>
28 #include <asm/mach-au1x00/au1xxx_psc.h>
29 #include <asm/mach-au1x00/au1200fb.h>
30 #include <asm/mach-au1x00/au1550_spi.h>
31 #include <asm/mach-db1x00/bcsr.h>
32
33 #include "platform.h"
34
35 #define BCSR_INT_IDE 0x0001
36 #define BCSR_INT_ETH 0x0002
37 #define BCSR_INT_PC0 0x0004
38 #define BCSR_INT_PC0STSCHG 0x0008
39 #define BCSR_INT_PC1 0x0010
40 #define BCSR_INT_PC1STSCHG 0x0020
41 #define BCSR_INT_DC 0x0040
42 #define BCSR_INT_FLASHBUSY 0x0080
43 #define BCSR_INT_PC0INSERT 0x0100
44 #define BCSR_INT_PC0EJECT 0x0200
45 #define BCSR_INT_PC1INSERT 0x0400
46 #define BCSR_INT_PC1EJECT 0x0800
47 #define BCSR_INT_SD0INSERT 0x1000
48 #define BCSR_INT_SD0EJECT 0x2000
49 #define BCSR_INT_SD1INSERT 0x4000
50 #define BCSR_INT_SD1EJECT 0x8000
51
52 #define DB1200_IDE_PHYS_ADDR 0x18800000
53 #define DB1200_IDE_REG_SHIFT 5
54 #define DB1200_IDE_PHYS_LEN (16 << DB1200_IDE_REG_SHIFT)
55 #define DB1200_ETH_PHYS_ADDR 0x19000300
56 #define DB1200_NAND_PHYS_ADDR 0x20000000
57
58 #define PB1200_IDE_PHYS_ADDR 0x0C800000
59 #define PB1200_ETH_PHYS_ADDR 0x0D000300
60 #define PB1200_NAND_PHYS_ADDR 0x1C000000
61
62 #define DB1200_INT_BEGIN (AU1000_MAX_INTR + 1)
63 #define DB1200_IDE_INT (DB1200_INT_BEGIN + 0)
64 #define DB1200_ETH_INT (DB1200_INT_BEGIN + 1)
65 #define DB1200_PC0_INT (DB1200_INT_BEGIN + 2)
66 #define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3)
67 #define DB1200_PC1_INT (DB1200_INT_BEGIN + 4)
68 #define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5)
69 #define DB1200_DC_INT (DB1200_INT_BEGIN + 6)
70 #define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7)
71 #define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8)
72 #define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9)
73 #define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10)
74 #define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11)
75 #define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12)
76 #define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13)
77 #define PB1200_SD1_INSERT_INT (DB1200_INT_BEGIN + 14)
78 #define PB1200_SD1_EJECT_INT (DB1200_INT_BEGIN + 15)
79 #define DB1200_INT_END (DB1200_INT_BEGIN + 15)
80
81 const char *get_system_type(void);
82
83 static int __init db1200_detect_board(void)
84 {
85 int bid;
86
87 /* try the DB1200 first */
88 bcsr_init(DB1200_BCSR_PHYS_ADDR,
89 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
90 if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
91 unsigned short t = bcsr_read(BCSR_HEXLEDS);
92 bcsr_write(BCSR_HEXLEDS, ~t);
93 if (bcsr_read(BCSR_HEXLEDS) != t) {
94 bcsr_write(BCSR_HEXLEDS, t);
95 return 0;
96 }
97 }
98
99 /* okay, try the PB1200 then */
100 bcsr_init(PB1200_BCSR_PHYS_ADDR,
101 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
102 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
103 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
104 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
105 unsigned short t = bcsr_read(BCSR_HEXLEDS);
106 bcsr_write(BCSR_HEXLEDS, ~t);
107 if (bcsr_read(BCSR_HEXLEDS) != t) {
108 bcsr_write(BCSR_HEXLEDS, t);
109 return 0;
110 }
111 }
112
113 return 1; /* it's neither */
114 }
115
116 int __init db1200_board_setup(void)
117 {
118 unsigned short whoami;
119
120 if (db1200_detect_board())
121 return -ENODEV;
122
123 whoami = bcsr_read(BCSR_WHOAMI);
124 switch (BCSR_WHOAMI_BOARD(whoami)) {
125 case BCSR_WHOAMI_PB1200_DDR1:
126 case BCSR_WHOAMI_PB1200_DDR2:
127 case BCSR_WHOAMI_DB1200:
128 break;
129 default:
130 return -ENODEV;
131 }
132
133 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
134 " Board-ID %d Daughtercard ID %d\n", get_system_type(),
135 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
136
137 return 0;
138 }
139
140 /******************************************************************************/
141
142 static u64 au1200_all_dmamask = DMA_BIT_MASK(32);
143
144 static struct mtd_partition db1200_spiflash_parts[] = {
145 {
146 .name = "spi_flash",
147 .offset = 0,
148 .size = MTDPART_SIZ_FULL,
149 },
150 };
151
152 static struct flash_platform_data db1200_spiflash_data = {
153 .name = "s25fl001",
154 .parts = db1200_spiflash_parts,
155 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts),
156 .type = "m25p10",
157 };
158
159 static struct spi_board_info db1200_spi_devs[] __initdata = {
160 {
161 /* TI TMP121AIDBVR temp sensor */
162 .modalias = "tmp121",
163 .max_speed_hz = 2000000,
164 .bus_num = 0,
165 .chip_select = 0,
166 .mode = 0,
167 },
168 {
169 /* Spansion S25FL001D0FMA SPI flash */
170 .modalias = "m25p80",
171 .max_speed_hz = 50000000,
172 .bus_num = 0,
173 .chip_select = 1,
174 .mode = 0,
175 .platform_data = &db1200_spiflash_data,
176 },
177 };
178
179 static struct i2c_board_info db1200_i2c_devs[] __initdata = {
180 { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */
181 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
182 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */
183 };
184
185 /**********************************************************************/
186
187 static void au1200_nand_cmd_ctrl(struct nand_chip *this, int cmd,
188 unsigned int ctrl)
189 {
190 unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W;
191
192 ioaddr &= 0xffffff00;
193
194 if (ctrl & NAND_CLE) {
195 ioaddr += MEM_STNAND_CMD;
196 } else if (ctrl & NAND_ALE) {
197 ioaddr += MEM_STNAND_ADDR;
198 } else {
199 /* assume we want to r/w real data by default */
200 ioaddr += MEM_STNAND_DATA;
201 }
202 this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr;
203 if (cmd != NAND_CMD_NONE) {
204 __raw_writeb(cmd, this->legacy.IO_ADDR_W);
205 wmb();
206 }
207 }
208
209 static int au1200_nand_device_ready(struct nand_chip *this)
210 {
211 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
212 }
213
214 static struct mtd_partition db1200_nand_parts[] = {
215 {
216 .name = "NAND FS 0",
217 .offset = 0,
218 .size = 8 * 1024 * 1024,
219 },
220 {
221 .name = "NAND FS 1",
222 .offset = MTDPART_OFS_APPEND,
223 .size = MTDPART_SIZ_FULL
224 },
225 };
226
227 struct platform_nand_data db1200_nand_platdata = {
228 .chip = {
229 .nr_chips = 1,
230 .chip_offset = 0,
231 .nr_partitions = ARRAY_SIZE(db1200_nand_parts),
232 .partitions = db1200_nand_parts,
233 .chip_delay = 20,
234 },
235 .ctrl = {
236 .dev_ready = au1200_nand_device_ready,
237 .cmd_ctrl = au1200_nand_cmd_ctrl,
238 },
239 };
240
241 static struct resource db1200_nand_res[] = {
242 [0] = {
243 .start = DB1200_NAND_PHYS_ADDR,
244 .end = DB1200_NAND_PHYS_ADDR + 0xff,
245 .flags = IORESOURCE_MEM,
246 },
247 };
248
249 static struct platform_device db1200_nand_dev = {
250 .name = "gen_nand",
251 .num_resources = ARRAY_SIZE(db1200_nand_res),
252 .resource = db1200_nand_res,
253 .id = -1,
254 .dev = {
255 .platform_data = &db1200_nand_platdata,
256 }
257 };
258
259 /**********************************************************************/
260
261 static struct smc91x_platdata db1200_eth_data = {
262 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
263 .leda = RPC_LED_100_10,
264 .ledb = RPC_LED_TX_RX,
265 };
266
267 static struct resource db1200_eth_res[] = {
268 [0] = {
269 .start = DB1200_ETH_PHYS_ADDR,
270 .end = DB1200_ETH_PHYS_ADDR + 0xf,
271 .flags = IORESOURCE_MEM,
272 },
273 [1] = {
274 .start = DB1200_ETH_INT,
275 .end = DB1200_ETH_INT,
276 .flags = IORESOURCE_IRQ,
277 },
278 };
279
280 static struct platform_device db1200_eth_dev = {
281 .dev = {
282 .platform_data = &db1200_eth_data,
283 },
284 .name = "smc91x",
285 .id = -1,
286 .num_resources = ARRAY_SIZE(db1200_eth_res),
287 .resource = db1200_eth_res,
288 };
289
290 /**********************************************************************/
291
292 static struct pata_platform_info db1200_ide_info = {
293 .ioport_shift = DB1200_IDE_REG_SHIFT,
294 };
295
296 #define IDE_ALT_START (14 << DB1200_IDE_REG_SHIFT)
297 static struct resource db1200_ide_res[] = {
298 [0] = {
299 .start = DB1200_IDE_PHYS_ADDR,
300 .end = DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1,
301 .flags = IORESOURCE_MEM,
302 },
303 [1] = {
304 .start = DB1200_IDE_PHYS_ADDR + IDE_ALT_START,
305 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
306 .flags = IORESOURCE_MEM,
307 },
308 [2] = {
309 .start = DB1200_IDE_INT,
310 .end = DB1200_IDE_INT,
311 .flags = IORESOURCE_IRQ,
312 },
313 };
314
315 static struct platform_device db1200_ide_dev = {
316 .name = "pata_platform",
317 .id = 0,
318 .dev = {
319 .dma_mask = &au1200_all_dmamask,
320 .coherent_dma_mask = DMA_BIT_MASK(32),
321 .platform_data = &db1200_ide_info,
322 },
323 .num_resources = ARRAY_SIZE(db1200_ide_res),
324 .resource = db1200_ide_res,
325 };
326
327 /**********************************************************************/
328
329 #ifdef CONFIG_MMC_AU1X
330 /* SD carddetects: they're supposed to be edge-triggered, but ack
331 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one
332 * is disabled and its counterpart enabled. The 200ms timeout is
333 * because the carddetect usually triggers twice, after debounce.
334 */
335 static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
336 {
337 disable_irq_nosync(irq);
338 return IRQ_WAKE_THREAD;
339 }
340
341 static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr)
342 {
343 mmc_detect_change(ptr, msecs_to_jiffies(200));
344
345 msleep(100); /* debounce */
346 if (irq == DB1200_SD0_INSERT_INT)
347 enable_irq(DB1200_SD0_EJECT_INT);
348 else
349 enable_irq(DB1200_SD0_INSERT_INT);
350
351 return IRQ_HANDLED;
352 }
353
354 static int db1200_mmc_cd_setup(void *mmc_host, int en)
355 {
356 int ret;
357
358 if (en) {
359 ret = request_threaded_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
360 db1200_mmc_cdfn, 0, "sd_insert", mmc_host);
361 if (ret)
362 goto out;
363
364 ret = request_threaded_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
365 db1200_mmc_cdfn, 0, "sd_eject", mmc_host);
366 if (ret) {
367 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
368 goto out;
369 }
370
371 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
372 enable_irq(DB1200_SD0_EJECT_INT);
373 else
374 enable_irq(DB1200_SD0_INSERT_INT);
375
376 } else {
377 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
378 free_irq(DB1200_SD0_EJECT_INT, mmc_host);
379 }
380 ret = 0;
381 out:
382 return ret;
383 }
384
385 static void db1200_mmc_set_power(void *mmc_host, int state)
386 {
387 if (state) {
388 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
389 msleep(400); /* stabilization time */
390 } else
391 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
392 }
393
394 static int db1200_mmc_card_readonly(void *mmc_host)
395 {
396 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
397 }
398
399 static int db1200_mmc_card_inserted(void *mmc_host)
400 {
401 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
402 }
403
404 static void db1200_mmcled_set(struct led_classdev *led,
405 enum led_brightness brightness)
406 {
407 if (brightness != LED_OFF)
408 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
409 else
410 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
411 }
412
413 static struct led_classdev db1200_mmc_led = {
414 .brightness_set = db1200_mmcled_set,
415 };
416
417 /* -- */
418
419 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
420 {
421 disable_irq_nosync(irq);
422 return IRQ_WAKE_THREAD;
423 }
424
425 static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr)
426 {
427 mmc_detect_change(ptr, msecs_to_jiffies(200));
428
429 msleep(100); /* debounce */
430 if (irq == PB1200_SD1_INSERT_INT)
431 enable_irq(PB1200_SD1_EJECT_INT);
432 else
433 enable_irq(PB1200_SD1_INSERT_INT);
434
435 return IRQ_HANDLED;
436 }
437
438 static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
439 {
440 int ret;
441
442 if (en) {
443 ret = request_threaded_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd,
444 pb1200_mmc1_cdfn, 0, "sd1_insert", mmc_host);
445 if (ret)
446 goto out;
447
448 ret = request_threaded_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd,
449 pb1200_mmc1_cdfn, 0, "sd1_eject", mmc_host);
450 if (ret) {
451 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
452 goto out;
453 }
454
455 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
456 enable_irq(PB1200_SD1_EJECT_INT);
457 else
458 enable_irq(PB1200_SD1_INSERT_INT);
459
460 } else {
461 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
462 free_irq(PB1200_SD1_EJECT_INT, mmc_host);
463 }
464 ret = 0;
465 out:
466 return ret;
467 }
468
469 static void pb1200_mmc1led_set(struct led_classdev *led,
470 enum led_brightness brightness)
471 {
472 if (brightness != LED_OFF)
473 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
474 else
475 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
476 }
477
478 static struct led_classdev pb1200_mmc1_led = {
479 .brightness_set = pb1200_mmc1led_set,
480 };
481
482 static void pb1200_mmc1_set_power(void *mmc_host, int state)
483 {
484 if (state) {
485 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
486 msleep(400); /* stabilization time */
487 } else
488 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
489 }
490
491 static int pb1200_mmc1_card_readonly(void *mmc_host)
492 {
493 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
494 }
495
496 static int pb1200_mmc1_card_inserted(void *mmc_host)
497 {
498 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
499 }
500
501
502 static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
503 [0] = {
504 .cd_setup = db1200_mmc_cd_setup,
505 .set_power = db1200_mmc_set_power,
506 .card_inserted = db1200_mmc_card_inserted,
507 .card_readonly = db1200_mmc_card_readonly,
508 .led = &db1200_mmc_led,
509 },
510 [1] = {
511 .cd_setup = pb1200_mmc1_cd_setup,
512 .set_power = pb1200_mmc1_set_power,
513 .card_inserted = pb1200_mmc1_card_inserted,
514 .card_readonly = pb1200_mmc1_card_readonly,
515 .led = &pb1200_mmc1_led,
516 },
517 };
518
519 static struct resource au1200_mmc0_resources[] = {
520 [0] = {
521 .start = AU1100_SD0_PHYS_ADDR,
522 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
523 .flags = IORESOURCE_MEM,
524 },
525 [1] = {
526 .start = AU1200_SD_INT,
527 .end = AU1200_SD_INT,
528 .flags = IORESOURCE_IRQ,
529 },
530 [2] = {
531 .start = AU1200_DSCR_CMD0_SDMS_TX0,
532 .end = AU1200_DSCR_CMD0_SDMS_TX0,
533 .flags = IORESOURCE_DMA,
534 },
535 [3] = {
536 .start = AU1200_DSCR_CMD0_SDMS_RX0,
537 .end = AU1200_DSCR_CMD0_SDMS_RX0,
538 .flags = IORESOURCE_DMA,
539 }
540 };
541
542 static struct platform_device db1200_mmc0_dev = {
543 .name = "au1xxx-mmc",
544 .id = 0,
545 .dev = {
546 .dma_mask = &au1200_all_dmamask,
547 .coherent_dma_mask = DMA_BIT_MASK(32),
548 .platform_data = &db1200_mmc_platdata[0],
549 },
550 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
551 .resource = au1200_mmc0_resources,
552 };
553
554 static struct resource au1200_mmc1_res[] = {
555 [0] = {
556 .start = AU1100_SD1_PHYS_ADDR,
557 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
558 .flags = IORESOURCE_MEM,
559 },
560 [1] = {
561 .start = AU1200_SD_INT,
562 .end = AU1200_SD_INT,
563 .flags = IORESOURCE_IRQ,
564 },
565 [2] = {
566 .start = AU1200_DSCR_CMD0_SDMS_TX1,
567 .end = AU1200_DSCR_CMD0_SDMS_TX1,
568 .flags = IORESOURCE_DMA,
569 },
570 [3] = {
571 .start = AU1200_DSCR_CMD0_SDMS_RX1,
572 .end = AU1200_DSCR_CMD0_SDMS_RX1,
573 .flags = IORESOURCE_DMA,
574 }
575 };
576
577 static struct platform_device pb1200_mmc1_dev = {
578 .name = "au1xxx-mmc",
579 .id = 1,
580 .dev = {
581 .dma_mask = &au1200_all_dmamask,
582 .coherent_dma_mask = DMA_BIT_MASK(32),
583 .platform_data = &db1200_mmc_platdata[1],
584 },
585 .num_resources = ARRAY_SIZE(au1200_mmc1_res),
586 .resource = au1200_mmc1_res,
587 };
588 #endif /* CONFIG_MMC_AU1X */
589
590 /**********************************************************************/
591
592 static int db1200fb_panel_index(void)
593 {
594 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
595 }
596
597 static int db1200fb_panel_init(void)
598 {
599 /* Apply power */
600 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
601 BCSR_BOARD_LCDBL);
602 return 0;
603 }
604
605 static int db1200fb_panel_shutdown(void)
606 {
607 /* Remove power */
608 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
609 BCSR_BOARD_LCDBL, 0);
610 return 0;
611 }
612
613 static struct au1200fb_platdata db1200fb_pd = {
614 .panel_index = db1200fb_panel_index,
615 .panel_init = db1200fb_panel_init,
616 .panel_shutdown = db1200fb_panel_shutdown,
617 };
618
619 static struct resource au1200_lcd_res[] = {
620 [0] = {
621 .start = AU1200_LCD_PHYS_ADDR,
622 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
623 .flags = IORESOURCE_MEM,
624 },
625 [1] = {
626 .start = AU1200_LCD_INT,
627 .end = AU1200_LCD_INT,
628 .flags = IORESOURCE_IRQ,
629 }
630 };
631
632 static struct platform_device au1200_lcd_dev = {
633 .name = "au1200-lcd",
634 .id = 0,
635 .dev = {
636 .dma_mask = &au1200_all_dmamask,
637 .coherent_dma_mask = DMA_BIT_MASK(32),
638 .platform_data = &db1200fb_pd,
639 },
640 .num_resources = ARRAY_SIZE(au1200_lcd_res),
641 .resource = au1200_lcd_res,
642 };
643
644 /**********************************************************************/
645
646 static struct resource au1200_psc0_res[] = {
647 [0] = {
648 .start = AU1550_PSC0_PHYS_ADDR,
649 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
650 .flags = IORESOURCE_MEM,
651 },
652 [1] = {
653 .start = AU1200_PSC0_INT,
654 .end = AU1200_PSC0_INT,
655 .flags = IORESOURCE_IRQ,
656 },
657 [2] = {
658 .start = AU1200_DSCR_CMD0_PSC0_TX,
659 .end = AU1200_DSCR_CMD0_PSC0_TX,
660 .flags = IORESOURCE_DMA,
661 },
662 [3] = {
663 .start = AU1200_DSCR_CMD0_PSC0_RX,
664 .end = AU1200_DSCR_CMD0_PSC0_RX,
665 .flags = IORESOURCE_DMA,
666 },
667 };
668
669 static struct platform_device db1200_i2c_dev = {
670 .name = "au1xpsc_smbus",
671 .id = 0, /* bus number */
672 .num_resources = ARRAY_SIZE(au1200_psc0_res),
673 .resource = au1200_psc0_res,
674 };
675
676 static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
677 {
678 if (cs)
679 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
680 else
681 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
682 }
683
684 static struct au1550_spi_info db1200_spi_platdata = {
685 .mainclk_hz = 50000000, /* PSC0 clock */
686 .num_chipselect = 2,
687 .activate_cs = db1200_spi_cs_en,
688 };
689
690 static struct platform_device db1200_spi_dev = {
691 .dev = {
692 .dma_mask = &au1200_all_dmamask,
693 .coherent_dma_mask = DMA_BIT_MASK(32),
694 .platform_data = &db1200_spi_platdata,
695 },
696 .name = "au1550-spi",
697 .id = 0, /* bus number */
698 .num_resources = ARRAY_SIZE(au1200_psc0_res),
699 .resource = au1200_psc0_res,
700 };
701
702 static struct resource au1200_psc1_res[] = {
703 [0] = {
704 .start = AU1550_PSC1_PHYS_ADDR,
705 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
706 .flags = IORESOURCE_MEM,
707 },
708 [1] = {
709 .start = AU1200_PSC1_INT,
710 .end = AU1200_PSC1_INT,
711 .flags = IORESOURCE_IRQ,
712 },
713 [2] = {
714 .start = AU1200_DSCR_CMD0_PSC1_TX,
715 .end = AU1200_DSCR_CMD0_PSC1_TX,
716 .flags = IORESOURCE_DMA,
717 },
718 [3] = {
719 .start = AU1200_DSCR_CMD0_PSC1_RX,
720 .end = AU1200_DSCR_CMD0_PSC1_RX,
721 .flags = IORESOURCE_DMA,
722 },
723 };
724
725 /* AC97 or I2S device */
726 static struct platform_device db1200_audio_dev = {
727 /* name assigned later based on switch setting */
728 .id = 1, /* PSC ID */
729 .num_resources = ARRAY_SIZE(au1200_psc1_res),
730 .resource = au1200_psc1_res,
731 };
732
733 /* DB1200 ASoC card device */
734 static struct platform_device db1200_sound_dev = {
735 /* name assigned later based on switch setting */
736 .id = 1, /* PSC ID */
737 .dev = {
738 .dma_mask = &au1200_all_dmamask,
739 .coherent_dma_mask = DMA_BIT_MASK(32),
740 },
741 };
742
743 static struct platform_device db1200_stac_dev = {
744 .name = "ac97-codec",
745 .id = 1, /* on PSC1 */
746 };
747
748 static struct platform_device db1200_audiodma_dev = {
749 .name = "au1xpsc-pcm",
750 .id = 1, /* PSC ID */
751 };
752
753 static struct platform_device *db1200_devs[] __initdata = {
754 NULL, /* PSC0, selected by S6.8 */
755 &db1200_ide_dev,
756 #ifdef CONFIG_MMC_AU1X
757 &db1200_mmc0_dev,
758 #endif
759 &au1200_lcd_dev,
760 &db1200_eth_dev,
761 &db1200_nand_dev,
762 &db1200_audiodma_dev,
763 &db1200_audio_dev,
764 &db1200_stac_dev,
765 &db1200_sound_dev,
766 };
767
768 static struct platform_device *pb1200_devs[] __initdata = {
769 #ifdef CONFIG_MMC_AU1X
770 &pb1200_mmc1_dev,
771 #endif
772 };
773
774 /* Some peripheral base addresses differ on the PB1200 */
775 static int __init pb1200_res_fixup(void)
776 {
777 /* CPLD Revs earlier than 4 cause problems */
778 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
779 printk(KERN_ERR "WARNING!!!\n");
780 printk(KERN_ERR "WARNING!!!\n");
781 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
782 printk(KERN_ERR "the board updated to latest revisions.\n");
783 printk(KERN_ERR "This software will not work reliably\n");
784 printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
785 printk(KERN_ERR "WARNING!!!\n");
786 printk(KERN_ERR "WARNING!!!\n");
787 return 1;
788 }
789
790 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
791 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff;
792 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
793 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
794 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
795 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff;
796 return 0;
797 }
798
799 int __init db1200_dev_setup(void)
800 {
801 unsigned long pfc;
802 unsigned short sw;
803 int swapped, bid;
804 struct clk *c;
805
806 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
807 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
808 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
809 if (pb1200_res_fixup())
810 return -ENODEV;
811 }
812
813 /* GPIO7 is low-level triggered CPLD cascade */
814 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
815 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
816
817 /* SMBus/SPI on PSC0, Audio on PSC1 */
818 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
819 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
820 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
821 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
822 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
823
824 /* get 50MHz for I2C driver on PSC0 */
825 c = clk_get(NULL, "psc0_intclk");
826 if (!IS_ERR(c)) {
827 pfc = clk_round_rate(c, 50000000);
828 if ((pfc < 1) || (abs(50000000 - pfc) > 2500000))
829 pr_warn("DB1200: can't get I2C close to 50MHz\n");
830 else
831 clk_set_rate(c, pfc);
832 clk_prepare_enable(c);
833 clk_put(c);
834 }
835
836 /* insert/eject pairs: one of both is always screaming. To avoid
837 * issues they must not be automatically enabled when initially
838 * requested.
839 */
840 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
841 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
842 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
843 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
844 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
845 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
846
847 i2c_register_board_info(0, db1200_i2c_devs,
848 ARRAY_SIZE(db1200_i2c_devs));
849 spi_register_board_info(db1200_spi_devs,
850 ARRAY_SIZE(db1200_spi_devs));
851
852 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
853 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
854 * or S12 on the PB1200.
855 */
856
857 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however
858 * this pin is claimed by PSC0 (unused though, but pinmux doesn't
859 * allow to free it without crippling the SPI interface).
860 * As a result, in SPI mode, OTG simply won't work (PSC0 uses
861 * it as an input pin which is pulled high on the boards).
862 */
863 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
864
865 /* switch off OTG VBUS supply */
866 gpio_request(215, "otg-vbus");
867 gpio_direction_output(215, 1);
868
869 printk(KERN_INFO "%s device configuration:\n", get_system_type());
870
871 sw = bcsr_read(BCSR_SWITCHES);
872 if (sw & BCSR_SWITCHES_DIP_8) {
873 db1200_devs[0] = &db1200_i2c_dev;
874 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
875
876 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */
877
878 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
879 printk(KERN_INFO " OTG port VBUS supply available!\n");
880 } else {
881 db1200_devs[0] = &db1200_spi_dev;
882 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
883
884 pfc |= (1 << 17); /* PSC0 owns GPIO215 */
885
886 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
887 printk(KERN_INFO " OTG port VBUS supply disabled\n");
888 }
889 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
890
891 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
892 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
893 */
894 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
895 if (sw == BCSR_SWITCHES_DIP_8) {
896 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
897 db1200_audio_dev.name = "au1xpsc_i2s";
898 db1200_sound_dev.name = "db1200-i2s";
899 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
900 } else {
901 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
902 db1200_audio_dev.name = "au1xpsc_ac97";
903 db1200_sound_dev.name = "db1200-ac97";
904 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
905 }
906
907 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
908 __raw_writel(PSC_SEL_CLK_SERCLK,
909 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
910 wmb();
911
912 db1x_register_pcmcia_socket(
913 AU1000_PCMCIA_ATTR_PHYS_ADDR,
914 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
915 AU1000_PCMCIA_MEM_PHYS_ADDR,
916 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
917 AU1000_PCMCIA_IO_PHYS_ADDR,
918 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
919 DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
920 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
921
922 db1x_register_pcmcia_socket(
923 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
924 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
925 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
926 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
927 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
928 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
929 DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
930 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
931
932 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
933 db1x_register_norflash(64 << 20, 2, swapped);
934
935 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
936
937 /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */
938 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
939 (bid == BCSR_WHOAMI_PB1200_DDR2))
940 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
941
942 return 0;
943 }
944
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