1 // SPDX-License-Identifier: GPL-2.0
2 /* OCTEON 3XXX DTS common parts. */
3
4 /dts-v1/;
5
6 / {
7 compatible = "cavium,octeon-3860";
8 #address-cells = <2>;
9 #size-cells = <2>;
10 interrupt-parent = <&ciu>;
11
12 soc@0 {
13 compatible = "simple-bus";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 ranges; /* Direct mapping */
17
18 ciu: interrupt-controller@1070000000000 {
19 compatible = "cavium,octeon-3860-ciu";
20 interrupt-controller;
21 /* Interrupts are specified by two parts:
22 * 1) Controller register (0 or 1)
23 * 2) Bit within the register (0..63)
24 */
25 #interrupt-cells = <2>;
26 reg = <0x10700 0x00000000 0x0 0x7000>;
27 };
28
29 gpio: gpio-controller@1070000000800 {
30 #gpio-cells = <2>;
31 compatible = "cavium,octeon-3860-gpio";
32 reg = <0x10700 0x00000800 0x0 0x100>;
33 gpio-controller;
34 /* Interrupts are specified by two parts:
35 * 1) GPIO pin number (0..15)
36 * 2) Triggering (1 - edge rising
37 * 2 - edge falling
38 * 4 - level active high
39 * 8 - level active low)
40 */
41 interrupt-controller;
42 #interrupt-cells = <2>;
43 /* The GPIO pin connect to 16 consecutive CUI bits */
44 interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
45 <0 20>, <0 21>, <0 22>, <0 23>,
46 <0 24>, <0 25>, <0 26>, <0 27>,
47 <0 28>, <0 29>, <0 30>, <0 31>;
48 };
49
50 smi0: mdio@1180000001800 {
51 compatible = "cavium,octeon-3860-mdio";
52 #address-cells = <1>;
53 #size-cells = <0>;
54 reg = <0x11800 0x00001800 0x0 0x40>;
55 };
56
57 pip: pip@11800a0000000 {
58 compatible = "cavium,octeon-3860-pip";
59 #address-cells = <1>;
60 #size-cells = <0>;
61 reg = <0x11800 0xa0000000 0x0 0x2000>;
62
63 interface@0 {
64 compatible = "cavium,octeon-3860-pip-interface";
65 #address-cells = <1>;
66 #size-cells = <0>;
67 reg = <0>; /* interface */
68
69 ethernet@0 {
70 compatible = "cavium,octeon-3860-pip-port";
71 reg = <0x0>; /* Port */
72 local-mac-address = [ 00 00 00 00 00 00 ];
73 };
74 ethernet@1 {
75 compatible = "cavium,octeon-3860-pip-port";
76 reg = <0x1>; /* Port */
77 local-mac-address = [ 00 00 00 00 00 00 ];
78 };
79 ethernet@2 {
80 compatible = "cavium,octeon-3860-pip-port";
81 reg = <0x2>; /* Port */
82 local-mac-address = [ 00 00 00 00 00 00 ];
83 };
84 };
85
86 interface@1 {
87 compatible = "cavium,octeon-3860-pip-interface";
88 #address-cells = <1>;
89 #size-cells = <0>;
90 reg = <1>; /* interface */
91 };
92 };
93
94 twsi0: i2c@1180000001000 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 compatible = "cavium,octeon-3860-twsi";
98 reg = <0x11800 0x00001000 0x0 0x200>;
99 interrupts = <0 45>;
100 clock-frequency = <100000>;
101 };
102
103 uart0: serial@1180000000800 {
104 compatible = "cavium,octeon-3860-uart","ns16550";
105 reg = <0x11800 0x00000800 0x0 0x400>;
106 clock-frequency = <0>;
107 current-speed = <115200>;
108 reg-shift = <3>;
109 interrupts = <0 34>;
110 };
111
112 bootbus: bootbus@1180000000000 {
113 compatible = "cavium,octeon-3860-bootbus";
114 reg = <0x11800 0x00000000 0x0 0x200>;
115 /* The chip select number and offset */
116 #address-cells = <2>;
117 /* The size of the chip select region */
118 #size-cells = <1>;
119 ranges = <0 0 0x0 0x1f400000 0xc00000>,
120 <1 0 0x10000 0x30000000 0>,
121 <2 0 0x10000 0x40000000 0>,
122 <3 0 0x10000 0x50000000 0>,
123 <4 0 0x0 0x1d020000 0x10000>,
124 <5 0 0x0 0x1d040000 0x10000>,
125 <6 0 0x0 0x1d050000 0x10000>,
126 <7 0 0x10000 0x90000000 0>;
127
128 cavium,cs-config@0 {
129 compatible = "cavium,octeon-3860-bootbus-config";
130 cavium,cs-index = <0>;
131 cavium,t-adr = <20>;
132 cavium,t-ce = <60>;
133 cavium,t-oe = <60>;
134 cavium,t-we = <45>;
135 cavium,t-rd-hld = <35>;
136 cavium,t-wr-hld = <45>;
137 cavium,t-pause = <0>;
138 cavium,t-wait = <0>;
139 cavium,t-page = <35>;
140 cavium,t-rd-dly = <0>;
141
142 cavium,pages = <0>;
143 cavium,bus-width = <8>;
144 };
145 cavium,cs-config@4 {
146 compatible = "cavium,octeon-3860-bootbus-config";
147 cavium,cs-index = <4>;
148 cavium,t-adr = <320>;
149 cavium,t-ce = <320>;
150 cavium,t-oe = <320>;
151 cavium,t-we = <320>;
152 cavium,t-rd-hld = <320>;
153 cavium,t-wr-hld = <320>;
154 cavium,t-pause = <320>;
155 cavium,t-wait = <320>;
156 cavium,t-page = <320>;
157 cavium,t-rd-dly = <0>;
158
159 cavium,pages = <0>;
160 cavium,bus-width = <8>;
161 };
162 cavium,cs-config@5 {
163 compatible = "cavium,octeon-3860-bootbus-config";
164 cavium,cs-index = <5>;
165 cavium,t-adr = <5>;
166 cavium,t-ce = <300>;
167 cavium,t-oe = <125>;
168 cavium,t-we = <150>;
169 cavium,t-rd-hld = <100>;
170 cavium,t-wr-hld = <30>;
171 cavium,t-pause = <0>;
172 cavium,t-wait = <30>;
173 cavium,t-page = <320>;
174 cavium,t-rd-dly = <0>;
175
176 cavium,pages = <0>;
177 cavium,bus-width = <16>;
178 };
179 cavium,cs-config@6 {
180 compatible = "cavium,octeon-3860-bootbus-config";
181 cavium,cs-index = <6>;
182 cavium,t-adr = <5>;
183 cavium,t-ce = <300>;
184 cavium,t-oe = <270>;
185 cavium,t-we = <150>;
186 cavium,t-rd-hld = <100>;
187 cavium,t-wr-hld = <70>;
188 cavium,t-pause = <0>;
189 cavium,t-wait = <0>;
190 cavium,t-page = <320>;
191 cavium,t-rd-dly = <0>;
192
193 cavium,pages = <0>;
194 cavium,wait-mode;
195 cavium,bus-width = <16>;
196 };
197
198 flash0: nor@0,0 {
199 compatible = "cfi-flash";
200 reg = <0 0 0x800000>;
201 #address-cells = <1>;
202 #size-cells = <1>;
203 };
204 };
205
206 dma0: dma-engine@1180000000100 {
207 compatible = "cavium,octeon-5750-bootbus-dma";
208 reg = <0x11800 0x00000100 0x0 0x8>;
209 interrupts = <0 63>;
210 };
211
212 dma1: dma-engine@1180000000108 {
213 compatible = "cavium,octeon-5750-bootbus-dma";
214 reg = <0x11800 0x00000108 0x0 0x8>;
215 interrupts = <0 63>;
216 };
217
218 usbn: usbn@1180068000000 {
219 compatible = "cavium,octeon-5750-usbn";
220 reg = <0x11800 0x68000000 0x0 0x1000>;
221 ranges; /* Direct mapping */
222 #address-cells = <2>;
223 #size-cells = <2>;
224
225 usbc@16f0010000000 {
226 compatible = "cavium,octeon-5750-usbc";
227 reg = <0x16f00 0x10000000 0x0 0x80000>;
228 interrupts = <0 56>;
229 };
230 };
231 };
232 };
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