1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 /*
3 * Copyright 2024 Mobileye Vision Technologies Ltd.
4 */
5
6 #include <dt-bindings/interrupt-controller/mips-gic.h>
7
8 #include "eyeq6h-fixed-clocks.dtsi"
9
10 / {
11 #address-cells = <2>;
12 #size-cells = <2>;
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16 cpu@0 {
17 device_type = "cpu";
18 compatible = "img,i6500";
19 reg = <0>;
20 clocks = <&occ_cpu>;
21 };
22 };
23
24 aliases {
25 serial0 = &uart0;
26 };
27
28 cpu_intc: interrupt-controller {
29 compatible = "mti,cpu-interrupt-controller";
30 interrupt-controller;
31 #address-cells = <0>;
32 #interrupt-cells = <1>;
33 };
34
35 soc: soc {
36 compatible = "simple-bus";
37 #address-cells = <2>;
38 #size-cells = <2>;
39 ranges;
40
41 uart0: serial@d3331000 {
42 compatible = "arm,pl011", "arm,primecell";
43 reg = <0 0xd3331000 0x0 0x1000>;
44 reg-io-width = <4>;
45 interrupt-parent = <&gic>;
46 interrupts = <GIC_SHARED 43 IRQ_TYPE_LEVEL_HIGH>;
47 clocks = <&occ_periph_w>, <&occ_periph_w>;
48 clock-names = "uartclk", "apb_pclk";
49 };
50
51 pinctrl_west: pinctrl@d3337000 {
52 compatible = "pinctrl-single";
53 reg = <0x0 0xd3337000 0x0 0xb0>;
54 #pinctrl-cells = <1>;
55 pinctrl-single,register-width = <32>;
56 pinctrl-single,function-mask = <0xffff>;
57 };
58
59 pinctrl_east: pinctrl@d3357000 {
60 compatible = "pinctrl-single";
61 reg = <0x0 0xd3357000 0x0 0xb0>;
62 #pinctrl-cells = <1>;
63 pinctrl-single,register-width = <32>;
64 pinctrl-single,function-mask = <0xffff>;
65 };
66
67 pinctrl_south: pinctrl@d8014000 {
68 compatible = "pinctrl-single";
69 reg = <0x0 0xd8014000 0x0 0xf8>;
70 #pinctrl-cells = <1>;
71 pinctrl-single,register-width = <32>;
72 pinctrl-single,function-mask = <0xffff>;
73 };
74
75 gic: interrupt-controller@f0920000 {
76 compatible = "mti,gic";
77 reg = <0x0 0xf0920000 0x0 0x20000>;
78 interrupt-controller;
79 #interrupt-cells = <3>;
80
81 /*
82 * Declare the interrupt-parent even though the mti,gic
83 * binding doesn't require it, such that the kernel can
84 * figure out that cpu_intc is the root interrupt
85 * controller & should be probed first.
86 */
87 interrupt-parent = <&cpu_intc>;
88
89 timer {
90 compatible = "mti,gic-timer";
91 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
92 clocks = <&occ_cpu>;
93 };
94 };
95 };
96 };
97
98 #include "eyeq6h-pins.dtsi"
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