1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2017 Microsemi Corporation */
3
4 / {
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mscc,ocelot";
8
9 cpus {
10 #address-cells = <1>;
11 #size-cells = <0>;
12
13 cpu@0 {
14 compatible = "mips,mips24KEc";
15 device_type = "cpu";
16 clocks = <&cpu_clk>;
17 reg = <0>;
18 };
19 };
20
21 aliases {
22 serial0 = &uart0;
23 };
24
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
30 };
31
32 cpu_clk: cpu-clock {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <500000000>;
36 };
37
38 ahb_clk: ahb-clk {
39 compatible = "fixed-factor-clock";
40 #clock-cells = <0>;
41 clocks = <&cpu_clk>;
42 clock-div = <2>;
43 clock-mult = <1>;
44 };
45
46 ahb@70000000 {
47 compatible = "simple-bus";
48 #address-cells = <1>;
49 #size-cells = <1>;
50 ranges = <0 0x70000000 0x2000000>;
51
52 interrupt-parent = <&intc>;
53
54 cpu_ctrl: syscon@0 {
55 compatible = "mscc,ocelot-cpu-syscon", "syscon";
56 reg = <0x0 0x2c>;
57 };
58
59 intc: interrupt-controller@70 {
60 compatible = "mscc,ocelot-icpu-intr";
61 reg = <0x70 0x70>;
62 #interrupt-cells = <1>;
63 interrupt-controller;
64 interrupt-parent = <&cpuintc>;
65 interrupts = <2>;
66 };
67
68 uart0: serial@100000 {
69 pinctrl-0 = <&uart_pins>;
70 pinctrl-names = "default";
71 compatible = "ns16550a";
72 reg = <0x100000 0x20>;
73 interrupts = <6>;
74 clocks = <&ahb_clk>;
75 reg-io-width = <4>;
76 reg-shift = <2>;
77
78 status = "disabled";
79 };
80
81 i2c: i2c@100400 {
82 compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
83 pinctrl-0 = <&i2c_pins>;
84 pinctrl-names = "default";
85 reg = <0x100400 0x100>, <0x198 0x8>;
86 #address-cells = <1>;
87 #size-cells = <0>;
88 interrupts = <8>;
89 clocks = <&ahb_clk>;
90
91 status = "disabled";
92 };
93
94 uart2: serial@100800 {
95 pinctrl-0 = <&uart2_pins>;
96 pinctrl-names = "default";
97 compatible = "ns16550a";
98 reg = <0x100800 0x20>;
99 interrupts = <7>;
100 clocks = <&ahb_clk>;
101 reg-io-width = <4>;
102 reg-shift = <2>;
103
104 status = "disabled";
105 };
106
107 spi: spi@101000 {
108 compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
109 #address-cells = <1>;
110 #size-cells = <0>;
111 reg = <0x101000 0x100>, <0x3c 0x18>;
112 interrupts = <9>;
113 clocks = <&ahb_clk>;
114
115 status = "disabled";
116 };
117
118 switch@1010000 {
119 compatible = "mscc,vsc7514-switch";
120 reg = <0x1010000 0x10000>,
121 <0x1030000 0x10000>,
122 <0x1080000 0x100>,
123 <0x10e0000 0x10000>,
124 <0x11e0000 0x100>,
125 <0x11f0000 0x100>,
126 <0x1200000 0x100>,
127 <0x1210000 0x100>,
128 <0x1220000 0x100>,
129 <0x1230000 0x100>,
130 <0x1240000 0x100>,
131 <0x1250000 0x100>,
132 <0x1260000 0x100>,
133 <0x1270000 0x100>,
134 <0x1280000 0x100>,
135 <0x1800000 0x80000>,
136 <0x1880000 0x10000>,
137 <0x1040000 0x10000>,
138 <0x1050000 0x10000>,
139 <0x1060000 0x10000>,
140 <0x1a0 0x1c4>;
141 reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
142 "port2", "port3", "port4", "port5", "port6",
143 "port7", "port8", "port9", "port10", "qsys",
144 "ana", "s0", "s1", "s2", "fdma";
145 interrupts = <18 21 22 16>;
146 interrupt-names = "ptp_rdy", "xtr", "inj", "fdma";
147
148 ethernet-ports {
149 #address-cells = <1>;
150 #size-cells = <0>;
151
152 port0: port@0 {
153 reg = <0>;
154 status = "disabled";
155 };
156 port1: port@1 {
157 reg = <1>;
158 status = "disabled";
159 };
160 port2: port@2 {
161 reg = <2>;
162 status = "disabled";
163 };
164 port3: port@3 {
165 reg = <3>;
166 status = "disabled";
167 };
168 port4: port@4 {
169 reg = <4>;
170 status = "disabled";
171 };
172 port5: port@5 {
173 reg = <5>;
174 status = "disabled";
175 };
176 port6: port@6 {
177 reg = <6>;
178 status = "disabled";
179 };
180 port7: port@7 {
181 reg = <7>;
182 status = "disabled";
183 };
184 port8: port@8 {
185 reg = <8>;
186 status = "disabled";
187 };
188 port9: port@9 {
189 reg = <9>;
190 status = "disabled";
191 };
192 port10: port@10 {
193 reg = <10>;
194 status = "disabled";
195 };
196 };
197 };
198
199 reset@1070008 {
200 compatible = "mscc,ocelot-chip-reset";
201 reg = <0x1070008 0x4>;
202 };
203
204 gpio: pinctrl@1070034 {
205 compatible = "mscc,ocelot-pinctrl";
206 reg = <0x1070034 0x68>;
207 gpio-controller;
208 #gpio-cells = <2>;
209 gpio-ranges = <&gpio 0 0 22>;
210 interrupt-controller;
211 interrupts = <13>;
212 #interrupt-cells = <2>;
213
214 i2c_pins: i2c-pins {
215 pins = "GPIO_16", "GPIO_17";
216 function = "twi";
217 };
218
219 uart_pins: uart-pins {
220 pins = "GPIO_6", "GPIO_7";
221 function = "uart";
222 };
223
224 uart2_pins: uart2-pins {
225 pins = "GPIO_12", "GPIO_13";
226 function = "uart2";
227 };
228
229 miim1_pins: miim1-pins {
230 pins = "GPIO_14", "GPIO_15";
231 function = "miim";
232 };
233
234 };
235
236 mdio0: mdio@107009c {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "mscc,ocelot-miim";
240 reg = <0x107009c 0x24>, <0x10700f0 0x8>;
241 interrupts = <14>;
242 status = "disabled";
243
244 phy0: ethernet-phy@0 {
245 reg = <0>;
246 };
247 phy1: ethernet-phy@1 {
248 reg = <1>;
249 };
250 phy2: ethernet-phy@2 {
251 reg = <2>;
252 };
253 phy3: ethernet-phy@3 {
254 reg = <3>;
255 };
256 };
257
258 mdio1: mdio@10700c0 {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 compatible = "mscc,ocelot-miim";
262 reg = <0x10700c0 0x24>;
263 interrupts = <15>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&miim1_pins>;
266 status = "disabled";
267 };
268
269 hsio: syscon@10d0000 {
270 compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
271 reg = <0x10d0000 0x10000>;
272
273 serdes: serdes {
274 compatible = "mscc,vsc7514-serdes";
275 #phy-cells = <2>;
276 };
277 };
278 };
279 };
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