1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012-2013 Cavium Inc., All Rights Reserved.
7 *
8 * MD5/SHA1/SHA256/SHA512 instruction definitions added by
9 * Aaro Koskinen <aaro.koskinen@iki.fi>.
10 *
11 */
12 #ifndef __LINUX_OCTEON_CRYPTO_H
13 #define __LINUX_OCTEON_CRYPTO_H
14
15 #include <linux/sched.h>
16 #include <asm/mipsregs.h>
17
18 #define OCTEON_CR_OPCODE_PRIORITY 300
19
20 extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
21 extern void octeon_crypto_disable(struct octeon_cop2_state *state,
22 unsigned long flags);
23
24 /*
25 * Macros needed to implement MD5/SHA1/SHA256:
26 */
27
28 /*
29 * The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256).
30 */
31 #define write_octeon_64bit_hash_dword(value, index) \
32 do { \
33 __asm__ __volatile__ ( \
34 "dmtc2 %[rt],0x0048+" STR(index) \
35 : \
36 : [rt] "d" (cpu_to_be64(value))); \
37 } while (0)
38
39 /*
40 * The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256).
41 */
42 #define read_octeon_64bit_hash_dword(index) \
43 ({ \
44 __be64 __value; \
45 \
46 __asm__ __volatile__ ( \
47 "dmfc2 %[rt],0x0048+" STR(index) \
48 : [rt] "=d" (__value) \
49 : ); \
50 \
51 be64_to_cpu(__value); \
52 })
53
54 /*
55 * The index can be 0-6.
56 */
57 #define write_octeon_64bit_block_dword(value, index) \
58 do { \
59 __asm__ __volatile__ ( \
60 "dmtc2 %[rt],0x0040+" STR(index) \
61 : \
62 : [rt] "d" (cpu_to_be64(value))); \
63 } while (0)
64
65 /*
66 * The value is the final block dword (64-bit).
67 */
68 #define octeon_md5_start(value) \
69 do { \
70 __asm__ __volatile__ ( \
71 "dmtc2 %[rt],0x4047" \
72 : \
73 : [rt] "d" (cpu_to_be64(value))); \
74 } while (0)
75
76 /*
77 * The value is the final block dword (64-bit).
78 */
79 #define octeon_sha1_start(value) \
80 do { \
81 __asm__ __volatile__ ( \
82 "dmtc2 %[rt],0x4057" \
83 : \
84 : [rt] "d" (value)); \
85 } while (0)
86
87 /*
88 * The value is the final block dword (64-bit).
89 */
90 #define octeon_sha256_start(value) \
91 do { \
92 __asm__ __volatile__ ( \
93 "dmtc2 %[rt],0x404f" \
94 : \
95 : [rt] "d" (value)); \
96 } while (0)
97
98 /*
99 * Macros needed to implement SHA512:
100 */
101
102 /*
103 * The index can be 0-7.
104 */
105 #define write_octeon_64bit_hash_sha512(value, index) \
106 do { \
107 __asm__ __volatile__ ( \
108 "dmtc2 %[rt],0x0250+" STR(index) \
109 : \
110 : [rt] "d" (value)); \
111 } while (0)
112
113 /*
114 * The index can be 0-7.
115 */
116 #define read_octeon_64bit_hash_sha512(index) \
117 ({ \
118 u64 __value; \
119 \
120 __asm__ __volatile__ ( \
121 "dmfc2 %[rt],0x0250+" STR(index) \
122 : [rt] "=d" (__value) \
123 : ); \
124 \
125 __value; \
126 })
127
128 /*
129 * The index can be 0-14.
130 */
131 #define write_octeon_64bit_block_sha512(value, index) \
132 do { \
133 __asm__ __volatile__ ( \
134 "dmtc2 %[rt],0x0240+" STR(index) \
135 : \
136 : [rt] "d" (value)); \
137 } while (0)
138
139 /*
140 * The value is the final block word (64-bit).
141 */
142 #define octeon_sha512_start(value) \
143 do { \
144 __asm__ __volatile__ ( \
145 "dmtc2 %[rt],0x424f" \
146 : \
147 : [rt] "d" (value)); \
148 } while (0)
149
150 /*
151 * The value is the final block dword (64-bit).
152 */
153 #define octeon_sha1_start(value) \
154 do { \
155 __asm__ __volatile__ ( \
156 "dmtc2 %[rt],0x4057" \
157 : \
158 : [rt] "d" (value)); \
159 } while (0)
160
161 /*
162 * The value is the final block dword (64-bit).
163 */
164 #define octeon_sha256_start(value) \
165 do { \
166 __asm__ __volatile__ ( \
167 "dmtc2 %[rt],0x404f" \
168 : \
169 : [rt] "d" (value)); \
170 } while (0)
171
172 /*
173 * Macros needed to implement SHA512:
174 */
175
176 /*
177 * The index can be 0-7.
178 */
179 #define write_octeon_64bit_hash_sha512(value, index) \
180 do { \
181 __asm__ __volatile__ ( \
182 "dmtc2 %[rt],0x0250+" STR(index) \
183 : \
184 : [rt] "d" (value)); \
185 } while (0)
186
187 /*
188 * The index can be 0-7.
189 */
190 #define read_octeon_64bit_hash_sha512(index) \
191 ({ \
192 u64 __value; \
193 \
194 __asm__ __volatile__ ( \
195 "dmfc2 %[rt],0x0250+" STR(index) \
196 : [rt] "=d" (__value) \
197 : ); \
198 \
199 __value; \
200 })
201
202 /*
203 * The index can be 0-14.
204 */
205 #define write_octeon_64bit_block_sha512(value, index) \
206 do { \
207 __asm__ __volatile__ ( \
208 "dmtc2 %[rt],0x0240+" STR(index) \
209 : \
210 : [rt] "d" (value)); \
211 } while (0)
212
213 /*
214 * The value is the final block word (64-bit).
215 */
216 #define octeon_sha512_start(value) \
217 do { \
218 __asm__ __volatile__ ( \
219 "dmtc2 %[rt],0x424f" \
220 : \
221 : [rt] "d" (value)); \
222 } while (0)
223
224 #endif /* __LINUX_OCTEON_CRYPTO_H */
225
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